JPS6232660A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS6232660A JPS6232660A JP17192085A JP17192085A JPS6232660A JP S6232660 A JPS6232660 A JP S6232660A JP 17192085 A JP17192085 A JP 17192085A JP 17192085 A JP17192085 A JP 17192085A JP S6232660 A JPS6232660 A JP S6232660A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gas channel
- mesa
- dimensional electron
- electron gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000005530 etching Methods 0.000 claims abstract description 15
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 18
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 27
- 229910045601 alloy Inorganic materials 0.000 abstract description 11
- 239000000956 alloy Substances 0.000 abstract description 11
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 235000021419 vinegar Nutrition 0.000 description 1
- 239000000052 vinegar Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置及びその製造方法に関し、特に２
次元電子ガスチャンネル層を有する半導体装置の低接触
抵抗化を実現する技術に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a semiconductor device and a method for manufacturing the same.
The present invention relates to a technique for realizing low contact resistance of a semiconductor device having a dimensional electron gas channel layer.
従来のこの種の半導体装置にあっては、低抵抗性を再現
性良く達成することが困難であったが、本発明は、２次
元電子ガスチャンネル層とＮ″ＧａＡｓ層等の低抵抗半
導体層とを直接接触させることにより、低抵抗性を実現
したものである。In conventional semiconductor devices of this type, it has been difficult to achieve low resistance with good reproducibility, but the present invention provides a two-dimensional electron gas channel layer and a low resistance semiconductor layer such as an N''GaAs layer. Low resistance is achieved by bringing them into direct contact.
従来の半導体装置、例えばＨＥＭＴ （ＨｉｇｈあるＳ
ｉ等をドープしたｆｉ、１ＧａＡｓ層２を積層形成する
とともに、ソース、ドレイン電極 （オーミック電極）
３．４をｎ−ＡｌＧａＡｓ層２がらＧａＡｓ層１にかけ
て形成し、さらにｎ −Ａ Ｉ ＧａＡｓ層２上にゲー
ト電極５を形成した構成を有し°ζいる。Conventional semiconductor devices, such as HEMT (High S
Fi, 1GaAs layers 2 doped with i, etc. are laminated, and source and drain electrodes (ohmic electrodes) are formed.
3.4 is formed from the n-AlGaAs layer 2 to the GaAs layer 1, and the gate electrode 5 is further formed on the n-AI GaAs layer 2.
ｎ Ａ Ｉ ＧａＡｓ層１！ ２中のＳｉから放出さ
れた電子は、ｎ −Ａ Ｉ ＧａＡｓ層２との界面のＧ
ａ Ａ ｓ層ｌ側にたまって２次元電子ガスチャンネ
ル層６を形成する。n A I GaAs layer 1! The electrons emitted from the Si in the n-A I GaAs layer 2 are
The two-dimensional electron gas channel layer 6 is formed by accumulating on the side of the a As layer l.
ＧａＡｓ層１は高純度で不純物が少ないため、不純物と
電子との衝突による移動度低下が少なくなり、２次元電
子ガスチャンネル層６内における電子の移動度が大きい
ものとなる。ごのようなＨＥＭＴにおいて、オーミック
電極３，４は例えばＡｕＧｅ／Ｎｉ合金によって構成さ
れ、図示のような状態でオーミック電極と２次元電子ガ
スチャンネルＮ６との接触（オーミック接触）が行われ
る。Since the GaAs layer 1 has high purity and contains few impurities, the decrease in mobility due to collisions between impurities and electrons is reduced, and the mobility of electrons in the two-dimensional electron gas channel layer 6 is increased. In a HEMT such as this, the ohmic electrodes 3 and 4 are made of, for example, an AuGe/Ni alloy, and contact (ohmic contact) between the ohmic electrodes and the two-dimensional electron gas channel N6 is made in the state shown in the figure.
しかしながら従来のＨＥＭＴにあっては、ｎ −Ａ Ｉ
ＧａＡｓ層２中のＡｌがオーミック電極に与える影響
により、あるいは２次元電子ガスチャンネル層とオーミ
ックアロイ層との接触領域が不均一であったり、接触面
積が狭い等の原因によって、接触抵抗（寄生抵抗）が増
大して低抵抗性を再現性良く実現することを困難にして
いた。However, in conventional HEMT, n −A I
Contact resistance (parasitic resistance) may increase due to the influence of Al in the GaAs layer 2 on the ohmic electrode, or due to non-uniform or narrow contact areas between the two-dimensional electron gas channel layer and the ohmic alloy layer. ) increases, making it difficult to achieve low resistance with good reproducibility.
上述したように、従来技術には２次元電子ガスチャンネ
ル層とオーミックアロイ層との接触領域が不均一である
、接触面積が狭い等の原因によって、接触抵抗が大きく
なるという問題がある。As described above, the conventional technology has a problem in that the contact resistance increases due to non-uniform contact areas between the two-dimensional electron gas channel layer and the ohmic alloy layer, narrow contact areas, and the like.
本発明の目的は、このような問題を解決して接触抵抗の
低減化を達成することができる半導体装置及び製造方法
を提供するものである。An object of the present invention is to provide a semiconductor device and a manufacturing method that can solve such problems and reduce contact resistance.
本発明の半導体装置は、２次元電子ガスチャンネル層を
有する半導体装置において、上記２次元電子ガスチャン
ネル層の少なくとも一部分を表面に露出させてメサ状部
とし、該メサ状部の該２次元電子ガスチャンネル層に直
接接触させて形成した低抵抗半導体層を、ソース、ドレ
イン電極となるオーミック電極と該２次元電子ガスチャ
ンネル層との間に介在させて成ることによって上記目的
を達成することができる。The semiconductor device of the present invention is a semiconductor device having a two-dimensional electron gas channel layer, in which at least a portion of the two-dimensional electron gas channel layer is exposed on the surface to form a mesa-shaped portion, and the two-dimensional electron gas channel layer in the mesa-shaped portion is The above object can be achieved by interposing a low resistance semiconductor layer formed in direct contact with the channel layer between the two-dimensional electron gas channel layer and ohmic electrodes serving as source and drain electrodes.
また、本発明方法は、２次元電子ガスチャンネル層を有
する半導体装置をメサエッチして、側部に上記２次元電
子ガスチャンネル層の少なくとも一部分を露出させる工
程と、上記メサエッチングした基板上に低抵抗半導体層
をエピタキシャル成長させる工程と、メサ状部の上記低
抵抗半導体層を所定のマスクを用いてオーバーエツチン
グする工程と、上記マスクを用いてゲート電極を斜め蒸
着で形成する工程とを備えたことによって上記目的を達
成することができる。The method of the present invention also includes a step of mesa-etching a semiconductor device having a two-dimensional electron gas channel layer to expose at least a part of the two-dimensional electron gas channel layer on the side, and a step of mesa-etching a semiconductor device having a two-dimensional electron gas channel layer to expose at least a portion of the two-dimensional electron gas channel layer on the side; By comprising the steps of epitaxially growing a semiconductor layer, over-etching the low-resistance semiconductor layer in the mesa-shaped portion using a predetermined mask, and forming a gate electrode by oblique evaporation using the mask. The above purpose can be achieved.
すなわち本発明の半導体装置は、メサ状部の２次元電子
ガ、スチャンネル層に直接接触させて形成した低抵抗半
導体層を、ソース、ドレインとなるオーミック電極と該
２次元電子ガスチャンネル層との間に介在させたので、
低接触抵抗性を、再現性良く実現できる。That is, in the semiconductor device of the present invention, a low resistance semiconductor layer formed in direct contact with a two-dimensional electron gas channel layer in a mesa-shaped portion is connected to an ohmic electrode serving as a source and a drain and the two-dimensional electron gas channel layer. Because I intervened in between,
Low contact resistance can be achieved with good reproducibility.
また、本発明に係る製造方法は、低抵抗半導体層をエピ
タキシャル成長させ、かつゲート電極を斜め蒸着で形成
するので、上記の如き半導体装置を高性能で、かつ容易
に製造できる。Further, in the manufacturing method according to the present invention, a low-resistance semiconductor layer is epitaxially grown and a gate electrode is formed by oblique vapor deposition, so that the above semiconductor device can be easily manufactured with high performance.
以下本発明の一実施例を説明する。この実施例は、本発
明をＦＥＴ、特にＨＥＭＴであるＦＥＴに適用したもの
である。An embodiment of the present invention will be described below. In this embodiment, the present invention is applied to an FET, particularly an FET that is a HEMT.
第１図は本発明の一実施例に係る半導体装置としてのＨ
ＥＭＴの構成を示す説明図である。このＨＥＭＴは台形
状にメサエッチングされたＧａＡｓ層１およびｎ −Ａ
Ｉｔ ＧａＡｓ層２とから成るメサ状部と、ｎ ”Ｇ
ａＡｓ等の低抵抗半導体層２０と、オーミックアロイ層
（オーミック電極） １１．１２と、２次元電子ガスチ
ャンネル層（以下２ＤＥＣ層という）６と、。FIG. 1 shows an H as a semiconductor device according to an embodiment of the present invention.
It is an explanatory diagram showing the composition of EMT. This HEMT consists of a trapezoidal mesa-etched GaAs layer 1 and an n-A
A mesa-shaped portion consisting of an It GaAs layer 2 and an n ”G
A low resistance semiconductor layer 20 such as aAs, an ohmic alloy layer (ohmic electrode) 11, 12, and a two-dimensional electron gas channel layer (hereinafter referred to as 2DEC layer) 6.
ゲート電極１３とから成る。２ＤＥＧ層６の少なくとも
一部はメサ状部の側壁に露出され、低抵抗半導体層２０
は２ＤＥＧ層６の該露出部に直接接触するとともに、ソ
ース、ドレイン電極となるオーミックアロイ層１１．１
２と２ＤＥＧ層との間に位置している。It consists of a gate electrode 13. At least a portion of the 2DEG layer 6 is exposed on the sidewall of the mesa-shaped portion, and the low resistance semiconductor layer 20
The ohmic alloy layer 11.1 is in direct contact with the exposed portion of the 2DEG layer 6 and serves as the source and drain electrodes.
2 and the 2DEG layer.
第２図（イ）〜（ニ）は実施例の半導体装置の製造工程
の説明図である。第３図はこの製造工程を示すフロー図
である。FIGS. 2(A) to 2(D) are explanatory diagrams of the manufacturing process of the semiconductor device of the embodiment. FIG. 3 is a flow diagram showing this manufacturing process.
第２図（イ）は第１のＥｐ （エピタキシャル）工程を
示し、この工程は第３図の工程Ｉａに該当する。第２図
（イ）に示す如＜、Ｓｉ等からなる半導体基板１５上に
は不純物をトープしていないＧａＡｓＮ１及びｎ −Ａ
ｆｆＧａＡｓ層２が順次積層されている。FIG. 2(a) shows a first Ep (epitaxial) step, which corresponds to step Ia in FIG. 3. As shown in FIG. 2(A), on a semiconductor substrate 15 made of Si or the like, GaAsN1 and n-A, which are not doped with impurities, are used.
ffGaAs layers 2 are sequentially stacked.
ｎ −Ａ ！！ ＧａＡｓ層２は活性であるためこれが
露出状態にあると、酸化するおそれがあるため、ｎ
Ａ Ｉ ＧａＡｓＦＪ ２の表面上にＧａＡｓ等のＣａ
ｐＨ（保護膜）１６を形成しておくのが好ましい、また
、例えばｎ−／’ＦｉＧａＡｓ層２とＧａＡｓ層１との
間に不純物をドープしていないｎ−Ａｊ２ＧａＡｓ等か
らなるスペーサ層１８を介在させておくと、スペーサ層
１８内における電子移動度が高いため有利である。スペ
ーサ層１８を介在させた場合、このスペーサＪｌｉ１８
を介してｎ−ＡＥＧａＡｓ層２中のＳｔ等の不純物の電
子がＧａＡｓ層１内に入り込むことによって２ＤＥＧ層
６が形成されることになる。n-A! ! Since the GaAs layer 2 is active, there is a risk of oxidation if it is exposed.
A I GaAs FJ 2 has Ca such as GaAs on the surface
It is preferable to form a pH (protective film) 16, and for example, a spacer layer 18 made of n-Aj2GaAs not doped with impurities is interposed between the n-/'FiGaAs layer 2 and the GaAs layer 1. This is advantageous because the electron mobility within the spacer layer 18 is high. When the spacer layer 18 is interposed, this spacer Jli18
Electrons from impurities such as St in the n-AEGaAs layer 2 enter the GaAs layer 1 through the 2DEG layer 6.
第２図（ロ）はメサエッチング工程（第３図の工程Ｉ）
及び第２のＥｐ工程（同、工程■）を示。Figure 2 (B) shows the mesa etching process (Step I in Figure 3)
and the second Ep step (same, step ■).
す。ここでは第１のＥｌ）工程で基板上に積層形成され
たＧａＡｓｊｉｉｌ、ｎ −Ａ Ｉ ＧａＡｓ層２を、
一旦Ｅｐ炉から取り出してからメサエッチングによって
例えばメサ状（断層状の側壁１９は垂直であってもよい
）に加工することによって２ＤＥＧ層６をメサ状部の側
壁１９から露出させておき（以上メサエッチング工程Ｉ
）、再び炉内でその上からＮ ’ＧａＡｓＮ２ＯをＥｐ
成長させて積層形成する（以上第２のＥｐ工程１１ｒ）
、ＺＤＥＧ層６を露出させる手段としてはメサエッチン
グのように断層状の露出部を形成する以外にも、種々の
方法の適用が可能である。Ｅｐ工程時の加熱によってＮ
’ＧａＡｓ層（低抵抗半導体層）２０中のＳｔ等の不純
物のＮ゛がＧａＡｓ層１及びｎ −Ａ ｊｉ ＧａＡｓ
層２の面上から内部に向って拡散して導電１２１を形成
するので、２ＤＥＧ層とＮ ”ＧａＡｓ層２０との接触
はより完全なものとなる。vinegar. Here, the GaAsjiil, n-A I GaAs layer 2 laminated on the substrate in the first El) step,
Once removed from the Ep furnace, the 2DEG layer 6 is exposed from the side wall 19 of the mesa-shaped portion by etching it into a mesa shape (the fault-shaped side wall 19 may be vertical). Etching process I
), then Ep N'GaAsN2O from above in the furnace again.
Grow and form a layer (above, second Ep step 11r)
As a means for exposing the ZDEG layer 6, various methods can be used in addition to forming a tomographic exposed portion such as mesa etching. N due to heating during the Ep process
'N' of impurities such as St in the GaAs layer (low resistance semiconductor layer) 20 is the GaAs layer 1 and n -A ji GaAs
Since the conductive layer 121 is diffused inward from the surface of the layer 2, the contact between the 2DEG layer and the N''GaAs layer 20 becomes more complete.
なお、Ｅｐ時の加熱によって２ＤＥＧ層内にまで拡散が
行われると２ＤＥＧ層内の電子移動度が低減するおそれ
もあるが、この問題はスペーサの介在或いは第２のＥｐ
工程における加熱温度の低減等によって、回避可能であ
る。また、２ＤＥＧ層６のμ（透電率）低減は第１のＥ
ｐ工程におけるＧａＡｓ層１の設計によって回避するこ
とができる。Note that if the heating during Ep causes diffusion into the 2DEG layer, the electron mobility within the 2DEG layer may be reduced, but this problem can be solved by intervening a spacer or by using the second Ep.
This can be avoided by reducing the heating temperature in the process. Furthermore, the reduction in μ (transmittance) of the 2DEG layer 6 is due to the first E
This can be avoided by designing the GaAs layer 1 in the p process.
次に、第２図（ハ）はオーバーエツチング工程（第３図
の工程■）及び゛ゲート形成工程（同、工程■）を示す
。まずフォトレジスト２５を用いて台形状部の上面２６
に位置するＮ″ＧａＡｓ層２０をオーバーエツチングす
ることによって、フォトレジスト２５の両エツジ２５ａ
がひさし状になる開口部２０ａを形成し、Ｎ″ＧａＡｓ
ＧａＡｓ層６を露出する（工程■）。その上に図示する
ようなゲートメタル１３を斜め蒸着形成する（工程■）
。この実施例ではゲートメタル１３はＮ’ＧｓＡｓｊ！
！２０の開口部２０ａ内壁の一部から上面２６にかけて
固着されているが、このような構成であると電気抵抗を
少なくすることができる。このような斜め蒸着によれば
、実効ゲート値を短くして耐電圧値を高めることもでき
る。Next, FIG. 2(c) shows an over-etching step (step ① in FIG. 3) and a gate forming step (step ① in the same figure). First, using a photoresist 25, the upper surface 26 of the trapezoidal part is
Both edges 25a of the photoresist 25 are etched by over-etching the N''GaAs layer 20 located at
forms an eave-like opening 20a, and N″GaAs
The GaAs layer 6 is exposed (step ①). A gate metal 13 as shown in the figure is formed on it by diagonal vapor deposition (step ■)
. In this embodiment, the gate metal 13 is N'GsAsj!
! Although it is fixed from a part of the inner wall of the opening 20a of 20 to the upper surface 26, such a structure can reduce electrical resistance. According to such oblique vapor deposition, it is also possible to shorten the effective gate value and increase the withstand voltage value.
また、上記エツチングにおいては、上面２６が多少前ら
れることがあっても差支えない。なお、Ｎ′″ＧａＡｓ
１ｉ２０は、ゲートメタル形成時におけるリフトオフ用
のスペーサとしても利用できるため、Ｎ″ＧａＡｓＨ２
Ｏの厚さはプロセスに応じて任意に調節することが好ま
しい。さらにリフトオフによってゲートを形成する場合
、フォトレジスト２５の開口部の両エツジ２５ａを使う
ことによってゲート長を短くすることができる。Further, in the etching described above, there is no problem even if the upper surface 26 is slightly moved forward. Note that N′″GaAs
1i20 can also be used as a lift-off spacer during gate metal formation, so N''GaAsH2
It is preferable to arbitrarily adjust the thickness of O depending on the process. Furthermore, when forming a gate by lift-off, the gate length can be shortened by using both edges 25a of the opening of the photoresist 25.
第２図（ニ）はオーミック形成工程を示し、ゲート１３
を間にはさんでＮ″ＧａＡｓ層２０上にソースとドレイ
ンを構成するオーミックアロイ１Ｊ１１．１２を通常の
ＧａＡｓ技術によって形成する。なお、図示のようにオ
ーミックアロイｔｉｌｌ、 １２はＮ”ＧａＡｓ１ｉ２
０を貫通しても差支えない。FIG. 2(d) shows the ohmic formation process, and the gate 13
Ohmic alloy 1J11.12 constituting the source and drain is formed on the N''GaAs layer 20 with the ohmic alloy 1J11.12 in between as shown in the figure.
There is no problem even if it passes through 0.
なお、当然のことではあるが、本発明は上述の実施例に
限定されない。Note that, as a matter of course, the present invention is not limited to the above-described embodiments.
上述の如く、本発明の半導体装置及びその製造方法はＺ
ＤＥＧ層と低抵抗半導体層とを直接接触させることによ
って、２ＤＥＣ；Ｊｉとオーミックアロイ層との間の低
接触抵抗を実現することができる。As described above, the semiconductor device and the manufacturing method thereof of the present invention are Z
By directly contacting the DEG layer and the low resistance semiconductor layer, low contact resistance between the 2DEC; Ji and the ohmic alloy layer can be realized.
第１図は本発明の一実施例の構成説明図、第２図（イ）
〜（ニ）は同実施例の製造についてをその形成工程順に
夫々示す説明図、第３図はその製造手順を示す工程フロ
ー図である。第４図は従来のＨＥＭＴの構成説明図であ
る。
１− Ｇ ａ Ａ ｓ層、２− ｎ −Ａ Ｉ Ｇ ａ
Ａ ｓ層、３゜４・・・オーミック電極、５・・・ゲ
ート、６−・・２次元電子ガスチャンネル層、１１．１
２・・・オーミックアロイ層、１３・・・ｙ−ト、１６
・・・Ｃａｐ層、１８・・・スペーサ層１９・・・側壁
、２０・・・低抵抗半導体層。
■・・・メサエッチング工程、■・・・低抵抗半導体層
の成長工程、■・・・オーバーエツチング工程、■・・
・ゲート形成工程。Figure 1 is an explanatory diagram of the configuration of an embodiment of the present invention, Figure 2 (a)
-(d) are explanatory diagrams showing the manufacturing steps of the same embodiment in the order of their formation steps, and FIG. 3 is a process flow diagram showing the manufacturing procedure. FIG. 4 is an explanatory diagram of the configuration of a conventional HEMT. 1-G a As layer, 2- n -A I Ga
As layer, 3゜4... Ohmic electrode, 5... Gate, 6-... Two-dimensional electron gas channel layer, 11.1
2... Ohmic alloy layer, 13... Y-to, 16
... Cap layer, 18 ... Spacer layer 19 ... Side wall, 20 ... Low resistance semiconductor layer. ■... Mesa etching process, ■... Low resistance semiconductor layer growth process, ■... Over etching process, ■...
・Gate formation process.
Claims (1)
おいて、 上記２次元電子ガスチャンネル層の少なくとも一部分を
表面に露出させてメサ状部とし、 該メサ状部の該２次元電子ガスチャンネル層に直接接触
させて形成した低抵抗半導体層を、ソース、ドレイン電
極となるオーミック電極と該２次元電子ガスチャンネル
層との間に介在させて成ることを特徴とする半導体装置
。 ２、２次元電子ガスチャンネル層を有する半導体装置を
メサエッチして、側部に上記２次元電子ガスチャンネル
層の少なくとも一部分を露出させる工程と、 上記メサエッチングした基板上に低抵抗半導体層をエピ
タキシャル成長させる工程と、 メサ状部の上記低抵抗半導体層を所定のマスクを用いて
オーバーエッチングする工程と、 上記マスクを用いてゲート電極を斜め蒸着で形成する工
程と、 を備えた半導体装置の製造方法。[Scope of Claims] A semiconductor device having a one- and two-dimensional electron gas channel layer, wherein at least a portion of the two-dimensional electron gas channel layer is exposed on the surface to form a mesa-shaped portion, and the two-dimensional electron gas channel layer in the mesa-shaped portion A semiconductor device characterized in that a low resistance semiconductor layer formed in direct contact with a gas channel layer is interposed between ohmic electrodes serving as source and drain electrodes and the two-dimensional electron gas channel layer. 2. mesa-etching a semiconductor device having a two-dimensional electron gas channel layer to expose at least a portion of the two-dimensional electron gas channel layer on the side; and epitaxially growing a low-resistance semiconductor layer on the mesa-etched substrate. A method for manufacturing a semiconductor device, comprising the steps of: over-etching the low-resistance semiconductor layer in the mesa-shaped portion using a predetermined mask; and forming a gate electrode by oblique vapor deposition using the mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17192085A JPS6232660A (en) | 1985-08-06 | 1985-08-06 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17192085A JPS6232660A (en) | 1985-08-06 | 1985-08-06 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232660A true JPS6232660A (en) | 1987-02-12 |
Family
ID=15932294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17192085A Pending JPS6232660A (en) | 1985-08-06 | 1985-08-06 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232660A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0741417A2 (en) * | 1995-05-04 | 1996-11-06 | Motorola, Inc. | Heterostructure field effect device having refractory ohmic contact directly on channel layer and method of making |
| US5818078A (en) * | 1994-08-29 | 1998-10-06 | Fujitsu Limited | Semiconductor device having a regrowth crystal region |
-
1985
- 1985-08-06 JP JP17192085A patent/JPS6232660A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818078A (en) * | 1994-08-29 | 1998-10-06 | Fujitsu Limited | Semiconductor device having a regrowth crystal region |
| US6121153A (en) * | 1994-08-29 | 2000-09-19 | Fujitsu Limited | Semiconductor device having a regrowth crystal region |
| EP0741417A2 (en) * | 1995-05-04 | 1996-11-06 | Motorola, Inc. | Heterostructure field effect device having refractory ohmic contact directly on channel layer and method of making |
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