KR910004319B1 - Manufacturing method of high electron mobility transistor - Google Patents
Manufacturing method of high electron mobility transistor Download PDFInfo
- Publication number
- KR910004319B1 KR910004319B1 KR1019880008722A KR880008722A KR910004319B1 KR 910004319 B1 KR910004319 B1 KR 910004319B1 KR 1019880008722 A KR1019880008722 A KR 1019880008722A KR 880008722 A KR880008722 A KR 880008722A KR 910004319 B1 KR910004319 B1 KR 910004319B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- gallium arsenide
- high electron
- source
- buffer layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 16
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract 3
- 238000001020 plasma etching Methods 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 16
- 230000027756 respiratory electron transport chain Effects 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
제 1 도는 종래의 갈륨비소 고전자 이동 트랜지스터의 단면도.1 is a cross-sectional view of a conventional gallium arsenide high electron transfer transistor.
제 2 도는 본 발명에 따른 갈륨비소 이온주입형 고전자 이동 트랜지스터의 공정순서도이다.2 is a process flowchart of a gallium arsenide ion implantation high electron transfer transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 소오스 또는 드레인전극 2 : 게이트 전극,1 source or drain electrode 2 gate electrode,
3 : 갈륨비소캡층(n+GaAs) 4 : 알루미늄 갈륨비소층(nAlGaAs)3: gallium arsenide cap layer (n + GaAs) 4: aluminum gallium arsenide layer (nAlGaAs)
5 : 버퍼층(GaAs) 6 : 기판(GaAs)5: buffer layer (GaAs) 6: substrate (GaAs)
7 : 이온주입층7: ion implantation layer
본 발명은 이종접합구조를 가지고 그 이종접합계면에서 전자변조를 행하는 반도체 장치에 적용되는 고전자 이동 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a high electron transfer transistor applied to a semiconductor device having a heterojunction structure and performing electron modulation in the heterojunction interface.
종래의 고전자 이동 트랜지스터는 제 1 도와 같은 구조를 갖고 있는 것으로 대개 갈륨비소캡층(3) 및 알루미늄갈륨비소층(4)으로 구성되어 있기 때문에 알루미늄갈륨비소(AlGaAs)층 위에 오옴성 접촉을 형성하기 위한 갈륨비소(n+GaAs)의 에피텍셜층을 성장시켜야만 되는 제조 공정이 필요하게 된다.The conventional high electron transfer transistor has a structure similar to that of the first diagram, and is generally composed of a gallium arsenide cap layer 3 and an aluminum gallium arsenide layer 4, thereby forming an ohmic contact on the aluminum gallium arsenide (AlGaAs) layer. There is a need for a manufacturing process in which an epitaxial layer of gallium arsenide (n + GaAs) must be grown.
또한 갈륨비소캡층(3) 및 알루미늄갈륨비소층(4)의 접합이 트랜지스터의 소오스, 게이트, 드레인 전 영역에 걸쳐 형성되어 있고 알루미늄 갈륨비소(AlGaAs)자체의 저항이 갈륨비소(GaAs)보다 높아 소오스측 및 드레인측에 기생저항이 발생될 뿐만 아니라 전도대 오프셋트로 인하여 소오스측 기생저항이 발생된다. 따라서 종래의 고전자 이동 트랜지스터는 제조공정의 증가 및 기생저항이 발생되어 고전자 이동 트랜지스터의 성능을 크게 저하시키는 단점이 있는 것이었다.In addition, a junction between the gallium arsenide cap layer 3 and the aluminum gallium arsenide layer 4 is formed over the entire source, gate, and drain regions of the transistor, and the resistance of aluminum gallium arsenide (AlGaAs) itself is higher than that of gallium arsenide (GaAs). The parasitic resistance is generated not only on the side and drain side but also on the source side parasitic resistance due to the conduction band offset. Therefore, the conventional high electron transfer transistor has a disadvantage in that an increase in manufacturing process and parasitic resistance are generated, thereby greatly degrading the performance of the high electron transfer transistor.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로 본 발명의 목적은 트랜지스터의 소오스 및 드레인측의 오옴성접촉을 위한 갈륨비소의 에피텍셜층을 형성시키지 않고 버퍼층내에 이온주입에 의하여 오옴성접촉이 될 수 있는 고전자 이동 트랜지스터의 제조방법을 제공하고자 하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to form ohmic contact by ion implantation into a buffer layer without forming an epitaxial layer of gallium arsenide for ohmic contact on the source and drain sides of a transistor. An object of the present invention is to provide a method of manufacturing a high electron transfer transistor.
본 발명의 특징은 기판위에 버퍼층 및 알루미늄갈륨비소층을 성장시키는 공정과, 게이트영역에만 알루미늄갈륨비소층만 남기고 플라즈마로 식각하는 공정과, 소오스 및 드레인영역에 실리콘 이온을 주입시켜 이온주입층을 형성시키는 공정과, 트랜지스터의 소오스전극, 드레인전극, 레이트전극이 리프트오프방식으로 형성되는 공정과로 된 것에 있다.Features of the present invention include a process of growing a buffer layer and an aluminum gallium arsenide layer on a substrate, etching with a plasma leaving only an aluminum gallium arsenide layer only in a gate region, and implanting silicon ions into the source and drain regions to form an ion implantation layer. And a step of forming a source electrode, a drain electrode, and a rate electrode of the transistor by a lift-off method.
이하 본 발명의 실시예를 첨부도면에 따라서 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제 2 도의 (a)도와 같이 GaAs 기판(6)위에 GaAs 버퍼층(5) 및 알루미늄갈륨비소층(4)을 제 1 도의 종래의 방법과 동일하게 성장시켜 형성한다.As shown in FIG. 2A, a
특히 본 발명은 고전자 이동 트랜지스터의 에피텍셜층의 성장공정을 생략시켜 소오스측의 기생저항을 감소시킬 수 있도록 한 것으로 종래에는 n+GaAs 캡층이 필요적으로 형성되어야 하고 에피텍셜층이 많아지면 결국 결정성장층 자체뿐만 아니라 계면등에 고온 열처리를 많이 받게되므로 신뢰성에 문제점이 생긴다.In particular, the present invention allows the parasitic resistance of the source side to be reduced by omitting the growth process of the epitaxial layer of the high electron transfer transistor. In the related art, the n + GaAs cap layer is required to be formed. As well as the growth layer itself, a lot of high temperature heat treatment is applied to the interface, so there is a problem in reliability.
즉, 알루미늄갈륨비소층(4)과 버퍼층(5)사이에서 2 차원 전자가스가 생겨 고전자 이동이 가져오게 되는데 전술한 바와 같이 많은 열처리를 받게되면 계면의 불안정성을 초래하게 된다.In other words, a two-dimensional electron gas is generated between the aluminum gallium arsenide layer 4 and the
그러나 본 발명은 (a)도와 같이 성장시킨 후 (b)도와 같이 게이트영역의 알루미늄갈륨비소층(4)만 남기고 모두 플라즈마로 식각한다.However, the present invention is grown as shown in (a) and then etched by plasma, leaving only the aluminum gallium arsenide layer 4 in the gate region as shown in (b).
그리고, 소오스, 드레인영역에 실리콘(Si)이온을 주입시켜 n+영역을 형성시켜 (c)도와 같이 이온주입층(7)이 구성되게 한다.Then, silicon (Si) ions are implanted into the source and drain regions to form n + regions to form the
이 상태에서 오옴성전극인 소오스전극, 드레인전극과 게이트전극을 리프트오프공정에 의하여 (d)도와 같은 고전자 이동 트랜지스터가 완성되는 것으로 이는 일반적인 고전자이동트랜지스터와는 반전된 형태의 구조를 갖게 된다.In this state, a high electron transfer transistor such as (d) is completed by a lift-off process of the source electrode, the drain electrode, and the gate electrode as the ohmic electrode, which has a structure inverted from that of a general high electron transfer transistor.
이때의 리프트오프공정은 이온주입층(7)에 소오스 및 드레인전극이 형성될 부분을 제외하고, PR층을 형성시킨 후 각각의 소오스, 드레인, 게이트전극을 형성시키고나서 현상에 의해 PR층을 제거하게 된다.At this time, the lift-off process removes the PR layer by developing each source, drain, and gate electrode after forming a PR layer except for a portion where the source and drain electrodes are to be formed in the
이상에서와 같이 본 발명은 트랜지스터의 소오스전극 및 드레인전극부위에 n+GaAs과 AlGaAs층 없이 직접 버퍼층에 이온주입을 행하여 오옴성접촉이 되게 함으로써 소오스측 기생저항치를 크게 줄이고 전달 콘덕턴스와 주파수특성을 향상시킬 수 있어 소자의 특성을 크게 개선시킬 수가 있으며, 이종접합간의 공정수도 단축시킬 수 있는 효과가 있는 것이다.As described above, the present invention directly implants ions into the buffer layer without the n + GaAs and AlGaAs layers on the source electrode and drain electrode of the transistor to make ohmic contact, thereby greatly reducing the source side parasitic resistance and reducing the transfer conductance and frequency characteristics. The characteristics of the device can be greatly improved, and the number of processes between heterojunctions can be shortened.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019880008722A KR910004319B1 (en) | 1988-07-14 | 1988-07-14 | Manufacturing method of high electron mobility transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019880008722A KR910004319B1 (en) | 1988-07-14 | 1988-07-14 | Manufacturing method of high electron mobility transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR900002466A KR900002466A (en) | 1990-02-28 |
| KR910004319B1 true KR910004319B1 (en) | 1991-06-25 |
Family
ID=19276051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019880008722A KR910004319B1 (en) | 1988-07-14 | 1988-07-14 | Manufacturing method of high electron mobility transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR910004319B1 (en) |
-
1988
- 1988-07-14 KR KR1019880008722A patent/KR910004319B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR900002466A (en) | 1990-02-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100305148B1 (en) | External enveloping molding module and method of attaching enveloping molding and glass working channel | |
| JP2643859B2 (en) | Compound semiconductor field effect transistor | |
| JPH0260063B2 (en) | ||
| JPH06177159A (en) | Field-effect transistor and manufacture thereof | |
| KR910004319B1 (en) | Manufacturing method of high electron mobility transistor | |
| US5514606A (en) | Method of fabricating high breakdown voltage FETs | |
| US5539248A (en) | Semiconductor device with improved insulating/passivating layer of indium gallium fluoride (InGaF) | |
| GB2239557A (en) | High electron mobility transistors | |
| US5640025A (en) | High frequency semiconductor transistor | |
| JPS6332273B2 (en) | ||
| JPH0216008B2 (en) | ||
| JP2728427B2 (en) | Field effect transistor and its manufacturing method | |
| JP2661569B2 (en) | Heterojunction field effect transistor and method of manufacturing the same | |
| JPH0472384B2 (en) | ||
| JPH0810701B2 (en) | Method for manufacturing junction field effect transistor | |
| JPH07201887A (en) | Field effect transistor | |
| JPH0529354A (en) | Manufacture of semiconductor device | |
| JP2616032B2 (en) | Method for manufacturing field effect transistor | |
| JPS5918679A (en) | Semiconductor device | |
| JPH0618217B2 (en) | Method for manufacturing semiconductor device | |
| JPS6070772A (en) | Manufacture of field-effect transistor | |
| JPS6223175A (en) | Manufacture of semiconductor device | |
| JPS6143443A (en) | Manufacture of semiconductor device | |
| JPH04122033A (en) | Manufacture of field effect transistor | |
| JPH0521467A (en) | Manufacture of field-effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| N231 | Notification of change of applicant | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050506 Year of fee payment: 15 |
|
| LAPS | Lapse due to unpaid annual fee |