JPS63174374A - Manufacture of field-effect semiconductor device - Google Patents
Manufacture of field-effect semiconductor deviceInfo
- Publication number
- JPS63174374A JPS63174374A JP647187A JP647187A JPS63174374A JP S63174374 A JPS63174374 A JP S63174374A JP 647187 A JP647187 A JP 647187A JP 647187 A JP647187 A JP 647187A JP S63174374 A JPS63174374 A JP S63174374A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- opening
- etching
- semiconductor substrate
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 8
- 239000010931 gold Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
この発明は、電界効果型半導体装置を製造するに際して
、
半導体基体面上の第１の絶縁膜に第１の開口を形成し、
第１の開口及びその近傍の第１の絶縁膜下の半導体基体
をエツチングしてリセスを形成し、第２の絶縁膜をリセ
スの第１の絶縁膜下の空間まで堆積し、第２の絶縁膜に
形成した第２の開口で半導体基体にショットキ接合する
ゲート電極を形成することにより、
短ゲート長のゲート構造に効果的なリセスを形成して、
ゲート耐圧とソース抵抗等の特性の両立を可能とする。[Detailed Description of the Invention] [Summary] The present invention, when manufacturing a field effect semiconductor device, comprises forming a first opening in a first insulating film on a semiconductor substrate surface;
A recess is formed by etching the semiconductor substrate under the first insulating film in the first opening and the vicinity thereof, and a second insulating film is deposited up to the space under the first insulating film in the recess. By forming a gate electrode that makes a Schottky junction with the semiconductor substrate through the second opening formed in the film, an effective recess is formed in the gate structure with a short gate length.
This makes it possible to achieve both characteristics such as gate breakdown voltage and source resistance.
本発明は電界効果型半導体装置の製造方法、特にそのシ
ョットキ接合形ゲート構造の製造方法の改善に関する。The present invention relates to a method for manufacturing a field effect semiconductor device, and particularly to an improvement in a method for manufacturing a Schottky junction gate structure.
砒化ガリウム（ＧａＡｓ）を半導体材料とするショット
キ接合形電界効果トランジスタ（ＭＥＳ ＦＥＴ）がマ
イクロ波帯域等において多数用いられており、更に空間
分離ドーピングと電子の２次元状態化により一層の高移
動度を実現した高電子移動度電界効果トランジスタ（Ｈ
ＥＭＴ）の実用化が始まっている。Schottky junction field effect transistors (MES FETs), which use gallium arsenide (GaAs) as a semiconductor material, are widely used in the microwave band, etc., and have even higher mobility through spatial separation doping and two-dimensional electron stateing. High electron mobility field effect transistor (H
EMT) has begun to be put into practical use.
これらのＦＥＴは、ゲート長を短縮して遮断周波数等の
周波数特性を向上すること、リセス長を短縮してソース
抵抗（ソース−ゲート間の寄生抵抗）を減少し、伝達コ
ンダクタンスｇ、を増大すること、しかもゲート耐圧を
確保することなどを目的として微細加工技術を駆使して
製造されるが、従来の製造方法の１例を第２図の工程順
模式側断面図を参照して説明する。These FETs shorten the gate length to improve frequency characteristics such as cutoff frequency, shorten the recess length to reduce source resistance (parasitic resistance between source and gate), and increase transfer conductance g. In addition, it is manufactured by making full use of microfabrication technology for the purpose of ensuring gate breakdown voltage, etc., and an example of a conventional manufacturing method will be described with reference to the schematic side sectional view of the process order in FIG. 2.
〔図（ａ）〕チャネル層等を備えた半導体基体２１上に
ソース、ドレイン電極２５を配設し、その上に第１の絶
縁膜２６を堆積してレジストマスク２７を形成し、絶縁
膜２６に開口２６ａを通常ドライエツチングによって形
成する。現在のホトリソグラフィ技術ではこの開口２６
ａの寸法１１は最短０．５−程度である。[Figure (a)] Source and drain electrodes 25 are provided on a semiconductor substrate 21 having a channel layer etc., a first insulating film 26 is deposited thereon to form a resist mask 27, and the insulating film 26 is An opening 26a is formed by dry etching. With current photolithography technology, this opening 26
The dimension 11 of a is about 0.5 - at the shortest.
〔図（ｂ）〕 レジストマスク２７を剥離して、プラズ
マＣＶＤ法等により第２の絶縁膜２８を厚さ０．２μｍ
程度に堆積する。この第２の絶縁膜２８は図示の様に、
開口２６ａの側面及び半導体基体２１０表出面にも堆積
して中央がくぼんだ形状となる。[Figure (b)] The resist mask 27 is peeled off, and a second insulating film 28 is formed to a thickness of 0.2 μm using a plasma CVD method or the like.
It accumulates to a certain extent. As shown in the figure, this second insulating film 28 is
It also accumulates on the side surfaces of the opening 26a and the exposed surface of the semiconductor substrate 210, resulting in a shape with a concave center.
〔図（Ｃ）〕第２の絶縁膜２８を基板面に垂直方向にド
ライエツチングし、半導体基体２１が表出する状態とす
る。この状態では第１の絶縁膜２６の側端面に第２の絶
縁膜２日が残って側壁２８Ｗとなり、例えば開口２６ａ
の寸法ｉ、が０．５四のとき、側壁２８−間の開口２８
ａの寸法１２は約０．２−となる。[Figure (C)] The second insulating film 28 is dry etched in a direction perpendicular to the substrate surface, so that the semiconductor substrate 21 is exposed. In this state, two portions of the second insulating film remain on the side end surfaces of the first insulating film 26, forming the side walls 28W, for example, the opening 26a.
When the dimension i of is 0.54, the opening 28 between the side wall 28 and
The dimension 12 of a is approximately 0.2-.
このエツチング後の清浄化処理により開口２８ａに表出
する半導体基体表面が通常僅かにエツチングされるが、
積極的に開口２８ａの近傍の半導体基体をリセスエッチ
ングしてもよい。The surface of the semiconductor substrate exposed in the opening 28a is usually slightly etched by this cleaning treatment after etching.
The semiconductor substrate near the opening 28a may be actively recess-etched.
〔図（ｄ）〕通常逆テーパー状の開口をこの開口２８ａ
上に形成したレジストマスク２９を設け、ゲート金属を
堆積してゲート電極３０を形成する。このときレジスト
マスク２９上にゲート金属の堆積３０’ ができる。[Figure (d)] This opening 28a usually has an inverted tapered shape.
A resist mask 29 formed above is provided, and gate metal is deposited to form a gate electrode 30. At this time, a gate metal deposit 30' is formed on the resist mask 29.
〔図（ｅ）〕 レジストマスク２９を剥離除去して、そ
の上のゲート金属の堆積３０゛ をリフトオフする。[Figure (e)] The resist mask 29 is peeled off and the deposited gate metal 30' thereon is lifted off.
上述の従来の製造方法において、側壁間の開口２８ａに
表出する半導体基体２１が清浄化処理で工・７チングさ
れてもその量は僅かであり、この開口を介して半導体基
体を積極的にリセスエッチングしても幅の制限から深さ
が制約される。In the conventional manufacturing method described above, even if the semiconductor substrate 21 exposed in the opening 28a between the side walls is etched in the cleaning process, the amount is very small, and the semiconductor substrate is actively etched through this opening. Even with recess etching, the depth is restricted due to the width restriction.
従ってリセス構造の効果は得難く、ゲート電極とのショ
ットキ接合が半導体基体の表面領域に形成されるか或い
は極く近接してゲート耐圧の確保が困難であり、ゲート
耐圧を考慮すれば特性に大きく影響する半導体基体の表
面領域の構成、不純物濃度などが制約され、ソース抵抗
、オーミックコンタクト抵抗の増大などの問題を生じて
いる。Therefore, it is difficult to obtain the effect of the recessed structure, and the Schottky junction with the gate electrode is formed on the surface area of the semiconductor substrate or is very close to the semiconductor substrate, making it difficult to ensure the gate breakdown voltage. The configuration and impurity concentration of the surface region of the semiconductor substrate that are affected are restricted, leading to problems such as an increase in source resistance and ohmic contact resistance.
前記問題点は、半導体基体面上に第１の絶縁膜を堆積し
、該第１の絶縁膜に第１の開口を形成し、該第１の開口
及びその近傍の該第１の絶縁膜下の該半導体基体をエツ
チングし、第２の絶縁膜を該エツチングによる該第１の
絶縁膜下の空間まで堆積し、該第１の開口内で該第２の
絶縁膜に第２の開口を形成し、該第２の開口に表出する
該半導体基体にショットキ接合し、該接合面近傍におい
て該第２の絶縁膜に画定されるゲート電極を形成する本
発明による電界効果型半導体装置の製造方法により解決
される。The problem is that a first insulating film is deposited on the surface of a semiconductor substrate, a first opening is formed in the first insulating film, and a portion under the first insulating film in and near the first opening is formed. etching the semiconductor substrate, depositing a second insulating film to the space under the first insulating film formed by the etching, and forming a second opening in the second insulating film within the first opening. and forming a Schottky junction on the semiconductor substrate exposed in the second opening, and forming a gate electrode defined on the second insulating film in the vicinity of the junction surface. It is solved by
本発明の製造方法では、リソグラフィ法によって第１の
絶縁膜に形成される相対的に大きい第１の開口を形成し
た時点で、半導体基体を絶縁膜下までリセスエッチング
し、第２の絶縁膜をこの第１の絶縁膜下の空間まで堆積
する。In the manufacturing method of the present invention, when the relatively large first opening is formed in the first insulating film by lithography, the semiconductor substrate is recess-etched to below the insulating film, and the second insulating film is formed. It is deposited up to the space below this first insulating film.
例えばゲート長を０．２５μｍ程度とする場合に、この
開口幅は前記従来例の側壁形成後の開口幅の２倍程度で
あるために、このエツチング処理で深ざ及び絶縁膜下の
サイドエツチング幅が０．０５〜０６１μｍ程度の効果
的なリセス形成が容易に可能であり、ゲート耐圧とソー
ス抵抗等の特性を両立させるなどの効果が得られる。For example, when the gate length is about 0.25 μm, this opening width is about twice the opening width after sidewall formation in the conventional example, so this etching process reduces the depth and the side etching width under the insulating film. Effective recess formation with a diameter of about 0.05 to 061 μm is easily possible, and effects such as achieving both characteristics such as gate breakdown voltage and source resistance can be obtained.
以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.
第１図ｆａ）乃至（ｆ）はＩＩ Ｅ Ｍ Ｔにかかる本
発明の実施例を示す工程順模式側断面図である。FIGS. 1fa) to 1(f) are schematic side sectional views in the order of steps showing an embodiment of the present invention according to II EMT.
第１図（ａ）参照二 半絶縁性ＧａＡｓ基板１上に、厚
さ０．５〜１μｍ程度のノンドープのＧａＡｓ層２、Ｓ
ｉを２ Ｘ １０’ ８ｃｍ−３程度にドープした厚さ
４０ｎｍ程度のｎ型砒化アルミニウムガリウム（ＡＩＧ
ａＡｓ）ＩＷ ３、これと同程度以上にＳｉをドープし
た厚さ例えば１２０１ｍ程度のｎ型ＧａＡｓ層４を順次
エピタキシャル成長する。このノンドープのＧａＡｓ層
２のｎ型ＡｌＧａＡｓ層３とのへテロ接合界面近傍に２
次元電子ガス２ｅが形成される。See FIG. 1(a) 2. On a semi-insulating GaAs substrate 1, a non-doped GaAs layer 2 with a thickness of about 0.5 to 1 μm, S
n-type aluminum gallium arsenide (AIG) with a thickness of about 40 nm doped with i to about 2
aAs)IW 3, and an n-type GaAs layer 4 doped with Si to the same degree or more and having a thickness of, for example, about 1201 m, are sequentially epitaxially grown. In the vicinity of the heterojunction interface between this non-doped GaAs layer 2 and the n-type AlGaAs layer 3,
Dimensional electron gas 2e is formed.
この半導体基体上に第１の絶縁膜６として、例えばＣＶ
Ｄ法等によりＳｉＯ□を厚さ０．３μｍ程度に堆積する
。更にゲート形成位置で幅Ｉ！、が例えば０．５μｍの
溝状をなす開口を設けたレジストマスク７をこの５ｉＯ
ｚ絶縁膜６上に設け、例えばＣＨＦ３、ＣＦ４等により
ドライエツチングして、Ｓｉ０ｇ絶縁膜６に開口６ａを
形成する。A first insulating film 6, for example, CV
SiO□ is deposited to a thickness of about 0.3 μm using the D method or the like. Furthermore, the width I at the gate formation position! For example, a resist mask 7 provided with a groove-shaped opening of 0.5 μm is coated with this 5iO
An opening 6a is formed in the Si0g insulating film 6 by providing it on the z insulating film 6 and dry etching it using, for example, CHF3, CF4 or the like.
第１図（ｂ）参照： このレジストマスク７およびＳｉ
Ｏ□絶縁膜６をマスクとして、例えばＣＣＩ□Ｆ２によ
るリアクティブイオンエツチング、或いは弗酸と過酸化
水素水によるウェットエツチング等を行い、例えば深さ
が開口６ａ下で０．１μｍ％ ｓｔｏ□絶縁膜６下への
サイドエツチング最大幅０．１−１従って半導体基体表
面の幅Ｌ＝０．７−程度のリセス構造４Ｒを形成する。See FIG. 1(b): This resist mask 7 and Si
Using the O□ insulating film 6 as a mask, reactive ion etching using, for example, CCI□F2, or wet etching using hydrofluoric acid and hydrogen peroxide, etc., is performed to form a sto□ insulating film with a depth of, for example, 0.1 μm% below the opening 6a. 6 downward side etching to form a recess structure 4R having a maximum width of about 0.1-1, so the width L of the surface of the semiconductor substrate is about 0.7-.
第１図（Ｃ１参照： レジストマスク７を剥離した後、
プラズマＣＶＤ法等によりこの基体上に第２の絶縁膜８
としてＳｉＯ□を再度堆積する。このＳｉＯ□絶縁膜８
は図示の如くリセス構造４Ｒのサイドエツチング部分を
充填する。FIG. 1 (see C1: After peeling off the resist mask 7,
A second insulating film 8 is formed on this substrate by plasma CVD method or the like.
Then, SiO□ is deposited again. This SiO□insulating film 8
fills the side etched portion of the recess structure 4R as shown.
第１図（ｄｌ参照： スパッタエツチング法等により基
体面に垂直方向にＳｉＯ□絶縁膜８をエツチングして開
口８ａを形成する。この結果側壁８讐が残置され、開口
８ａの幅１２は本実施例では約０．２５−となっている
。FIG. 1 (see dl: The SiO□ insulating film 8 is etched in a direction perpendicular to the substrate surface using a sputter etching method or the like to form an opening 8a. As a result, side walls 8 are left and the width 12 of the opening 8a is the same as in this embodiment. In the example, it is approximately 0.25-.
第１図（ｅｌ参照： この開口８ａ上に逆テーパー状の
開口を形成したレジストマスク９を設け、ゲート電極層
として例えばチタン／白金／金（Ｔｉ／Ｐｔ／Ａｕ）等
を厚さ０．５ｕｍ程度に堆積して、ゲート電極１ｏを形
成する。開口外のレジストマスク９上にはゲート金属層
１０゛ が堆積する。FIG. 1 (see el: A resist mask 9 with an inverted tapered opening is provided over the opening 8a, and a gate electrode layer made of, for example, titanium/platinum/gold (Ti/Pt/Au) is formed to a thickness of 0.5 um. A gate metal layer 10' is deposited on the resist mask 9 outside the opening.
第１図（ｆ）参照： レジストマスク９を剥離してゲー
ト金属層１０″をリフトオフした後、本実施例ではゲー
ト電極１０をマスクとして第１の絶縁膜６をエツチング
する。Refer to FIG. 1(f): After removing the resist mask 9 and lifting off the gate metal layer 10'', in this embodiment, the first insulating film 6 is etched using the gate electrode 10 as a mask.
次いでオーミックコンタクト電極層として例えば金ゲル
マニウム／ニッケル／金（ＡｕＧｅ／Ｎｉ／Ａｕ）層を
堆積し、バターニング後例えば温度４００’Ｃ１２分間
程度の熱処理を行って、半導体基体との間の合金領域５
Ａが２次元電子ガス２ｅに達するソース、ドレイン電極
５を形成する。なお５゛はゲート電極１゜上に堆積した
ＡｕＧｅ／Ｎｉ／Ａｕ層である。Next, for example, a gold-germanium/nickel/gold (AuGe/Ni/Au) layer is deposited as an ohmic contact electrode layer, and after buttering, heat treatment is performed at a temperature of, for example, 400'C for about 12 minutes to form an alloy region 5 between it and the semiconductor substrate.
Source and drain electrodes 5 are formed where A reaches the two-dimensional electron gas 2e. Note that 5° is an AuGe/Ni/Au layer deposited on 1° of the gate electrode.
本実施例のソース抵抗は約０．８Ωｍｍ、ゲート−ドレ
イン間の耐圧は約６Ｖで、ソース抵抗が等しい従来例の
この耐圧約３■の２倍となり、本発明の効果が実証され
ている。The source resistance of this embodiment is about 0.8 Ωmm, and the breakdown voltage between the gate and drain is about 6V, which is twice the breakdown voltage of about 3cm in the conventional example with the same source resistance, thus proving the effectiveness of the present invention.
以上説明した如く本発明によれば、絶縁膜を再度堆積し
て側壁を設けることによりゲート長を短縮する電界効果
型半導体装置の製造方法においても、効果的なリセス構
造を形成することが容易に可能となり、ゲート耐圧とソ
ース抵抗、オーミックコンタクト抵抗等の特性を両立さ
せるなどの効果が得られ、電界効果型半導体装置の特性
の向上に大きく寄与する。As explained above, according to the present invention, an effective recess structure can be easily formed even in a method for manufacturing a field effect semiconductor device in which the gate length is shortened by depositing an insulating film again to provide a sidewall. This makes it possible to obtain effects such as achieving both characteristics such as gate breakdown voltage, source resistance, and ohmic contact resistance, which greatly contributes to improving the characteristics of field-effect semiconductor devices.
第１図は実施例の工程順模式側断面図、第２図は従来例
の工程順模式側断面図である。
図において、
１は半絶縁性Ｇ ａ、Ａ ｓ基板、
２はノンドープのＧａＡｓ層、２ｅは２次元電子ガス、
３はｎ型Ａ］ＧａＡｓ層、 ４はｎ型ＧａＡｓ層
、４Ｒはリセス構造、
５はソース、ドレイン電極、
６は第１の絶縁膜、 ６ａはその開口、７．９はレ
ジストマスク、
８は第２の絶縁膜、 ８ａはその開口、８Ｗは第２
の絶縁膜による側壁、
１０はゲート電極を示す。FIG. 1 is a schematic side sectional view of the process order of the embodiment, and FIG. 2 is a schematic side sectional view of the process order of the conventional example. In the figure, 1 is a semi-insulating Ga, As substrate, 2 is a non-doped GaAs layer, 2e is a two-dimensional electron gas,
3 is an n-type GaAs layer, 4 is an n-type GaAs layer, 4R is a recess structure, 5 is a source and drain electrode, 6 is a first insulating film, 6a is an opening thereof, 7.9 is a resist mask, 8 is a resist mask 8a is the opening of the second insulating film, 8W is the second insulating film;
10 indicates a gate electrode.
Claims (1)
膜に第１の開口を形成し、該第１の開口及びその近傍の
該第１の絶縁膜下の該半導体基体をエッチングし、第２
の絶縁膜を該エッチングによる該第１の絶縁膜下の空間
まで堆積し、該第１の開口内で該第２の絶縁膜に第２の
開口を形成し、該第２の開口に表出する該半導体基体に
ショットキ接合し、該接合面近傍において該第２の絶縁
膜に画定されるゲート電極を形成することを特徴とする
電界効果型半導体装置の製造方法。Depositing a first insulating film on a surface of the semiconductor substrate, forming a first opening in the first insulating film, and depositing the semiconductor substrate under the first insulating film in and near the first opening. Etched and second
an insulating film is deposited to the space under the first insulating film by the etching, a second opening is formed in the second insulating film within the first opening, and the second insulating film is exposed in the second opening. A method for manufacturing a field effect semiconductor device, comprising forming a Schottky junction on the semiconductor substrate and forming a gate electrode defined in the second insulating film near the junction surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP647187A JPS63174374A (en) | 1987-01-14 | 1987-01-14 | Manufacture of field-effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP647187A JPS63174374A (en) | 1987-01-14 | 1987-01-14 | Manufacture of field-effect semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63174374A true JPS63174374A (en) | 1988-07-18 |
Family
ID=11639369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP647187A Pending JPS63174374A (en) | 1987-01-14 | 1987-01-14 | Manufacture of field-effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63174374A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0430289A2 (en) * | 1989-12-01 | 1991-06-05 | Hughes Aircraft Company | Fabrication of self-aligned, T-gate hemt |
| JPH03190246A (en) * | 1989-12-20 | 1991-08-20 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH05190869A (en) * | 1992-01-13 | 1993-07-30 | Nec Corp | Quantum small-cage wire type field-effect transistor and manufacture thereof |
| EP0592064A2 (en) * | 1992-08-19 | 1994-04-13 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor and method of production |
| US5391899A (en) * | 1991-10-29 | 1995-02-21 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor device with a particular gate structure |
| US5548144A (en) * | 1993-03-05 | 1996-08-20 | Mitsubishi Denki Kabushiki Kaisha | Recessed gate field effect transistor |
| US6159861A (en) * | 1997-08-28 | 2000-12-12 | Nec Corporation | Method of manufacturing semiconductor device |
| US6337262B1 (en) * | 2000-03-06 | 2002-01-08 | Chartered Semiconductor Manufacturing Ltd. | Self aligned T-top gate process integration |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5772384A (en) * | 1980-10-24 | 1982-05-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field-effect transistor |
-
1987
- 1987-01-14 JP JP647187A patent/JPS63174374A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5772384A (en) * | 1980-10-24 | 1982-05-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field-effect transistor |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0430289A2 (en) * | 1989-12-01 | 1991-06-05 | Hughes Aircraft Company | Fabrication of self-aligned, T-gate hemt |
| EP0430289A3 (en) * | 1989-12-01 | 1995-08-16 | Hughes Aircraft Co | Fabrication of self-aligned, t-gate hemt |
| JPH03190246A (en) * | 1989-12-20 | 1991-08-20 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| US5391899A (en) * | 1991-10-29 | 1995-02-21 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor device with a particular gate structure |
| JPH05190869A (en) * | 1992-01-13 | 1993-07-30 | Nec Corp | Quantum small-cage wire type field-effect transistor and manufacture thereof |
| EP0592064A2 (en) * | 1992-08-19 | 1994-04-13 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor and method of production |
| US5358885A (en) * | 1992-08-19 | 1994-10-25 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a field effect transistor with a T-shaped gate electrode and reduced capacitance |
| EP0592064A3 (en) * | 1992-08-19 | 1995-08-16 | Mitsubishi Electric Corp | Field effect transistor and method of production |
| US5548144A (en) * | 1993-03-05 | 1996-08-20 | Mitsubishi Denki Kabushiki Kaisha | Recessed gate field effect transistor |
| US6159861A (en) * | 1997-08-28 | 2000-12-12 | Nec Corporation | Method of manufacturing semiconductor device |
| US6337262B1 (en) * | 2000-03-06 | 2002-01-08 | Chartered Semiconductor Manufacturing Ltd. | Self aligned T-top gate process integration |
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