JP2715868B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect transistor.

[0002]

2. Description of the Related Art A heterojunction field effect transistor (hereinafter, referred to as an HJFET) is a field effect transistor utilizing a two-dimensional electron gas accumulated at a heterojunction interface, and has excellent high speed and low noise. It has been put to practical use as an ultra-low noise high frequency amplifying element. In recent years, research and development of high-output FETs and integrated circuits using HJFETs have been actively conducted.

[0003] HJFET is undoped high purity GaAs.
Typically, an AlGaAs layer (electron supply layer) doped with a donor impurity is epitaxially grown on the layer (electron transit layer). In such a configuration, free electrons supplied from a donor in the AlGaAs layer move to an undoped GaAs layer having an electron affinity higher than that of the AlGaAs. Therefore, a two-dimensional electron accumulation layer is formed on the GaAs layer side of the heterojunction formed by the AlGaAs layer and the GaAs layer. Since the two-dimensional electron storage layer is formed in the undoped layer, electrons traveling therethrough are not scattered by donor impurities and have high mobility.

[0004] The HJFET uses the two-dimensional electron storage layer described above as a channel of the FET. Usually, A
The voltage applied to the gate electrode that has been Schottky-joined on the lGaAs electron supply layer causes the voltage below the gate electrode to decrease.
The accumulation state of the two-dimensional electrons is modulated, and the current flowing between the source electrode and the drain electrode is controlled. Where the source
When an electric field is applied between the drains, traveling two-dimensional electrons spread in the depth direction, and the electrons flow out to the buffer layer. Therefore, AlGaAs having a lower electron affinity than GaAs forming the electron transit layer under the electron transit layer.
By inserting a hetero buffer layer made of s, outflow of electrons to the buffer layer is prevented.

FIG. 3 is a schematic structural view of a conventional HJEFT using an AlGaAs / GaAs heterojunction. In the figure, an undoped GaAs buffer layer 32, an undoped AlGaAs hetero buffer layer 33, and an undoped GaAs electron transit layer 3 are formed on a semi-insulating GaAs substrate 31.
4. donor impurity-doped AlGaAs electron supply layer 35;
Donor impurity-doped GaAs contact resistance reducing cap layers 36 are sequentially stacked by epitaxial growth. Then, a gate electrode 37 is formed on the central surface of the electron supply layer 35, and source and drain electrodes 38 and 39 are provided on the cap layer 36, respectively.

[0006]

FIG. 4 is a block diagram of the H shown in FIG.
It is an energy band figure in a JFET structural drawing. When a high voltage is applied to the electron transit layer 34, impact ionization occurs. Here, when a part of holes generated by impact ionization is captured by a hole trap in the electron supply layer, the drain current increases because the net charge concentration in the electron supply layer increases. That is, it has recently been found that holes flowing from the electron transit layer to the electron supply layer are one of the causes of kink generation.

The undoped GaAs electron transit layer 34
At the heterojunction interface between the semiconductor layer and the undoped AlGaAs hetero buffer layer 33, there is an energy difference in the electron affinity and the sum of the electron affinity and the band gap. Due to such an energy barrier by the hetero buffer layer, two-dimensional electrons are prevented from flowing into the buffer layer. Get bigger,
An energy barrier for holes is created, and holes are also accumulated in the channel layer. This is also said to be one of the causes of a current anomaly called kink which is a problem in a high drain voltage region (E.I. Fujishiro et al., Japanese Journal of Applied Physics Eye, Vol. 27, No. 19, El 1
742, 1988; I. Fujishir
o. et al. , Jpn. J. Appl. Phys
s. , Vol. 27, no. 9, 1988, p. L17
42).

Further, in an AlGaAs / GaAs two-dimensional electron gas FET, i-A
_{l 0. 8 Ga 0. 2} As 0. 8 Sb 0. Examples are in JP-A-4-177841 using a ₂ hetero buffer layer.

[0009] An object of the present invention is to provide a field effect transistor which solves the above problems.

[0010]

In order to achieve the above object, a field effect transistor according to the present invention has a semiconductor substrate, a hetero buffer layer made of a first semiconductor formed on the semiconductor substrate, and a hetero buffer layer. An electron transit layer composed of a second semiconductor adjacent to the buffer layer, a hole barrier layer composed of a third semiconductor adjacent to the electron transit layer, and an electron composed of a fourth semiconductor adjacent to the hole barrier layer And a supply layer.

The characteristics of each layer constituting the field effect transistor are described below.

(1) The third semiconductor constituting the hole barrier layer is larger than the sum (x ₄ + Eg ₄ ) of the electron affinity (x ₄ ) and the band gap (Eg ₄ ) of the fourth semiconductor. It has the sum (x ₃ + Eg ₃ ) of the electron affinity (x ₃ ) and the band gap (Eg ₃ ), and has the electron affinity (x ₃ ) of the _third semiconductor and the electron affinity (x ₄ ) of the fourth semiconductor. The difference (x ₃ −x ₄ ) is the thermal energy (3 kT /
It is much smaller than 2). k is the Boltzmann constant, T is the absolute temperature, and (3 kT / 2) is the thermal energy of the electron.

(2) The first semiconductor constituting the hetero buffer layer has an electron affinity (x ₁ ) smaller than the electron affinity (x ₂ ) of the adjacent second semiconductor, and the second semiconductor Sum of the electron affinity (x ₂ ) and band gap (Eg ₂ ) of the first semiconductor (x ₂ + Eg ₂ ), and the sum of the electron affinity (x ₁ ) and the band gap (Eg ₁ ) of the first semiconductor (x ₁ + Eg ₁ ) ) Difference (x ₂ + Eg ₂ −x ₁ −E)
g ₁ )) is sufficiently smaller than the thermal energy (3 kT / 2) of the electrons.

(3) The fourth semiconductor forming the electron supply layer contains an n-type impurity and has an electron affinity (x ₂ ) smaller than the electron affinity (x ₂ ) of the second semiconductor forming the electron transit layer. x ₄ ).

[0015]

The operation of the present invention will be described using a GaAs field effect transistor.

By using GaAs _x P _{1 -x} as a hole barrier layer sandwiched between the electron supply layer and the electron transit layer of the FET and selecting a suitable composition ratio thereof, the hole barrier layer and Although the difference between the electron affinities of the electron supply layers is smaller than the thermal energy of the electrons, the sum of the electron affinity and the energy gap of the hole barrier layer can be made larger than that of the electron supply layers. It is possible to prevent holes from flowing into the supply layer and being captured by the hole trap. At the same time, Al _y Ga _{1 -y}
By using As _z Sb ₁ -z and selecting the composition ratio to an appropriate value, it is possible to prevent the two-dimensional electrons from spreading to the buffer layer with an electron affinity smaller than the electron affinity of the adjacent electron transit layer. In the sum of the electron affinity and the band gap, the energy difference between the electron transit layer and the hetero buffer layer can be made smaller than the thermal energy of the electrons, so that holes can be prevented from accumulating in the electron transit layer.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. Here, as an example, AlGaAs / GaAs based H
An example of the JFET will be described. However, the present invention is not limited to this material. By knowing the energy gap of the material forming the electron transit layer and the electron supply layer, the electron affinity between the electron supply layer and the hole barrier layer can be improved. Only the sum of the energy gap and the electron supply layer has an energy difference with the electron supply layer, and the bulk semiconductor used as the hole barrier layer can be selected so that the energy difference of the electron affinity is smaller than the thermal energy difference of the electrons. At the same time, in the electron transit layer and the hetero buffer layer, there is an energy difference only in electron affinity, and the energy difference between the electron affinity and the sum of the band gap is smaller than the thermal energy difference of electrons. A bulk semiconductor used as a buffer layer can be selected.

FIG. 1 is a sectional view of an element according to an embodiment of the present invention, and FIG. 2 is an energy band diagram thereof.

As shown in FIG. 1, the following layers are formed on a semi-insulating GaAs substrate 11 by epitaxial growth. 12: undoped GaAs buffer layer _13:... Undoped _{Al 0 8 Ga 0 2 As 0} 8 Sb
_{. 0 2} hetero buffer layer (having a thickness of about 1000A (angstrom)) 14: undoped GaAs electron transit layer _15:.. Undoped GaAs _{0 4 3} P _{0 5 7} hole blocking layer (having a thickness of several tens A～100A) 16 _{:. n + -Al 0 3 Ga} 0 7 as electron supply layer _17:. n ₊ -GaAs contact layer where, n ₊ -GaAs layer 17 is a layer for making an ohmic contact better.

Next, source and drain electrodes 18 and 19 made of ohmic contact metal are formed on the surface of the growth substrate.
Is formed by a lift-off method or the like, and an undoped Ga in which a two-dimensional electron gas is formed by an alloy method of heating or the like.
It is in contact with the As layer 14.

Next, the source and drain electrodes 18 and 1
The n ₊ -GaAs layer 17 between the portions 9 is partially removed by etching, and a gate electrode 110 made of a metal for Schottky junction is formed in that portion.

The hetero buffer layer 13 is made of, for example, undoped Al _0.8 Ga when the electron transit layer is made of GaAs <sub>.
0. 2 As 0. 8 Sb</sub> 0. By using _two mixed crystals, also the hole barrier layer 15, for example, the electron supply layer A
l _{0. 3} Ga _{0 .7} undoped Ga when the As
The use of _{As 0. 4 3 P 0.} 5 7 mixed crystal,
An energy band diagram as shown in FIG. 2 is obtained. Figure 2
Reference numerals 12, 13, 14, 15, and 16 of 1 are reference numerals, respectively.
25, 24, 23, 22, and 21.

By selecting the above composition ratio for the hole barrier layer, the Al _0.3 Ga _0.7 As layer 16 and the Ga
As _{0. 4 3} Although P _{0. 5 7} layers 15 and there is no difference in the electron affinity at the heterojunction interface, is the sum of electron affinity and energy gap having a difference of about 0.2 eV, electrons from the electron transit layer Since a barrier of about 0.3 eV is formed when holes flow into the supply layer, it is possible to prevent holes from flowing from the electron transit layer to the electron supply layer.

At the same time, by selecting the above composition ratio for the hetero buffer layer, the GaAs layer 14 and the Al
_{0. 8 Ga 0. 2 As} 0. 8 Sb 0. The difference in the electron affinity at the heterojunction interface between _two layers 13 Despite about 0.4 eV, the energy difference in the sum of the electron affinity and band gap And holes can be prevented from accumulating in the electron transit layer. As a result, kink can be suppressed twice.

The composition of GaAsP and AlGaAsSb is not limited to the above, and holes are simultaneously formed according to the composition of the electron supply layer, the electron transit layer, etc. so that holes do not flow from the electron transit layer to the electron supply layer. The hole may be selected so that the holes do not accumulate in the electron transit layer. In the case where the hetero buffer layer and the hole barrier layer are made of a material having lattice mismatch with the substrate, the hetero junction can be satisfactorily performed if the thickness is less than the critical thickness.

[0026]

According to the present invention, it is possible to avoid a current abnormal phenomenon (kink) which has been a problem in a high drain voltage region of a conventional HJFET. Further, the manufacturing method is the same as that of the conventional hetero buffer layer except that a thin film of a semiconductor having a strain is used as the material of the conventional hetero buffer layer. The hole barrier layer and the hetero buffer layer can be freely selected, and can be applied to a wide range of fields.

[Brief description of the drawings]

FIG. 1 is a sectional view of an element structure showing an embodiment of an HJFET of the present invention.

FIG. 2 is an energy band diagram of the embodiment of the HJFET of the present invention.

FIG. 3 is a cross-sectional view of a device structure of a conventional HJFET.

FIG. 4 is an energy band diagram of a conventional HJFET.

[Explanation of symbols]

11 GaAs substrate 12 an undoped GaAs layer 13 an undoped _{Al 0. 8 Ga 0. 2} As 0. 8 Sb
_0.2 Layer 14 undoped GaAs layer 15 an undoped _{GaAs 0. 4 3 P 0.} 5 7 Layer 16 donor impurity doped _{Al 0. 3 Ga 0. 7} As layer 17 donor impurity-doped GaAs layer 18 source electrode 19 drain electrode 110 gate electrode 31 GaAs substrate 32 an undoped GaAs layer 33 an undoped _{Al 0. 3 Ga 0. 7} As layer 34 an undoped GaAs layer 35 donor impurity doped _{Al 0. 3 Ga 0. 7} As layer 36 donor impurity-doped GaAs layer 37 gate electrode 38 source electrode 39 Drain electrode

Claims (4)

(57) [Claims] 1. A semiconductor substrate, a hetero buffer layer made of a first semiconductor formed on the semiconductor substrate, an electron transit layer made of a second semiconductor adjacent to the hetero buffer layer, and the electron transit layer A field effect transistor comprising: a hole barrier layer made of a third semiconductor adjacent to the first semiconductor; and an electron supply layer made of a fourth semiconductor adjacent to the hole barrier layer. 2. The method according to claim 1, wherein the third semiconductor constituting the hole barrier layer has an electron affinity (x) possessed by a fourth semiconductor.
₄ ) and the sum of the band gap (Eg ₄ ) (x ₄ + Eg ₄
), The sum of the electron affinity (x ₃ ) and the band gap (Eg ₃ ) (x ₃ + Eg ₃ ), and the electron affinity of the third semiconductor (x ₃ ) and the electron affinity of the fourth semiconductor difference _{(x 4) (x 3 -x} 4) thermal energy (3 kT / 2) with electron (k is the Boltzmann constant, T
2. The field effect transistor according to claim 1, wherein the temperature is sufficiently smaller than the absolute temperature. 3. The first semiconductor constituting the hetero buffer layer according to claim 1, wherein the first semiconductor has an electron affinity (x ₁ ) smaller than an electron affinity (x ₂ ) of an adjacent second semiconductor, and The sum (x ₂ + Eg ₂ ) of the electron affinity (x ₂ ) and band gap (Eg ₂ ) of the _second semiconductor, the electron affinity (x ₁ ) and band gap (E
g ₁ ) difference (x ₂ + Eg ₂ ) of the sum (x ₁ + Eg ₁ )
-X ₁ -Eg ₁ ) is the thermal energy (3 kT) of the electron
2. The method according to claim 1, wherein the value is sufficiently smaller than (2).
Or a field-effect transistor according to claim 2 . 4. The electron supply layer according to claim 1, wherein the fourth semiconductor constituting the electron supply layer contains an n-type impurity, and is obtained from the electron affinity (x ₂ ) of the second semiconductor constituting the electron transit layer. 3. The field-effect transistor according to claim 1, wherein the field-effect transistor has a small electron affinity (x ₄ ).