JPH07169945A - Field effect transistor - Google Patents

Abstract

PURPOSE:To prevent the generation of an abnormal current by a method wherein a hole barrier layer is formed adjoining to an electron travelling layer, and an electron feeding layer is provided adjoining to the hole barrier layer. CONSTITUTION:There is no difference in the electron affinity on the heterojunction interface between an Al0.3Ga0.7As layer 16 and a GaAs0.43P0.57 layer 15. However, there is a difference of about 0.2eV in the sum of the electron affinity and an energy gap, and as a barrier of about 0.3eV is formed when a hole flows in the electron feeding layer 16 from an electron travelling layer 14, the flow-in of the hole to the electron feeding layer 16 from the electron travelling layer 14 can be prevented. Also, in spite of the fact that there is about 0.4eV in the difference of electron affinity on the heterojunction interface between the GaAS layer 14 and the Al0.8Ga0.2A0.8Sb0.2 layer 13, there is no energy difference in the sum of electron affinity and band gap, and the accumulation of a hole in the electron travelling layer 14 can be prevented. As a result, kinks can be doubly suppressed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to the structure of field effect transistors.

[0002]

2. Description of the Related Art A heterojunction field effect transistor (hereinafter referred to as "HJFET") is a field effect transistor utilizing a two-dimensional electron gas accumulated at a heterojunction interface and has excellent high speed and low noise. It has been put to practical use as an amplifying element for ultra-low noise and high frequency. Further, recently, research and development of high-power FETs using HJFETs, integrated circuits, and the like have been actively conducted.

HJFET is undoped high-purity GaAs
Typically, an AlGaAs layer (electron supply layer) doped with a donor impurity is epitaxially grown on the layer (electron transit layer). In such a structure, free electrons supplied from the donor in the AlGaAs layer move to the undoped GaAs layer having an electron affinity larger than that of the AlGaAs. Therefore, a two-dimensional electron storage layer is formed on the GaAs layer side of the heterojunction surface formed by the AlGaAs layer and the GaAs layer. Since the two-dimensional electron storage layer is formed in the undoped layer, the electrons traveling in the two-dimensional electron storage layer have high mobility without being scattered by donor impurities.

The HJFET uses the above-mentioned two-dimensional electron storage layer as a channel of the FET. Usually A
The voltage applied to the gate electrode that is Schottky-junctioned on the 1 GaAs electron supply layer causes 2
The accumulation state of the dimensional electrons is modulated, and the current flowing between the source electrode and the drain electrode is controlled. Where source
When an electric field is applied between the drains, traveling two-dimensional electrons spread in the depth direction, causing electrons to flow out to the buffer layer. Therefore, AlGaA having an electron affinity lower than that of GaAs forming the electron transit layer below the electron transit layer.
By inserting the hetero buffer layer made of s, the outflow of electrons to the buffer layer is prevented.

FIG. 3 is a schematic structural diagram of a conventional HJEFT using an AlGaAs / GaAs heterojunction. In the figure, an undoped GaAs buffer layer 32, an undoped AlGaAs heterobuffer layer 33, and an undoped GaAs electron transit layer 3 are provided on a semi-insulating GaAs substrate 31.
4, donor impurity-doped AlGaAs electron supply layer 35,
The donor impurity-doped GaAs contact resistance reducing cap layer 36 is sequentially laminated by an epitaxial growth method. A gate electrode 37 is formed on the surface of the central portion of the electron supply layer 35, and source and drain electrodes 38 and 39 are provided on the cap layer 36, respectively.

[0006]

FIG. 4 shows H shown in FIG.
It is an energy band figure in a JFET structure figure. When a high voltage is applied to the electron transit layer 34, impact ionization occurs. Here, if some of the holes generated by the impact ionization are trapped in the hole traps in the electron supply layer, the net charge concentration in the electron supply layer increases, and the drain current increases. That is, it has recently been found that holes flowing from the electron transit layer to the electron supply layer are one of the causes of the kink.

Also, the undoped GaAs electron transit layer 34
There is an energy difference between the electron affinity and the sum of the electron affinity and the band gap at the heterojunction interface between the undoped AlGaAs heterobuffer layer 33 and the undoped AlGaAs heterobuffer layer 33. Such an energy barrier by the heterobuffer layer prevents two-dimensional electrons from flowing into the buffer layer, but at the same time, the sum of the electron affinity and the energy gap is higher in the heterobuffer layer than in the electron transit layer. Getting bigger,
An energy barrier for holes is created, and holes are also accumulated in the channel layer. This is also said to be one of the causes of current anomalies known as kinks, which is a problem in the high drain voltage region (Each eye Fujishiro et al. Japanese Journal of Applied Physics Eye, Volume 27, Issue 19, El 1
See page 742, 1988: H.M. I. Fujishir
o. et al. , Jpn. J. Appl. Phy
s. , Vol. 27, No. 9, 1988, p. L17
42).

Further, in the AlGaAs / GaAs two-dimensional electron gas FET, in order to suppress the kink, i-A
_{l 0. 8 Ga 0. 2} As 0. 8 Sb 0. Examples are in JP-A-4-177841 using a ₂ hetero buffer layer.

An object of the present invention is to provide a field effect transistor which solves the above problems.

[0010]

In order to achieve the above object, a field effect transistor according to the present invention comprises a semiconductor substrate, a hetero buffer layer formed on the semiconductor substrate and comprising a first semiconductor, and the hetero buffer layer. An electron transit layer made of a second semiconductor adjacent to the buffer layer, a hole barrier layer made of a third semiconductor adjacent to the electron transit layer, and an electron made of a fourth semiconductor adjacent to the hole barrier layer. And a supply layer.

The features of each layer constituting this field effect transistor are shown below.

(1) The third semiconductor composing the hole blocking layer is larger than the sum (x ₄ + Eg ₄ ) of the electron affinity (x ₄ ) and the band gap (Eg ₄ ) of the fourth semiconductor. It has a sum of electron affinity (x ₃ ) and band gap (Eg ₃ ) (x ₃ + Eg ₃ ), and also has an electron affinity (x ₃ ) of the _third semiconductor and an electron affinity (x ₄ ) of the fourth semiconductor. The difference (x ₃ −x ₄ ) is the thermal energy of the electron ( ₃ kT /
It is sufficiently smaller than 2). k is the Boltzmann constant, T is the absolute temperature, and (3kT / 2) is the thermal energy of the electron.

(2) The first semiconductor forming the heterobuffer layer has an electron affinity (x ₁ ) smaller than the electron affinity (x ₂ ) of the adjacent second semiconductor, and the second semiconductor (X ₂ + Eg ₂ ) of the electron affinity (x ₂ ) and bandgap (Eg ₂ ) of the first semiconductor, and (x ₁ + Eg ₁ ) of the electron affinity (x ₁ ) and bandgap (Eg ₁ ) of the first semiconductor ) Difference (x ₂ + Eg ₂ −x ₁ −E
g ₁ )) is sufficiently smaller than the thermal energy of electrons (3 kT / 2).

(3) The fourth semiconductor forming the electron supply layer contains an n-type impurity, and has an electron affinity (x ₂ ) smaller than the electron affinity (x ₂ ) of the second semiconductor forming the electron transit layer. x ₄ ).

[0015]

The operation of the present invention will be described using a GaAs field effect transistor.

Using GaAs _x P _{1 -X} as a hole blocking layer sandwiched between the electron supply layer and the electron transit layer of the FET,
By selecting the composition ratio to an appropriate value, the difference in electron affinity between the hole blocking layer and the electron supply layer is smaller than the thermal energy of electrons, but the sum of the electron affinity and energy gap of the hole blocking layer is Since it can be made larger than the electron supply layer, holes can be prevented from flowing into the electron supply layer from the electron transit layer and trapped by the hole traps.
At the same time, Al _y Ga _{1 -y} As is used as a hetero buffer layer.
By using _z sb ₁ -z and selecting its composition ratio to an appropriate value, two-dimensional electrons having a smaller electron affinity than the electron affinity of the adjacent electron transit layer are prevented from spreading to the buffer layer, while In the sum of the affinity and the band gap, the energy difference between the electron transit layer and the heterobuffer layer can be made smaller than the thermal energy of the electrons, so that holes can be prevented from accumulating in the electron transit layer.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. Here, as an example, AlGaAs / GaAs H
Examples of the JFET will be described, but the material is not limited to this material, and the electron affinity in the electron supply layer and the hole barrier layer can be obtained by knowing the energy gap of the material forming the electron transit layer and the electron supply layer. The bulk semiconductor to be used as the hole blocking layer can be selected so that it has an energy difference with the electron supply layer only in the sum of the energy gap and the energy difference of the electron affinity is smaller than the thermal energy difference of the electrons. At the same time, in the electron transit layer and the hetero-buffer layer, there is an energy difference only in the electron affinity, and the energy difference between the electron affinity and the sum of the band gap is smaller than the thermal energy difference of the electrons. The bulk semiconductor used as the buffer layer can be selected.

FIG. 1 shows a cross-sectional view of an element of an embodiment of the present invention, and FIG. 2 shows its energy band diagram.

As shown in FIG. 1, the following layers are formed on the semi-insulating GaAs substrate 11 by epitaxial growth. 12: undoped GaAs buffer layer _13:... Undoped _{Al 0 8 Ga 0 2 As 0} 8 Sb
_{. 0 2} hetero buffer layer (having a thickness of about 1000A (angstrom)) 14: undoped GaAs electron transit layer _15:.. Undoped GaAs _{0 4 3} P _{0 5 7} hole blocking layer (having a thickness of several tens A～100A) 16 _{:. n + -Al 0 3 Ga} 0 7 as electron supply layer _17:. n ₊ -GaAs contact layer where, n ₊ -GaAs layer 17 is a layer for making an ohmic contact better.

Next, the source and drain electrodes 18 and 19 made of a metal for ohmic contact are formed on the surface of the growth substrate.
Is formed by a lift-off method or the like, and an undoped Ga is formed in which a two-dimensional electron gas is formed by an alloy method of applying heating or the like.
It is in contact with the As layer 14.

Next, the source and drain electrodes 18 and 1
The n ₊ -GaAs layer 17 between 9 is partially removed by etching, and a gate electrode 110 made of a Schottky junction metal is formed in that portion.

The heterobuffer layer 13 is, for example, undoped Al _0.8 Ga when the electron transit layer is GaAs <sub>.
0. 2 As 0. 8 Sb</sub> 0. By using _two mixed crystals, also the hole barrier layer 15, for example, the electron supply layer Al
_{0. 3} Ga _{0. 7} undoped GaAs when the As
_0. By using _{4 3} P _{0. 5 7} mixed crystal, the energy band diagram as shown in FIG. 2 is obtained.

[0023] By choosing a set of ratios, such as described above as a hole blocking _{layer, Al 0. 3 Ga 0. 7} As layers 16 and G
GaAs _{0. 4 3} Although P _{0. 5 7} layers 15 and there is no difference in the electron affinity at the heterojunction interface, is the sum of electron affinity and energy gap having a difference of about 0.2 eV, electrons from the electron transit layer Since a barrier of about 0.3 eV is formed when holes flow into the supply layer, it is possible to prevent holes from flowing from the electron transit layer to the electron supply layer.

At the same time, by selecting the above composition ratio for the hetero buffer layer, the GaAs layer 14 and the Al
_{0. 8 Ga 0. 2 As} 0. 8 Sb 0. The difference in the electron affinity at the heterojunction interface between _two layers 13 Despite about 0.4 eV, the energy difference in the sum of the electron affinity and band gap Can be prevented, and holes can be prevented from accumulating in the electron transit layer. This enables double suppression of kinks.

The composition of GaAsP and AlGaAsSb is not limited to this, and depending on the composition of the electron supply layer, the electron transit layer, etc., holes do not flow into the electron supply layer from the electron transit layer at the same time. The holes should not be accumulated in the electron transit layer. Further, in the case where the hetero buffer layer or the hole blocking layer is made of a material having a lattice mismatch with the substrate, if the thickness is not more than the critical film thickness, good hetero junction can be achieved without any problem.

[0026]

According to the present invention, it is possible to avoid the current abnormal phenomenon (kink) which has been a problem in the high drain voltage region of the conventional HJFET. In addition, the manufacturing method is relatively easy because it is the same as the conventional method except that a semiconductor thin film having a strain is used as the material of the conventional heterobuffer layer, and it is positive due to the band gap of the electron supply layer and the electron transit layer. The hole barrier layer and the hetero buffer layer can be freely selected, and the application in a wide range of fields is possible.

[Brief description of drawings]

FIG. 1 is a sectional view of an element structure showing an embodiment of an HJFET of the present invention.

FIG. 2 is an energy band diagram of an example of HJFET of the present invention.

FIG. 3 is a cross-sectional view of a conventional HJFET device structure.

FIG. 4 is an energy band diagram of a conventional HJFET.

[Explanation of symbols]

11 GaAs substrate 12 an undoped GaAs layer 13 an undoped _{Al 0. 8 Ga 0. 2} As 0. 8 Sb
_0.2 Layer 14 undoped GaAs layer 15 an undoped _{GaAs 0. 4 3 P 0.} 5 7 Layer 16 donor impurity doped _{Al 0. 3 Ga 0. 7} As layer 17 donor impurity-doped GaAs layer 18 source electrode 19 drain electrode 110 gate electrode 31 GaAs substrate 32 an undoped GaAs layer 33 an undoped _{Al 0. 3 Ga 0. 7} As layer 34 an undoped GaAs layer 35 donor impurity doped _{Al 0. 3 Ga 0. 7} As layer 36 donor impurity-doped GaAs layer 37 gate electrode 38 source electrode 39 Drain electrode

Claims (4)

[Claims] 1. A semiconductor substrate, a heterobuffer layer made of a first semiconductor formed on the semiconductor substrate, an electron transit layer made of a second semiconductor adjacent to the heterobuffer layer, and an electron transit layer. A field effect transistor comprising a hole blocking layer made of a third semiconductor adjacent to the hole blocking layer, and an electron supply layer made of a fourth semiconductor adjacent to the hole blocking layer. 2. The third semiconductor composing the hole barrier layer according to claim 1, has an electron affinity (x
₄ ) and bandgap (Eg ₄ ) sum (x ₄ + Eg ₄ )
Larger electron affinity (x ₃ ) and bandgap (E
g ₃₎ has a sum (x ₃ + eg ₃₎ of, and the difference between the third semiconductor electron affinity and (x ₃₎ fourth semiconductor electron affinity _{(x 4) (x 3 -x} 4) Electronic Thermal energy of (3kT / 2) (k is Boltzmann's constant, T is absolute temperature)
The field effect transistor according to claim 1, wherein the field effect transistor is sufficiently smaller than 3. The first semiconductor constituting the heterobuffer layer according to claim 1, has an electron affinity (x ₁ ) smaller than an electron affinity (x ₂ ) of an adjacent second semiconductor, and Sum of electron affinity (x ₂ ) and band gap (Eg ₂ ) of the second semiconductor (x ₂ + Eg ₂ ), electron affinity (x ₁ ) and band gap (Eg ₁ ) of the first semiconductor
The difference of the sum (x ₁ + Eg ₁₎ of the _{(x 2 + Eg 2 -x 1} -Eg
₁₎ is a field effect transistor of claim 1, wherein the sufficiently smaller than the energy (3 kT / 2) with electron. 4. The fourth semiconductor constituting the electron supply layer according to claim 1 contains an n-type impurity, and is obtained from the electron affinity (x ₂ ) of the second semiconductor constituting the electron transit layer. The field effect transistor according to claim 1, which has a small electron affinity (x ₄ ).