JP2689877B2 - Heterojunction FET manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to a method for manufacturing a heterojunction FET.

[0002]

2. Description of the Related Art As a compound semiconductor FET, an FET using a two-dimensional electron gas (2DEG) layer induced between two semiconductor layers having different band gaps and having a heterojunction having a smaller band gap is known. Regarding this, for example, “Heterojunction type field effect transistor (Japanese Patent Laid-Open Publication No. Hei 1-1432” by Inoue and Matsuno) is described.
No. 7).

A conventional hetero FET will be described with reference to FIG. As shown in FIG. 5A, semi-insulating GaA
An undoped GaAs buffer layer 2 is formed on the s substrate 1, and then, as shown in FIG.
_0.2 Ga _0.8 As hetero buffer layer 3, undoped In
_{A 0.2} Ga _0.8 As channel layer 4 is formed, and then, as shown in FIG.
As shown in (c), an n-type Al _0.2 Ga _0.8 As electron supply layer 5 and a gate electrode 9 are formed. 7 and 8 are n
A source electrode and a drain electrode provided via the type GaAs contact layer 6. In this way, n-type Al
_0.2 Ga _0.8 As Electron supply layer 5 and undoped In _0.2 G
a _0.8 As channel layer 4 and undoped Al _0.2 Ga _0.8
A 2DEG layer (not shown) is formed in the potential well made of the As heterobuffer layer 3. In the FET, the current flowing through the 2DEG layer between the source electrode 7 and the drain electrode 8 is controlled by the voltage applied to the gate electrode 9, and in order to improve the performance of the device, (1) 2D
High sheet electron concentration and high electron mobility in EG layer (2) Good pinch-off characteristics (leak current is small) gm
Is important, but conventionally undoped GaA
s layer 2 or n-type GaAs contact layer 6 at 450 ° C.
From 520 ° C. to 520 ° C. at a constant substrate temperature.

[0004]

However, it is not always true that the optimum temperature for epitaxial growth is the same for all the above-mentioned substances, and there is room for improvement of the electron mobility and gm described above. I can say.

An object of the present invention is to provide a manufacturing method capable of realizing a heterojunction FET having further improved electric characteristics.

[0006]

SUMMARY OF THE INVENTION A heterojunction FE of the present invention is provided.
The manufacturing method of T is that GaAs is formed on the surface of a semi-insulating GaAs substrate.
Buffer layer, Al _x Ga _1-x As heterobuffer layer (0
<X <1), the In _y Ga _1-y As channel layer (0 <y <1) having a smaller bandgap than the Al _x Ga _1-x As heterobuffer layer and the In _y Ga _1-y As channel layer Large bandgap Al _z Ga _1-z As
Heterojunction F including a step of sequentially epitaxially growing an electron supply layer (0 <z <1) to form a heterojunction structure
In the manufacturing method of ET, the Al _z Ga _1-z As electron supply layer and the GaAs buffer layer are grown at a substrate temperature of 600 ° C. or higher and 700 ° C. or lower, respectively, and In _y Ga _1-y
The As channel layer and the Al _x Ga _1-x As heterobuffer layer are grown at 400 ° C. or higher and 500 ° C. or lower, respectively.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 1A, after the semi-insulating GaAs substrate 1 is thermally cleaned in the growth chamber of the MBE apparatus, the undoped GaAs buffer is grown by MBE at a growth temperature of 600 ° C. to 700 ° C., for example 600 ° C. A layer 2A (about 1 μm thick) is grown. Next, after lowering the growth temperature to 400 ° C. to 500 ° C. (for example, 500 ° C.), as shown in FIG. 1B, undoped Al _0.2 Ga
_{The 0.8} As heterobuffer layer 3 has a thickness of about 100 nm, and the undoped In _0.2 Ga _0.8 As channel layer 4 has a thickness of about 15 nm.
nm, and then the growth temperature is set to 600 ° C. again.
The temperature was raised to 700 ° C., for example 600 ° C., and as shown in FIG. 1C, an n-type Al _0.2 Ga _0.8 As electron supply layer 5A was grown to a thickness of about 400 nm, and then an n-type GaAs contact layer 6A was grown. Here, in the n-type Al _0.2 Ga _0.8 As electron supply layer 5A, Si as an n-type impurity is Nd = 2 × 10.
^{Doped at} a concentration of ¹⁸ cm ^-3 . Next, the n-type GaAs contact layer 6 is formed and patterned to form the gate electrode 9 and the like.

2D at 77K of a heterojunction FET
N-type Al with electron mobility μ of EG layer and sheet electron concentration ns
The growth temperature dependence of the _0.2 Ga _0.8 As electron supply layer is shown.
However, the growth temperature of the undoped GaAs buffer layer 2A is the same as that of the n-type Al _0.2 Ga _0.8 As electron supply layer 5A, and the undoped Al _0.2 Ga _0.8 As heterobuffer layer 3 and the undoped In _0.2 Ga _0.8 As channel layer 4 are formed.
Has a growth temperature of 500 ° C. Since it is difficult to grow an In _y Ga _1-y As layer at 550 ° C. or higher, it has been conventionally required to grow 4
It had grown at a temperature of 50 ° C to 520 ° C.

From this, by growing the n-type Al _0.2 Ga _0.8 As electron supply layer 5A and the undoped GaAs buffer layer 2A at a high temperature of 600 ° C. to 700 ° C., 2
It can be seen that the electron mobility μ of the DEG layer and the sheet electron concentration ns can be greatly increased. This is probably because, as one of the causes, the growth temperature is optimized, the activation rate of impurities is improved, and sufficient electrons are supplied to the 2DEG layer. n-type Al _0.2 Ga _0.8 As supply layer 600
When grown at a high temperature of ℃ to 700 ℃, electron mobility μ and sheet electron concentration ns are μ = 2.5 × 10 ⁴ cm, respectively.
² / v · s, ns = 2.4 × 10 ¹² cm ⁻² , which is 25% higher than that of the conventional example.

Further, in FIG. 3, undoped Al _0.2 Ga _0.8
The long temperature dependence of the leakage current of an As heterobuffer layer is shown. However, the growth temperature of the undoped In _0.2 Ga _0.8 As channel layer 4 is 500 ° C., the undoped GaAs buffer layer 2, the n-type Al _0.2 Ga _0.8 As electron supply layer 5 and the n-type Al _0.2 Ga _0.8 As electron supply layer 5.
The growth temperature of the mold contact layer 6 is 600 ° C.

It can be seen that when the growth temperature is lowered by 100 degrees from 600 ° C., the leakage current sharply decreases (the pinch-off characteristic is improved) and the resistance is increased. From this, Al _0.2 G
In the a _0.8 As heterobuffer layer, the leakage current is reduced to 1/1000 by growing at a low temperature of 400 ° C to 500 ° C.
Can be suppressed. A growth temperature of less than 400 ° C. is not preferable because it tends to polycrystallize and the crystallinity deteriorates. Then, a gate electrode 9 and a source electrode 7 are formed on the epitaxial crystal by a well-known photolithography method.
The heterojunction FET is manufactured by forming the drain electrode 8 and the drain electrode 8.

2D between source electrode 7 and drain electrode 8
The current flowing through the EG layer is controlled by the voltage applied to the gate electrode 9, and the pinch-off characteristic is good because the undoped Al _0.2 Ga _0.8 As heterobuffer layer 3 is grown at a low temperature. In addition, n-type Al _0.2 Ga _0.8 As Since the electron supply layer is grown at a high temperature, the electron mobility μ and the sheet electron concentration ns are increased, and the transconductance gm of the FET is increased by 25% as compared with the conventional structure.

FIG. 4 is a sectional view for explaining a modification of the embodiment.

The process up to the formation of the undoped In _0.2 Ga _0.8 As channel layer 4 is the same as in the first embodiment.

Next, the growth temperature is raised to 600 ° C. to 700 ° C., for example 600 ° C., and an undoped Al _0.2 Ga _0.8 As layer 5-1A having a thickness of 3 nm is formed by the MBE method. The Ga beam supply is stopped at the same temperature, and Si
A δ-doped layer 5-2A (Si sheet concentration 5 × 10 ¹² cm ⁻² ) is formed by applying a beam, and the Si beam is stopped to form Ga.
The beam is re-supplied and the undoped A with a thickness of 30 nm
l _0.2 Ga _0.8 As layer 5-3A is formed. Thus δ
An electron supply layer having a doped structure is formed.

Thus, the electron mobility μ and the sheet electron concentration ns of the 2DEG layer at 77K are increased by about 30%, compared with the conventional example described with reference to FIG.
= 2.6 × 10 ⁴ cm ² / V · S, ns = 2.5 × 10
It became ¹² cm ^-2 . The mutual conductance gm is 30.
% Increased. These numbers are better than those according to one embodiment because the electron supply layer has a δ-doped structure.

[0018]

As described above, according to the present invention, Al _z
A Ga _1-z As electron supply layer and a GaAs buffer layer are grown at a substrate temperature of 600 ° C. to 700 ° C., and an Iny Ga 1-y As channel layer and an Al x Ga 1-x As hetero buffer layer are grown.
By growing at each optimized growth temperature of 0 ° C. to 500 ° C., the activation rate of the Alz Ga1-z As electron supply layer is increased, and the sheet electron concentration and electron mobility of the 2DEG layer can be significantly increased. It was possible, and the pinch-off characteristic was very good. Therefore, mutual conductance g
Heterojunction F in which m is increased by 25 to 30% as compared with the conventional example
It has become possible to manufacture ET.

[Brief description of the drawings]

FIG. 1 (a) to (c) for explaining an embodiment of the present invention.
FIG.

FIG. 2 shows electron mobility μ and sheet electron concentration n of 2DEG layer.
3 is a graph showing the growth temperature dependence of an n-type Al _0.2 Ga _0.8 As electron supply layer of s.

FIG. 3 is a graph showing the growth temperature dependence of the leakage current of an undoped Al _0.2 Ga _0.8 As heterobuffer layer.

FIG. 4 is a sectional view for explaining a modification of the embodiment.

FIG. 5 is a process sequence cross-sectional rain which is divided into (a) to (c) for explanation of a conventional example.

[Explanation of symbols]

1 semi-insulating GaAs layer 2,2A undoped GaAs buffer layer 3 of undoped Al _0.2 Ga _0.8 As hetero buffer layer 4 of undoped In _0.2 Ga _0.8 As channel layer 5, 5A n-type Al _0.2 Ga _0.8 As electron supply layer 5-1A, 5 -2A, 5-3A Electron supply layer having δ-doped structure 6, 6A n-type GaAs contact layer 7 Source electrode 8 Drain electrode 9 Gate electrode

Claims (2)

(57) [Claims] 1. A GaAs buffer layer and an Al _x Ga _1-x As hetero buffer layer (0 <
x <1), the Al _x Ga _1-x As hetero buffer layer than a band smaller In _y Ga _1-y As channel layer gaps (0 <y <1) and said In _y Ga _1-y As band than the channel layer Heterojunction FE including a step of sequentially epitaxially growing Al _z Ga _1-z As electron supply layers (0 <z <1) having a large gap to form a heterojunction structure
In the manufacturing method of T, the Al _z Ga _1-z As electron supply layer and the GaAs buffer layer are grown at a substrate temperature of 600 ° C. or higher and 700 ° C. or lower, respectively, and In _y Ga _1-y A
A method of manufacturing a heterojunction FET, comprising growing an s channel layer and an Al _x Ga _1-x As heterobuffer layer at 400 ° C. or higher and 500 ° C. or lower, respectively. 2. The method for manufacturing a heterojunction FET according to claim 1, wherein x = y = z = 0.2.