JP2728121B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a III-V compound semiconductor and a method of manufacturing the same.

[0002]

2. Description of the Related Art III-V represented by GaAs and InP
Field effect transistors such as MESFETs and high electron mobility transistors (HEMTs) using group III compound semiconductors
Widely applied to high frequency devices and low noise devices. Recently, its low power consumption has attracted attention, and its use as an optical communication IC has been considered.

However, recently, in a field effect transistor using a compound, gm, f
It has been pointed out that device characteristics such as t and Vt fluctuate (Yannick Gobert et al .: III, Transactions, ON, Electron Device Magazine)
Vol. 41, pp. 299-305 1994: Yan
nick Gobert et al. IEEE Tr
ansactionson Electron Dev
ices, Vol 41, pp294-305, 199
4).

In order to solve this problem, it is effective to form a back gate under the channel and compensate for the temperature fluctuation. For this reason, a normal MESFE as shown in FIG.
In the T structure, a structure is proposed in which ap ⁻ layer 102 and a p ⁺⁺ layer 103 are provided below an n-GaAs operation layer 100 provided with a gate 105 as an i-GaAs layer 101 as a buffer layer. -343434).

For the same purpose, a semi-insulating GaAs substrate 10
A method using a p-type GaAs substrate instead of 4 has also been attempted.

[0006] Further, as shown in FIG.
A structure is proposed in which only the lower part of the gate region is formed of the p-layer 107 except for the p-type wiring portion. Then, an ion implantation method is used to fabricate this structure (Japanese Patent Laid-Open No.
4-59961 gazette).

[0007]

The above-mentioned prior arts have the following problems. First, in order to form a back gate for temperature compensation control, in a structure using a p-type substrate or a p-layer buffer, the conventional process can be used as it is, and there is no problem in device fabrication, but the p-layer extends to the source and drain regions. , The parasitic capacitance increases, and g
This causes deterioration of device characteristics such as m and fT.

A structure in which a p-layer is formed only below the gate region does not have the above-mentioned problem, and is effective in a MESFET structure.
When the present invention is applied to a HEMT or a doped channel FET having a / GaAs heterostructure, there is a concern that the source resistance may increase. Also, ion implantation is used for fabricating the structure, but it is difficult to control the n-type and p-type doping by ion implantation, and it is necessary to heat the substrate to 800 ° C. or higher for activation. There is a problem.

Therefore, an object of the present invention is to provide a field effect transistor which solves such a problem, particularly for a field effect transistor having a heterostructure, and a method of manufacturing the same.

[0010]

According to the present invention, III-
In a field effect transistor using a group V compound semiconductor, a gate electrode is formed in an n-type conduction type channel, and only a lower portion of an n-type semiconductor layer including a gate electrode portion is a p-type conduction type semiconductor layer. in form, the extraction electrode on a portion thereof disposed, source, drain part forms a lower semiconductor layer of the high-resistance than the channel, also forms a portion connecting with the channel n ⁺ semiconductor layer, the n ⁺ semiconductor A field effect transistor having a structure in which an ohmic electrode is provided on a layer is obtained.

According to the present invention, there is provided a field-effect transistor in which an n-type channel is formed by a heterojunction of two semiconductor layers having different electron affinities.

According to the present invention, the n ⁺ -type semiconductor layers in the source and drain regions are formed of a semiconductor layer having a higher electron affinity than the semiconductor layer forming the channel. Is obtained.

According to the present invention, in a method of manufacturing a field effect transistor using a group III-V compound semiconductor, a p-type semiconductor layer is grown on a semi-insulating substrate ,
An n-type semiconductor layer serving as a channel layer is sequentially grown thereon ,
After a gate electrode serving as a gate is formed over the channel layer , the other portions including the p-type semiconductor layer are removed by etching, except for the gate portion, and thereafter, metalorganic vapor phase epitaxy or metalorganic molecules are removed. First, a high-resistance semiconductor layer is formed on the channel by selective growth using a line epitaxy method.
A method for manufacturing a field effect transistor is provided, wherein the source and drain regions are selectively formed by growing to the lower end of the layer and subsequently growing the n ⁺ semiconductor layer to the surface .

[0014]

In the present invention, the p-layer used as the back gate is present only in the gate region, so that the parasitic capacitance can be reduced and the device characteristics can be prevented from deteriorating. In addition, by using a semiconductor layer having a high electron affinity for the source and drain regions, the source resistance can be reduced and gm and fT can be increased, particularly in a field effect transistor having a heterostructure. Also, in the case of fabricating this structure, selective growth by metalorganic vapor phase epitaxy or metalorganic molecular beam epitaxy is used instead of ion implantation, so that controllability such as doping concentration is high, and the material of the semiconductor layer is also used. It can be diversified and the most suitable material can be selected. The process is advantageous because it does not require a high temperature of 700 ° C. or more.

[0015]

FIG. 1 is a sectional view showing the structure of a first embodiment of the field effect transistor of the present invention. FIG. 1 shows a case where the present invention is applied to a HEMT structure. 1, an i-GaAs buffer layer (3) is formed on a semi-insulating GaAs substrate 10.
00 nm) 11, p-GaAs layer (10 nm, 1 × 10
¹⁸ cm ^-3 ) 12, i-GaAs channel layer (20 nm)
13, n-AlGaAs electron supply layer (30 nm, 2 × 1
0 ¹⁸ cm ^-3 ) 14 are sequentially formed, and WS
A T-type gate electrode 20 made of i is formed. Furthermore, in the source and drain regions, the i-GaAs selective growth layer (310 nm) 30 and the n ⁺ -GaAs selective growth layer (50
nm, 5 × 10 ¹⁸ cm ⁻³ ) 31 and an ohmic metal electrode 4 of AuGe / Ni / Au formed thereon.
0 is formed.

FIG. 2 shows a second embodiment of the field effect transistor, in which the present invention is applied to a doped channel FET structure. The i-GaAs channel layer 13 of FIG.
n-GaAs instead of the n-AlGaAs electron supply layer 14
Channel layer (20 nm, 2 × 10 ¹⁸ cm ⁻³ ) 15, i−
An AlGaAs barrier layer (300 nm) 16 is used. Others are the same as the configuration of FIG.

Although the i-GaAs buffer layer 11 is provided in consideration of the influence of contamination at the substrate / epi interface, it may be omitted if there is no particular effect.

Next, a method for manufacturing the field effect transistor of the present invention will be described below with reference to the drawings. FIG.
3A to 3E are process diagrams showing one embodiment of a method for manufacturing a field effect transistor of the present invention for a HEMT structure on a GaAs substrate.

First, as shown in FIG. 3A, an i-GaAs buffer layer 11 and a p-type buffer layer 11 are formed on a semi-insulating GaAs substrate 10 by molecular beam epitaxy (MBE).
-GaAs layer 12, i-GaAs channel layer 13, n-
An AlGaAs electron supply layer 14 is sequentially grown. Next, FIG.
As shown in (b), a T-type gate metal electrode 20 made of WSi is formed, and covered with a SiO ₂ film 50 by thermal CVD. Here, regarding the processing method of the T-type gate,
Omitted.

In FIG. 3C, using the SiO ₂ film 50 as a mask, wet or dry etching is performed.
The source and drain regions are etched down to the substrate. Next, as shown in FIG. 3D, metal organic chemical vapor deposition (MOV)
PE), metalorganic molecular beam epitaxial method (MOMB
E), the i-GaAs selective growth layer 30 and the n-GaAs selective growth layer 31 are
_The selective growth is performed sequentially using the _two films 50 as a mask. In the case of MOVPE, for example, in the case of MOVPE, good selective growth can be obtained by using trimethylgallium (TMG) and arsine (AsH ₃ ) as raw materials at a growth pressure of 10 Torr and a growth temperature of 600 ° C. Disilane (Si ₂ H ₆ ) was used as an n-type dopant.

Finally, as shown in FIG.
_{If the two} films 50 are removed and AuGe / Ni / Au is deposited as an ohmic metal electrode 40 in a self-aligned manner, a field effect transistor is completed.

In the field-effect transistor of the present invention, since the p-layer used as the back gate exists only in the gate region, the parasitic capacitance can be reduced, and Vt and the like can be modulated without deteriorating the device characteristics.

As a result of the selective growth of the source and drain regions, the source resistance can be reduced and the device characteristics can be improved.

In the embodiment, the HEM on the GaAs substrate is used.
Although the manufacturing method for the T structure is described, the FE having a heterojunction may be used in both the doped channel FET structure and the semiconductor-insulator-semiconductor structure (SISFET) shown in FIG.
Everything is applicable to T. The semiconductor layer is also made of AlG
Not limited to aAs / GaAs, other semiconductor materials such as InGaAs may be used. In particular, the channel layer and n ⁺ −
If InGaAs having an appropriate composition is used for the GaAs layer, further improvement in device characteristics can be expected. Needless to say, fabrication on an InP substrate is also possible. Further, the gate electrode material, ohmic electrode material, growth conditions and the like shown in the present invention are all optional.

[0025]

As described above, by using the field effect transistor of the present invention and the method of manufacturing the same,
Since the p layer used as the back gate exists only in the gate region, the parasitic capacitance can be reduced, Vt can be modulated without deteriorating the device characteristics, and the device characteristics fluctuation due to the temperature change can be compensated. it can.

Further, as a result of forming a low-resistance semiconductor layer in the source and drain regions by selective growth, source resistance can be reduced and device characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a structural sectional view showing a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a structural sectional view showing a field effect transistor according to a second embodiment of the present invention.

FIG. 3 is a process chart showing one embodiment of a method for manufacturing a field effect transistor of the present invention.

FIG. 4 is a structural sectional view showing an example of a conventional field effect transistor.

FIG. 5 is a structural sectional view showing another example of a conventional field-effect transistor.

[Explanation of symbols]

Reference Signs List 10 semi-insulating GaAs substrate 11 i-GaAs buffer layer 12 p-GaAs layer 13 i-GaAs channel layer 14 n-AlGaAs electron supply layer 15 n-GaAs channel layer 16 i-AlGaAs barrier layer 20 gate electrode 30 i-GaAs selection Growth layer 31 n ⁺ -GaAs selective growth layer 40 ohmic metal electrode 50 SiO ₂ film

Claims (5)

(57) [Claims] 1. A field effect transistor using a group III-V compound semiconductor, which has a structure in which a gate electrode is formed in an n-type conduction type channel and only a lower portion of an n-type semiconductor layer including a gate electrode portion is provided. It is formed of a p-type conductivity type semiconductor layer, a lead electrode is provided in one part thereof, and the source and drain portions are formed of a high resistance semiconductor layer below the channel, and a portion connected to the channel is formed of an n ⁺ semiconductor layer. A field-effect transistor formed and provided with an ohmic electrode on an n ⁺ semiconductor layer. 2. A field effect transistor according to claim 1, wherein the n-type conductivity type channel field effect transistor, characterized in that it is formed by the heterojunction of two semiconductor layers having different electron affinities. 3. The field effect transistor of claim 1, wherein the feature source, n ⁺ -type semiconductor layer drain region, that are formed in a large semiconductor layer electron affinity than the semiconductor layer forming the channel Field effect transistor. 4. A method of manufacturing a field-effect transistor using a III-V compound semiconductor, comprising: growing a p-type semiconductor layer on a semi-insulating substrate;
The n-type semiconductor layer are sequentially grown consisting, gate on the channel layer
Use after forming a gate electrode serving as the bets, leaving the gate portion, the other portion is removed by etching including the p-type semiconductor layer, then the metal organic vapor phase epitaxy or metal organic molecular beam Epichikisharu method by gastric selective growth, or
Not grow high-resistance semiconductor layer to the lower end of the channel layer,
Subsequently, a method for manufacturing a field effect transistor, wherein an n ⁺ semiconductor layer is grown to the surface and source and drain regions are selectively formed. 5. The field effect transistor according to claim 4,
In the manufacturing method, the channel layer has a different electron affinity.
Formed by a heterojunction of two semiconductor layers
A method for manufacturing a field-effect transistor.