JP2006093731A - Compound semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor device with high threshold voltage and large gain, used for a power amplifier, etc. of a mobile communication terminal. <P>SOLUTION: This device comprises: a semi-insulating GaAs substrate 10; a buffer layer 12 formed on the semi-insulating GaAs substrate 10; an electron running layer 14 which is an InGaAs layer formed on the buffer layer 12; a relaxing layer 16 which is an AlGaInAs layer having a thin thickness about 10 nm formed on the electron running layer 14; and a barrier layer 18 which is an AlGaAs layer formed on the relaxing layer 16, has a thin thickness about 20 nm, and also has a composition ratio of Al larger than that of the relaxing layer 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a compound semiconductor device used for a power amplifier of a mobile communication terminal.

  In a mobile communication terminal such as a cellular phone, a MESFET using GaAs capable of high-speed operation is used as a power amplifier component of a transmitter.

  However, in the conventional MESFET, the threshold voltage is lower than 0V, and even when the gate voltage is 0V, the drain current is not completely turned off, and a slight drain leakage current of about several tens of μA flows. Even a slight drain leakage current may shorten the battery life in a mobile phone or the like that has a long waiting time (standby time) without communication.

  In order to eliminate the drain leakage current of the MESFET, a large negative voltage may be applied to the gate electrode. For this purpose, a battery for generating a negative voltage is required separately. However, mounting a plurality of batteries causes an increase in volume and cost, which is not desirable due to the characteristics of the mobile communication terminal.

  Although it is conceivable to use a DC / DC converter that generates a negative voltage without separately mounting a battery for generating a negative voltage, the DC / DC converter consumes more current than the drain leakage current. This is not desirable.

  Therefore, a method has been proposed in which a drain transistor is cut off by inserting a switch transistor operating at a positive voltage into the drain terminal of the MESFET.

  However, when the switch transistor operates and a current flows between the collector and the emitter, a voltage drop occurs between the collector and the emitter, and the voltage drop increases as the flowing current increases. For this reason, the voltage applied to the drain electrode of MESFET will fall. Here, in order to maintain the same output power as before, it is necessary to compensate by increasing the current. Furthermore, the power supply voltage is being lowered in order to reduce the power consumption of the mobile communication terminal, and the voltage drop of the switch transistor becomes even more problematic.

  Therefore, a compound semiconductor device that does not require insertion of a switch transistor has been proposed.

  The proposed compound semiconductor device will be described with reference to FIG. FIG. 5 is a sectional view showing a proposed compound semiconductor device.

  In the proposed compound semiconductor device, the use of a thin barrier layer facilitates the influence of the gate voltage on the electron transit layer, and the threshold voltage is set higher than 0V.

A buffer layer 212 made of GaAs with a thickness of 600 nm is formed on the semi-insulating GaAs substrate 210, and an electron transit layer 214 made of In _0.2 Ga _0.8 As with a thickness of 14 nm is formed on the buffer layer 212. ing.

On the electron transit layer 214, a barrier layer 218 made of Al _0.75 Ga _0.25 As is formed with a thickness of 20 nm. Since the gate leakage current tends to increase when the thickness of the barrier layer 218 is reduced, an increase in the gate leakage current is prevented by using a material having a large Al composition ratio.

  On the barrier layer 218, a GaAs layer 220 is formed to realize a good contact with each electrode with a thickness of 30 nm.

  A gate electrode 222 is provided on the GaAs layer 220, and a source electrode 224 and a drain electrode 226 are formed on both sides of the gate electrode 222.

  Under the source electrode 224 and the drain electrode 226, ohmic regions 228 and 230 into which n-type impurities are implanted at a high concentration are formed so as to reach the semi-insulating GaAs substrate 210.

  Further, in order to prevent the electric field from concentrating between the ohmic regions 228 and 230 and the region where no impurity is implanted, an LDD (Lightly Doped Drain) region reaching the semi-insulating GaAs substrate in a region other than under the gate electrode. 232 and 234 are formed, respectively.

  Thus, in the proposed compound semiconductor device, the threshold voltage can be made higher than 0 V by using the barrier layer 218 having a large Al composition ratio and a small thickness. The drain current can be turned off without application to the gate electrode.

  However, in the proposed compound semiconductor device, since the barrier layer 218 having a high Al composition ratio is formed on the electron transit layer 214 that does not contain Al, the interface between the electron transit layer 214 and the barrier layer 218 is formed. The bonding state was very bad, and there were many crystal defects in the barrier layer 218. For this reason, since the gain is small and the reliability is low, it cannot be put into practical use.

  An object of the present invention is to provide a compound semiconductor device having a high threshold voltage and a large gain.

  The object is to form a semi-insulating GaAs substrate, a buffer layer formed on the semi-insulating GaAs substrate, an electron transit layer formed on the buffer layer and being an InGaAs layer, and an electron transit layer. A relaxation layer that is an AlGaInAs layer having a thickness as thin as about 10 nm, and a barrier layer that is formed on the relaxation layer and is as thin as about 20 nm and having an Al composition ratio larger than that of the relaxation layer. It is achieved by a compound semiconductor device characterized by having Thereby, crystal defects in the barrier layer can be reduced, and a compound semiconductor device having a large gain can be provided. Further, since the barrier layer and the relaxation layer are very thin, it is possible to provide a compound semiconductor device in which the gate voltage is sufficiently affected by the electron transit layer and the threshold voltage is higher than 0V.

  Also, the object is to provide a semi-insulating InP substrate, a buffer layer formed on the semi-insulating InP substrate, an electron transit layer formed on the buffer layer and being an InGaAs layer, and the electron transit layer. And a barrier layer formed on the relaxation layer and having a thickness of about 40 nm and a composition ratio of Al larger than that of the relaxation layer. It is achieved by a compound semiconductor device characterized by having a layer. Thereby, crystal defects in the barrier layer can be reduced, and a compound semiconductor device having a large gain can be provided. Further, since the barrier layer and the relaxation layer are very thin, it is possible to provide a compound semiconductor device in which the gate voltage is sufficiently affected by the electron transit layer and the threshold voltage is higher than 0V.

  In the above compound semiconductor device, it is desirable that the barrier layer is not doped with impurities.

In the above compound semiconductor device, the barrier layer is preferably doped with a p-type impurity, and the impurity concentration is preferably 1 × 10 ¹⁹ cm ⁻³ or less.

  In the above compound semiconductor device, it is desirable that the electron transit layer has an In composition ratio z that increases toward the relaxation layer.

In the above compound semiconductor device, the electron transit layer is preferably doped with an n-type impurity, and the impurity concentration is preferably 1 × 10 ¹⁸ cm ⁻³ or less.

  As described above, according to the present invention, the relaxation layer having a small Al composition ratio is formed on the electron transit layer, and the barrier layer having a large Al composition ratio is formed on the relaxation layer. It is possible to provide a compound semiconductor device that can be reduced and have a large gain. In addition, since the barrier layer is made of a material containing a large amount of Al, the thickness of the barrier layer can be made very thin, and the thickness of the relaxation layer is also very thin, so that the influence of the gate voltage is sufficient for the electron transit layer. A compound semiconductor device having a threshold voltage higher than 0 V can be provided.

[First Embodiment]
A compound semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of the compound semiconductor device according to the present embodiment. FIG. 2 is a graph showing the gain characteristics of the compound semiconductor device according to the present embodiment. FIG. 3 is a graph showing the gate voltage-gate leakage current characteristics.

  In the compound semiconductor device according to the first embodiment of the present invention, a relaxation layer with a reduced Al composition ratio is formed between the electron transit layer and the barrier layer in order to reduce the occurrence of crystal defects in the barrier layer. It is characterized by that.

A buffer layer 12 made of GaAs having a thickness of 600 nm is formed on a semi-insulating GaAs substrate 10 having a plane orientation (100), an offset angle of 2.5 °, and a diameter of 3 inches. On the buffer layer 12, an electron transit layer 14 made of In _z Ga _1-z As having a thickness of 14 nm and an In composition ratio z of 0.2 is formed. The electron transit layer 14 is not doped with impurities. Further, the In composition ratio z of the electron transit layer 14 may be in the range of more than 0.1 and 0.5 or less.

On the electron transit layer 14, a relaxation layer 16 made of (Al _x Ga _1-x ) _y In _1-y As having a thickness of 5 nm, an Al composition ratio x of 0.25, and a composition ratio y of 0.95 is formed. Is formed. Since the relaxation layer 16 has a small Al composition ratio, the interface between the electron transit layer 14 and the relaxation layer 16 can be formed in a good state. The Al composition ratio x of the relaxation layer 16 may be in the range of 0.1 to 0.5 and the composition ratio y in the range of 0.9 to 1.0. Moreover, the thickness of the relaxation layer 16 should just be the range of 10 nm or less.

A barrier layer 18 made of Al _x Ga _1-x As having a thickness of 15 nm and an Al composition ratio x of 0.75 is formed on the relaxing layer 16. Since the gate leakage current tends to increase when the thickness of the barrier layer 18 is reduced, the increase in the gate leakage current is prevented by using a material having a large Al composition ratio. In addition, since the relaxation layer 16 to which Al is slightly added is formed under the barrier layer 18, the bonding with the barrier layer 18 to which Al is added becomes good, and crystal defects in the barrier layer 18 can be reduced. it can. The barrier layer 18 is not doped with impurities, and the non-doping level is desirably 5 × 10 ¹⁷ cm ⁻³ or less. Further, the Al composition ratio x of the barrier layer 18 may be in the range of 0.4 to 0.8. Further, the thickness of the barrier layer 18 may be in the range of 20 nm or less.

The electron transit layer 14, the relaxation layer 16, and the barrier layer 18 are grown by a MOVPE (Metal Organic Vapor Phase Growth Growth System) method. The growth furnace is a reduced pressure horizontal furnace, the growth pressure is 76 Torr, and the substrate temperature is 660 ° C. As the raw material of the group III element, TMG (Trimethylgallium) or TEG (Triethylgallium) is used as the Ga raw material, TMAL (Trimethylalluminum) is used as the Al raw material, and TMI (Trimethyllinium) is used as the In raw material. In addition, AsH ₃ is used as the source of the group V element.

  On the barrier layer 18, a GaAs layer 20 having a thickness of 30 nm and a good contact with each electrode is formed.

  A gate electrode 22 having a gate length of 0.5 μm is formed on the GaAs layer 20, and a source electrode 24 and a drain electrode 26 are formed on both sides of the gate electrode 22. In the regions below the source electrode 24 and the drain electrode 26, ohmic regions 28 and 30 into which n-type impurities are implanted at a high concentration are formed so as to reach the semi-insulating GaAs substrate 10.

  Further, in order to prevent the electric field from concentrating between the ohmic regions 28 and 30 and the region where no impurity is implanted, the LDD regions 32 and 34 reaching the semi-insulating GaAs substrate 10 in a region other than under the gate electrode 22. Are formed respectively.

  Next, the characteristics of the compound semiconductor device according to the present embodiment will be explained.

  FIG. 2 is a graph showing the gate voltage on the horizontal axis and the output power on the vertical axis. A solid line indicates the gain characteristic of the compound semiconductor device according to the present embodiment, and a broken line indicates the gain characteristic of the proposed compound semiconductor device. As shown in FIG. 2, the gain of the compound semiconductor device according to the present embodiment is much larger than the gain of the proposed compound semiconductor device.

Further, when the graph shows the relationship between the drain current and the gate voltage, with the horizontal axis representing the gate voltage and the vertical axis representing the square root of the drain current, there is a region that is substantially linear. This slope is referred to as a k value, and the gain increases as the k value increases. When the drain voltage is 0.1 V, the k value of the proposed compound semiconductor device is 320 mA / V ² / mm, whereas the k value of the compound semiconductor device according to the present embodiment is 450 mA / V ² / mm. And the gain is greatly improved.

  FIG. 3 is a graph showing the gate voltage on the horizontal axis and the gate leakage current on the vertical axis. A solid line indicates the gate leakage current characteristic of the compound semiconductor device according to the present embodiment, and a broken line indicates the gate leakage current characteristic of the proposed compound semiconductor device. The gate leakage current characteristic of the compound semiconductor device according to the present embodiment is almost the same as the gate leakage current characteristic of the proposed compound semiconductor device, which shows good characteristics.

  In addition, the source resistivity of the compound semiconductor device according to the present embodiment is 1.3 Ω · mm, and the source resistivity of the proposed compound semiconductor device is 2 Ω · mm, which is much higher than that of the proposed compound semiconductor device. Smaller and improved.

  Further, the gate breakdown voltage of the compound semiconductor device according to the present embodiment is 1.36 V, which is almost the same as the gate breakdown voltage of 1.39 V of the proposed compound semiconductor device, and exhibits good characteristics.

  As described above, in this embodiment, the relaxation layer 16 having a small Al composition ratio x is formed on the electron transit layer 14, and the barrier layer 18 having a large Al composition ratio is formed on the relaxation layer 16. The crystal defects can be reduced, and the gain can be increased as shown in FIG. Further, since the barrier layer 18 is made of a material containing a large amount of Al, the thickness of the barrier layer 18 can be made very thin, and the thickness of the relaxation layer 16 is also very thin. 14 and the threshold voltage can be made higher than 0V.

[Second Embodiment]
A compound semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view of the compound semiconductor device according to the present embodiment.

  The compound semiconductor device according to the second embodiment of the present invention is characterized in that the material is different from that of the compound semiconductor device according to the first embodiment.

A buffer layer 112 made of InP and having a thickness of 600 nm is formed on a semi-insulating InP substrate 110. An electron transit layer 114 made of In _z Ga _1-z As having a thickness of 20 nm and an In composition ratio z of 0.45 is formed on the buffer layer 112. Note that the electron transit layer 114 is not doped with impurities. The In composition ratio z of the electron transit layer 114 may be in the range of 0.3 to 0.7.

A relaxation layer 116 made of (Al _x Ga _1-x ) _y In _1-y As having a thickness of 5 nm, an Al composition ratio x of 0.3, and a composition ratio y of 0.5 is formed on the electron transit layer 114. Is formed. Since the relaxation layer 116 has a small Al composition ratio, the interface between the electron transit layer 114 and the relaxation layer 116 can be formed in a good state. The Al composition ratio x of the relaxation layer 116 may be in the range of 0.1 to 0.35, and the composition ratio y may be in the range of 0.3 to 0.7. The thickness of the relaxing layer 116 may be in the range of 10 nm or less.

A barrier layer 118 made of Al _x In _1-x As having a thickness of 30 nm and an Al composition ratio x of 0.7 is formed on the relaxing layer 116. Since the gate leakage current tends to increase when the thickness of the barrier layer 118 is reduced, the increase in the gate leakage current is prevented by using a material having a large Al composition ratio. In addition, since the relaxation layer 16 to which Al is slightly added is formed under the barrier layer 18, the bonding with the barrier layer 118 to which Al is added becomes good, and crystal defects in the barrier layer 118 can be reduced. it can. Note that the barrier layer 118 is not doped with impurities, and the non-doping level is desirably 5 × 10 ¹⁷ cm ⁻³ or less. Further, the Al composition ratio x of the barrier layer 118 may be in the range of 0.3 to 0.7. Further, the thickness of the barrier layer 118 may be in the range of 40 nm or less.

The electron transit layer 114, the relaxation layer 116, and the barrier layer 118 are grown by the MOVPE method. The growth furnace is a reduced pressure horizontal furnace, the growth pressure is 76 Torr, and the substrate temperature is 660 ° C. As the Group III element material, TMG is used as a Ga material, TMAL as a TEG, Al material, and TMI as an In material. In addition, AsH ₃ is used as the source of the group V element.

  On the barrier layer 118, an InP layer 120 is formed to achieve a good contact with each electrode with a thickness of 25 nm.

  A gate electrode 122 having a gate length of 0.5 μm is formed on the InP layer 120, and a source electrode 124 and a drain electrode 126 are formed on both sides of the gate electrode 122. Under the source electrode 124 and the drain electrode 126, ohmic regions 128 and 130 into which n-type impurities are implanted at a high concentration are formed so as to reach the semi-insulating InP substrate 110.

  Further, in order to prevent the electric field from concentrating between the ohmic regions 128 and 130 and the region where no impurity is implanted, the LDD regions 132 and 134 reaching the semi-insulating InP substrate 110 in a region other than under the gate electrode 122. Are formed respectively.

  The characteristics of the compound semiconductor device according to the present embodiment are the same as those of the compound semiconductor device according to the first embodiment.

  As described above, in this embodiment, the relaxation layer 116 having a small Al composition ratio is formed on the electron transit layer 114 and the barrier layer 118 having a large Al composition ratio is formed on the relaxation layer 116. Crystal defects can be reduced and gain can be increased. In addition, since the barrier layer 118 is made of a material containing a large amount of Al, the thickness of the barrier layer 118 can be made very thin, and the thickness of the relaxation layer 116 is also very thin. The threshold voltage can be made higher than 0V.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

For example, in the first or second embodiment, a p-type impurity may be added to the barrier layer to increase the gate breakdown voltage. The impurity concentration may be in the range of 1 × 10 ¹⁹ cm ⁻³ .

  In the first or second embodiment, the In composition ratio z of the electron transit layer may be increased toward the relaxation layer. When a thick electron transit layer having a large In composition ratio z is formed on the buffer layer, distortion occurs. However, if the In composition ratio z is reduced near the interface with the buffer layer and the In composition ratio z is increased toward the relaxation layer, the strain can be reduced. If the In composition ratio z is increased, a large drain current can flow. In the case where the In composition ratio z of the electron transit layer is greatly increased toward the relaxation layer, the In composition ratio z is in the range of greater than 0.1 and less than or equal to 0.5 in the first embodiment. Is desirable. In the second embodiment, the In composition ratio z is preferably in the range of 0.3 to 0.7.

In the first or second embodiment, an n-type impurity may be added to the electron transit layer so that a large drain current flows. The impurity concentration may be in the range of 1 × 10 ¹⁸ cm ⁻³ or less.

It is sectional drawing which shows the compound semiconductor device by 1st Embodiment of this invention. It is a graph which shows the gain characteristic of the compound semiconductor device by 1st Embodiment of this invention. 4 is a graph showing gate voltage-gate leakage current characteristics of the compound semiconductor device according to the first embodiment of the present invention. It is sectional drawing which shows the compound semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the compound semiconductor device proposed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semi-insulating GaAs substrate 12 ... Buffer layer 14 ... Electron transit layer 16 ... Relaxation layer 18 ... Barrier layer 20 ... GaAs layer 22 ... Gate electrode 24 ... Source electrode 26 ... Drain electrode 28, 30 ... Ohmic region 32, 34 ... LDD region 110 ... semi-insulating InP substrate 112 ... buffer layer 114 ... electron transit layer 116 ... relaxation layer 118 ... barrier layer 120 ... InP layer 122 ... gate electrode 124 ... source electrode 126 ... drain electrodes 128, 130 ... ohmic region 132, 134 ... LDD region 210 ... semi-insulating GaAs substrate 212 ... buffer layer 214 ... electron transit layer 218 ... barrier layer 220 ... GaAs layer 222 ... gate electrode 224 ... source electrode 226 ... drain electrodes 228, 230 ... ohmic regions 232, 234 ... LDD region

Claims (6)

A semi-insulating GaAs substrate;
A buffer layer formed on the semi-insulating GaAs substrate;
An electron transit layer formed on the buffer layer and being an InGaAs layer;
A relaxation layer formed on the electron transit layer and being an AlGaInAs layer having a thickness as thin as about 10 nm;
A compound semiconductor device comprising: a barrier layer formed on the relaxation layer, having a thickness as thin as about 20 nm, and an AlGaAs layer having an Al composition ratio larger than that of the relaxation layer. A semi-insulating InP substrate;
A buffer layer formed on the semi-insulating InP substrate;
An electron transit layer formed on the buffer layer and being an InGaAs layer;
A relaxation layer formed on the electron transit layer and being an AlGaInAs layer having a thickness as thin as about 10 nm;
A compound semiconductor device comprising: a barrier layer formed on the relaxation layer, having a thickness as thin as about 40 nm, and an AlInAs layer having an Al composition ratio larger than that of the relaxation layer. The compound semiconductor device according to claim 1 or 2,
The compound semiconductor device, wherein the barrier layer is not doped with impurities. The compound semiconductor device according to claim 1 or 2,
The compound semiconductor device, wherein the barrier layer is doped with p-type impurities and has an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or less. The compound semiconductor device according to claim 1 or 2,
The compound semiconductor device, wherein the electron transit layer has an In composition ratio z that increases toward the relaxation layer. The compound semiconductor device according to claim 1 or 2,
The compound semiconductor device, wherein an n-type impurity is added to the electron transit layer, and an impurity concentration is 1 × 10 ¹⁸ cm ⁻³ or less.

Images