JP2004022818A - Double heterojunction bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a double heterojunction bipolar transistor which is small in the transient build-up voltage of a collector current, wherein the power efficiency when it is used, for example, for a high-frequency power amplifier, can be improved. <P>SOLUTION: There are provided a first semiconductor layer (11), which is formed on a semiconductor substrate and contains a first conductivity-type impurity of high concentration as a sub-collector, a second semiconductor layer (12), which is formed on the first semiconductor layer, and contains a first conductivity-type impurity of low concentration as a collector, a third semiconductor layer (13) which is formed on the second semiconductor layer, a fourth semiconductor layer (14) which is formed on the third semiconductor layer, and contains a second conductivity-type impurity of high concentration as a base, and a fifth semiconductor layer (15) which is formed on the fourth semiconductor layer, contains the first conductivity-type impurity as an emitter, and has forbidden band width larger than that of the fourth semiconductor layer. The third semiconductor layer has forbidden band width larger than that of the fourth semiconductor layer and spontaneous polarization. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The invention particularly relates to double heterojunction bipolar transistors.
[0002]
[Prior art]
Generally, a mobile phone or a portable information terminal requires a power amplifier for transmitting a high frequency in a frequency range of 1 GHz or more. An important characteristic of the transistor used in the power amplifier is power use efficiency. First, since it is advantageous that the input high-frequency power is small in order to obtain a desired high-frequency output, a transistor having excellent high-frequency characteristics is required. Second, it is necessary to have a characteristic of efficiently converting DC power supplied from a battery to high-frequency power. For this reason, there is a demand for a transistor that has a characteristic in which the series resistance of the element is small while securing a desired breakdown voltage.
[0003]
A heterojunction bipolar transistor (hereinafter abbreviated as HBT) formed on a III-V compound semiconductor substrate such as GaAs has excellent high-frequency characteristics due to the material properties of high electron mobility and operates with a single positive power supply. It has any of the possible characteristics and is increasingly used in mobile terminals such as mobile phones. However, there is still a problem from the viewpoint of efficiently converting DC power supplied from a battery to high-frequency power.
[0004]
FIG. 8 shows typical IV characteristics of an HBT using InGaP for the emitter and GaAs for the base and the collector. The collector current IC, the collector - emitter voltage _{V CE} is not rise from zero, it rises from the voltage Voffset, which commonly called collector offset voltage. This collector offset voltage Voffset is typically about 0.3 V for InGaP / GaAs-HBT. When a load is connected to the collector of a transistor having such characteristics and a high frequency is input to the base to obtain high frequency power, the operating point of the HBT transistor every moment moves on the load line L in FIG. . Therefore, the maximum voltage amplitude Vp at which the waveform of the high-frequency power obtained from the characteristics of FIG. 8 can be linearly amplified without distortion is Vp = (Vcc-Vk)
It is. Here, Vcc is the power supply voltage, and Vk is the minimum voltage at which the load line L intersects the operating region of the HBT. Therefore, for example, the collector efficiency when this transistor is biased to class B is
ηc = (Vcc−Vk) / Vcc * π / 4
It becomes. The voltage Vk is the sum of the offset voltage Voffset and the voltage drop due to the series resistance. In the example of FIG. 8, the voltage drop due to the series resistance is about 0.2 V and Vk is 0.5 V. Therefore, when it is assumed that the power is supplied directly to the Li-ion battery and the voltage is 3.6 V, the collector efficiency is 68%. If the offset voltage can be reduced to zero, the efficiency is 75%. Therefore, the efficiency is expected to decrease by about 7% due to the presence of the offset voltage.
[0005]
Furthermore, in recent mobile phones, a method of adjusting the transmission power of a mobile terminal according to the distance to a base station, such as a CDMA method, is adopted. In the adjustment of the transmission power, a system in which the supply voltage to the collector is made variable by using a DC-DC converter or the like has a high power use efficiency and is increasingly used. For example, assuming that the supply voltage is reduced to 1.2 V, the efficiency in the absence of an offset voltage is 68%, but the presence of the offset voltage deteriorates the efficiency by 46% to 19%. For this reason, it is an important subject to reduce the offset voltage of the HBT, particularly in application to a transmission amplifier of a mobile terminal in which a power supply voltage is variable.
[0006]
In order to solve such a problem, application of a double heterojunction bipolar transistor (hereinafter abbreviated as DHBT) has been attempted. The offset voltage is caused by the asymmetry of the EB (emitter, base) junction and the BC (base, collector) junction. Specifically, since the ON voltage of the BC junction is lower than the ON voltage of the EB junction, the transistor enters a saturation region when VCE becomes substantially equal to the difference between the ON voltages. The DHBT is based on the idea of introducing a heterojunction into the BC junction to reduce the asymmetry between the EB junction and the BC junction to reduce the offset voltage. In the HBT, since the doping concentration of the base is much higher than the doping concentration of the collector, the current flowing through the BC junction is mainly a hole current. Therefore, if a hole current crossing the BC junction can be controlled by the heterojunction introduced into the BC junction to make the ON voltage of the BC junction almost equal to that of the EB junction, the offset voltage can be reduced, and the knee voltage (Vk) can be reduced. .
[0007]
However, focusing on the electron current crossing the BC junction, a problem specific to DHBT becomes a problem. If the bandgap of the semiconductor forming the collector is made larger than the bandgap of the semiconductor forming the base, a hetero-barrier is formed in the conduction band that prevents an electron current flowing from the emitter to the collector. For this reason, in the DHBT, there are problems that electrons are accumulated in the base and the current gain is significantly reduced, and the upper limit of the collector current is reduced. In order to remove such a current blocking effect, one of the commonly used means is to place a spacer between a heterojunction between BC and a PN junction as disclosed in, for example, JP-A-2001-176881. There is.
[0008]
[Problems to be solved by the invention]
FIG. 9 shows a band diagram of a DHBT having the conventional spacer 53. As shown in FIG. In the structure shown in FIG. 9, electrons injected from the emitter contact layer 56 pass from the wide band gap emitter layer 55 to the narrow band gap base layer 54, pass through the narrow band gap spacer layer 53, and have a wide band gap. It flows to the collector layer 52 and reaches the collector electrode via the sub-collector layer 51.
[0009]
Here, since the apex 57 of the barrier of the conduction band generated at the heterojunction between the BC (base and collector) exists in the strong electric field region of the depletion layer in the collector 52, electrons are obtained by the tunnel effect and this strong electric field. Energy can easily pass through this hetero barrier. However, even with this spacer structure, the knee voltage cannot be effectively reduced yet. That is, when the collector voltage decreases and the electric field intensity of the collector depletion layer decreases, electrons cannot pass through the conduction band barrier generated at the hetero junction between the BCs. In particular, when the current density increases and the electron concentration in the collector depletion layer increases, the electric field intensity near the base-collector junction further decreases, and this obstruction becomes significant.
[0010]
FIG. 10 shows a band diagram of a DHBT having a conventional spacer biased in a saturation region. As shown in FIG. 10, when the apex 57 of the conduction band barrier substantially matches the conduction band edge of the base 54, a significant electron current blocking effect occurs. Normally, in a bipolar transistor, when the electron current increases and the electric field intensity of the collector depletion layer at the BC junction reaches zero, a so-called base pushout phenomenon occurs, and as a result, the current gain and the cutoff frequency decrease. Therefore, the current at which the electric field intensity of the collector depletion layer at the BC junction reaches zero becomes a measure of the upper limit of the operation of the transistor.
[0011]
However, in the DHBT, as shown in FIG. 10, a blocking effect of the electron current occurs before the electric field intensity of the collector depletion layer at the BC junction reaches zero, so that the operating current range is significantly narrowed. It is. Therefore, even if a spacer is used, a DHBT with sufficient performance cannot be obtained, and as a result, there is a problem that an HBT having a low knee voltage cannot be obtained.
[0012]
As described above, the conventional HBT still has a problem from the viewpoint of efficiently converting DC power supplied from a battery to high-frequency power.
[0013]
[Means for Solving the Problems]
The present invention provides a first semiconductor layer containing a high-concentration first conductivity type impurity formed on a semiconductor substrate and serving as a sub-collector, and a low-concentration first semiconductor formed on the first semiconductor layer and serving as a collector. A second semiconductor layer containing an impurity of one conductivity type, a third semiconductor layer formed on the second semiconductor layer, and a high-concentration base formed on the third semiconductor layer and serving as a base; A fourth semiconductor layer containing impurities of the second conductivity type, and a bandgap larger than the fourth semiconductor layer containing impurities of the first conductivity type formed on the fourth semiconductor layer and serving as an emitter and serving as an emitter; A fifth semiconductor layer, wherein the third semiconductor layer has a wider band gap than the fourth semiconductor layer and has spontaneous polarization, and has a configuration of a double heterojunction bipolar transistor.
[0014]
With such a configuration, since the semiconductor layer having a larger band gap than the base and having spontaneous polarization is inserted between the base and the collector, the hole current injected from the base to the collector during operation in the saturation region is reduced. A DHBT having a small offset voltage and a small offset voltage can be obtained, and even under a bias condition in which the electric field strength of the collector layer is small, the stopping power of the electron flow is reduced, so that the DHBT having a large operating current and a low knee voltage is provided. I can do it.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment in which the present invention is applied to an InGaP / GaAs-DHBT formed on a GaAs substrate will be described in detail with reference to the drawings.
[0016]
(1st Embodiment)
As shown in FIG. 1, in the InGaP / GaAs-DHBT of this embodiment, an N ⁺ -type GaAs layer 11 serving as a subcollector is formed on a [100] plane of a semi-insulating GaAs substrate 10 and serves as a collector. An N ⁻ type GaAs layer 12 is formed on the GaAs layer 11, an InGaP layer 13 having spontaneous polarization is formed on the GaAs layer 12, and a P ⁺ type GaAs layer 14 serving as a base is formed on the InGaP layer 13. An N-type InGaP layer 15 serving as an emitter is formed on the GaAs layer 14, an N ⁺ -type GaAs layer 16 serving as a contact buffer is formed on the InGaP layer 15, and an N ⁺ -type InGaAs layer 17 serving as a contact layer is formed. Has a laminated structure formed on the GaAs layer 16.
[0017]
This laminated structure can be formed on the [100] plane of the GaAs substrate 10 by, for example, the MOCVD method. First, an N ⁺ -type GaAs layer 11 serving as a sub-collector layer is deposited to a thickness of 500 nm on the [100] plane of the GaAs substrate 10 at a doping concentration of 5 × 10 ¹⁸ cm ⁻³ , and a doping concentration of 1 × An N ⁻ -type GaAs layer 12 serving as a collector layer is deposited to a thickness of 700 nm at 10 ¹⁶ cm ⁻³ . Next, an N ⁻ -type InGaP layer 13 is grown on the GaAs layer 12 at a doping concentration of 1 × 10 ¹⁶ cm ⁻³ to a thickness of 10 nm. At this time, by setting the growth temperature in the range of 620 ° C. to 670 ° C., the InGaP layer 13 forms a natural superlattice in which InP and GaP are alternately stacked in the <111> direction.
[0018]
Further, a P ⁺ type GaAs layer 14 serving as a base layer is deposited to a thickness of 60 nm on the InGaP layer 13 at a doping concentration of 4 × 10 ¹⁹ cm ⁻³ , and a doping concentration of 5 × 10 ¹⁷ cm ⁻³ is formed thereon. An N-type InGaP layer 15 serving as an emitter layer is deposited to a thickness of 50 nm. On this InGaP layer 15, an N ⁺ type GaAs layer 16 as a contact buffer layer is grown to a thickness of 100 nm as a contact buffer layer at a doping concentration of 5 × 10 ¹⁸ cm ⁻³ , and a contact is formed at a doping concentration of 3 × 10 ¹⁹ cm ⁻³ . An N ⁺ -type InGaAs layer 17 serving as a layer is deposited to a thickness of 100 nm.
[0019]
Finally, the surfaces of the sub-collector layer 11 and the base layer 14 are partially exposed by mesa etching, and a collector electrode 18 and a base electrode 19 are formed on the respective exposed surfaces, and an emitter electrode 20 is formed on the InGaAs layer 17. The DHBT was formed.
[0020]
Here, the In composition ratio of the N ⁻ -type InGaP layer 13 and the N-type InGaP emitter layer 15 is 0.5, and is lattice-matched to the GaAs substrate 10.
[0021]
In the InGaP layer 13 thus formed, spontaneous polarization occurs because In and Ga having different ionization tendencies are regularly arranged alternately. For this reason, as shown in FIG. 2, the positive charge 21 having a surface density of approximately q * 10 ¹² Coulomb / cm ² is present on the collector 12 side of the InGaP layer 13, and the surface density is approximately q * 10 ¹² on the base 14 side. A negative charge 22 of ¹² Coulomb / cm ² is generated. Therefore, at the end face of the InGaP layer 13 on the collector 12 side, a discontinuity of Qs / ε occurs in the electric field strength. Here, Qs is the density of the positive charges 21 generated on the side of the collector 12 of the InGaP layer 13, and ε is the dielectric constant of the InGaP layer 13. Therefore, even if the electron current increases and the electric field intensity of the depletion layer in the collector 12 decreases, the electric field of Qs / ε remains in the InGaP layer 13 even if it becomes zero at the end face of the InGaP layer 13 on the collector 12 side.
[0022]
FIG. 2 shows a band diagram in such a bias state. The band is bent toward the collector 12 side of the InGaP layer 13 by an electric field due to spontaneous polarization of the InGaP layer 13. Since the magnitude of this electric field reaches a magnitude of about 150 kV / cm, the electron current can pass through the hetero barrier by tunnel effect.
[0023]
FIG. 3 shows a band diagram when the collector voltage is lowered so that the band in the collector 12 region becomes flat in the saturation region. Even in this case, an electric field due to spontaneous polarization remains in the InGaP layer 13, so that an electron current can pass therethrough. At this time, the potential difference between both ends of the InGaP layer 13 is calculated as d * Qs / ε, where d is the thickness of the InGaP layer 13, and is 0.15V. That is, the offset voltage is about 0.15 V, which can be reduced to about half that of a normal HBT.
[0024]
Accordingly, the current-voltage characteristics of the DHBT according to the present embodiment are as shown in FIG. FIG. 11 shows, for comparison, the characteristics of a conventional DHBT in which all the collector layers are also InGaP layers. In the characteristic of the conventional DHBT shown in FIG. 11, although the offset voltage is small, the effective knee voltage becomes extremely large due to the current blocking effect, whereas the characteristic of the DHBT of the present embodiment shown in FIG. Is suppressed up to the point where the base push-out occurs, so that a characteristic in which the knee voltage is small is obtained.
[0025]
In order to effectively bring out the effects of this embodiment as shown in FIG. 4, it is necessary to determine the structure according to the following design guidelines. For example, assuming that the offset voltage Voffset is 0.15 V or less, the thickness d of the InGaP layer 13 having spontaneous polarization is d <0.15 * ε / Qs
It becomes. Qs can be varied depending on the growth conditions of the InGaP layer 13, but it is necessary to secure an electric field strength that allows electrons to pass through the barrier. Assuming that the electric field strength is about 50 kV / cm or more, the thickness d of the InGaP layer 13 having spontaneous polarization for which the present embodiment is effective is 30 nm or less.
[0026]
On the other hand, in order to suppress the diffusion of holes from the base 14 to the collector 12 by the InGaP layer 13 having spontaneous polarization, the probability that light holes tunnel through the InGaP layer 13 must be reduced. For this reason, there is a lower limit to the thickness d of the InGaP layer 13, but according to experiments by the inventor, a thickness of 10 nm or more was required. Therefore, it has been found that the thickness d of the InGaP layer 13 having spontaneous polarization is 10 nm or more and 30 nm or less, which is a condition for obtaining a preferable result.
[0027]
According to the present embodiment, the offset voltage Voffset is about 0.15 V, which is about half that of a normal HBT. Therefore, the collector efficiency ηc of the DHBT of the present embodiment when biased to class B is determined by the following equation.
[0028]
ηc = (Vcc−Vk) / Vcc * π / 4
Here, when the power source is Vcc = 3.6 V as a Li-ion battery and Vk = 0.35 V with the potential drop due to the series resistance being 0.2 V, ηc = 71%, which is 5% lower than the conventional collector efficiency of 66%. Efficiency increases. Further, if the collector supply voltage is reduced to 1.2 V (Vcc = 1.2 V), ηc = 56%, and an increase in efficiency of 10% from the conventional collector efficiency of 46% is expected.
[0029]
As described above, according to the present embodiment, the difference from the conventional collector efficiency is more remarkable when the collector supply voltage is lower. In recent years, in a system in which the supply voltage to the collector is variable according to the distance from the base station, such as a CDMA system in a mobile phone, the use efficiency is high and promising in consideration of application to a transmission amplifier of a mobile terminal. It is. In particular, the effect of the present embodiment is very large, for example, the continuous talk time of the mobile phone can be greatly extended.
[0030]
As described above, according to the present embodiment, it is possible to obtain a double heterojunction bipolar transistor capable of performing high-efficiency power amplification with a low knee voltage and improving the power efficiency of a mobile terminal as compared with the related art.
[0031]
(Second embodiment)
It is also possible to apply the present invention in combination with DHBT by the spacer method. FIG. 5 shows the configuration of the DHBT according to such an embodiment. The configuration of the DHBT according to the second embodiment is almost the same as the configuration of the DHBT according to the first embodiment shown in FIG. 1 except that a spacer layer and a spacer layer are formed on the N ⁻ -type InGaP layer 13. The point is that an N ⁺ -type GaAs layer 30 is grown, and a P ⁺ -type GaAs layer 14 serving as a base is stacked thereon. The other configurations are the same, and the same reference numerals are given and duplicate explanations are omitted.
[0032]
The N ⁺ -type GaAs layer 30 serving as a spacer layer formed in the DHBT of the second embodiment is formed by MOCVD at a doping concentration of 2 × 10 ¹⁸ cm ⁻³ and the N ⁺ -type GaAs layer 30. Is performed by growing it to a thickness of 5 nm. All other semiconductor layers are the same as in FIG.
[0033]
In the second embodiment, as described above, the spacer layer 30 is doped with a donor in order to compensate for the negative charge on the end face of the spontaneously polarized InGaP layer 13 on the base 14 side and prevent the hetero barrier from lifting. It is preferable to introduce a positive fixed charge. It is desirable that the doping amount is such that the integral value of the donor in the spacer 30 is substantially equal to the negative charge amount of the spontaneously polarized InGaP layer 13.
[0034]
As in the first embodiment, spontaneous polarization occurs in the InGaP layer 13 because In and Ga having different ionization tendencies are regularly arranged alternately. For this reason, according to the present embodiment, in addition to the effects of the first embodiment, the electric field strength of the InGaP layer 13 is such that the electron current does not pass even under a bias condition in which the electric field strength of the depletion layer in the collector 12 decreases. , And a double heterojunction bipolar transistor having a characteristic of a small offset voltage and a low knee voltage can be obtained. That is, as is clear from the comparison between the band diagram of FIG. 3 and the band diagram of FIG. 6, it can be seen that an electric field is generated between the base layer 14 and the spontaneous polarization layer 13 in FIG.
(Third embodiment)
As shown in FIG. 7, in the structure of the first embodiment, the N ⁻ -type GaAs layer 12 serving as the collector layer is replaced with a disordered InGaP layer 40 containing no natural superlattice. The configuration of each of the remaining semiconductor layers is the same as that of FIG. 1, and the same reference numerals are given and the description thereof will be omitted.
[0035]
The disordered InGaP layer 40 containing no natural superlattice shown in FIG. 7 does not cause spontaneous polarization. Therefore, when an InGaP thin film 13 containing a natural superlattice and having spontaneous polarization is grown thereon, positive fixed charges are generated at the interface. Therefore, the effect similar to that of the first embodiment eliminates the blocking effect of the electron current, and a transistor characteristic with a small offset voltage and a low knee voltage can be obtained. In particular, in the third embodiment, since the collector depletion layer is formed in the InGaP layer 40 having a larger band gap than the GaAs layer 12, in addition to the effects of the first embodiment, the collector has a higher withstand voltage. Is obtained.
[0036]
(Other embodiments)
In each of the above embodiments, the present invention is applied to an InGaP / GaAs double heterojunction bipolar transistor. However, the present invention can be similarly implemented using other semiconductor materials capable of obtaining spontaneous polarization. For example, since a strong spontaneous polarization occurs in the AlGaN layer grown on the GaN substrate, it is possible to manufacture a DHBT according to the gist of the present invention.
[0037]
【The invention's effect】
As described above in detail, according to the present invention, since the semiconductor layer having a larger band gap than the base is inserted between the collector and the collector, the hole current injected from the base to the collector during the saturation operation is reduced. And a DHBT with a small offset voltage can be obtained. Further, since the semiconductor layer having a larger band gap than the base has spontaneous polarization, even under a bias condition in which the electric field strength of the collector is reduced, the ability of stopping the electron flow is reduced. And a DHBT with a low knee voltage can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a DHBT according to a first embodiment of the present invention.
FIG. 2 is a band diagram of the first embodiment of the present invention.
FIG. 3 is a band diagram of the first embodiment of the present invention biased to a saturation region.
FIG. 4 is a DHBT current-voltage characteristic diagram according to the first embodiment of the present invention.
FIG. 5 is a schematic sectional view of a DHBT according to a second embodiment of the present invention.
FIG. 6 is a band diagram of a second embodiment of the present invention, biased in the saturation region.
FIG. 7 is a schematic sectional view of a DHBT according to a third embodiment of the present invention.
FIG. 8 is a current-voltage characteristic diagram of a conventional single heterojunction bipolar transistor.
FIG. 9 is a band diagram of a DHBT having a narrow band gap spacer layer at a conventional base-collector junction biased in the active region.
FIG. 10 is a band diagram of a DHBT having a narrow band gap spacer layer at a conventional base-collector junction biased in the saturation region.
FIG. 11 is a current-voltage characteristic diagram of a conventional DHBT.
[Explanation of symbols]
InGaP layer 14 ... ^{P +} -type GaAs base layer 15 having a type GaAs collector layer 13 ... spontaneous polarization ^- Voffset ... offset voltage L ... load line Vk ... knee voltage 10 ... GaAs substrate 11 ... ^{N +} -type GaAs sub-collector layer 12 ... N ... N-type InGaP emitter layer 16 ... N ⁺ type GaAs contact buffer layer 17 ... N ⁺ type InGaAs contact layer 18 ... collector electrode 19 ... base electrode 20 ... emitter electrode 21 ... positive fixed surface charge 22 generated by spontaneous polarization 22 ... spontaneous Negative fixed surface charge generated by polarization 30... Narrow band gap spacer layer 40.

Claims (9)

A first semiconductor layer formed on a semiconductor substrate and including a high-concentration impurity of a first conductivity type serving as a subcollector;
A second semiconductor layer containing a low-concentration impurity of the first conductivity type formed on the first semiconductor layer and serving as a collector;
A third semiconductor layer formed on the second semiconductor layer;
A fourth semiconductor layer formed on the third semiconductor layer and containing a high-concentration impurity of the second conductivity type serving as a base;
A fifth semiconductor layer formed on the fourth semiconductor layer and containing an impurity of the first conductivity type serving as an emitter and having a larger bandgap than the fourth semiconductor layer;
A double heterojunction bipolar transistor, wherein the third semiconductor layer has a larger band gap than the fourth semiconductor layer and has spontaneous polarization. The double heterojunction according to claim 1, wherein the first, second, and fifth semiconductor layers are N-type semiconductor layers, respectively, and the fourth semiconductor layer is a P-type semiconductor layer. Bipolar transistor. The double heterojunction according to claim 2, wherein an electric field generated by the spontaneous polarization in the third semiconductor layer travels from the second semiconductor layer serving as the collector to the fourth semiconductor layer serving as a base. Bipolar transistor. 3. The semiconductor device according to claim 2, wherein the fourth semiconductor layer is formed of P-type GaAs, and the third semiconductor layer is formed of InGaP including a natural superlattice of InP and GaP. Double heterojunction bipolar transistor. 3. The double heterojunction bipolar transistor according to claim 2, wherein the thickness of the third semiconductor layer is 10 nm or more and 30 nm or less. The fourth semiconductor layer is formed of P-type GaAs, the third semiconductor layer is formed of InGaP including a natural superlattice of InP and GaP, and the fourth semiconductor layer is formed between the fourth and third semiconductor layers. 2. The double heterojunction bipolar transistor according to claim 1, wherein an N-type GaAs spacer layer having a narrower band gap than the fifth semiconductor layer is inserted. 7. The double heterojunction bipolar transistor according to claim 6, wherein the N-type GaAs spacer layer is set so that the integrated value of the donor becomes substantially equal to the amount of the spontaneously polarized negative charge of the third semiconductor layer. . The double heterojunction bipolar transistor according to claim 2 or 6, wherein the second semiconductor layer is formed of disordered InGaP that does not include a natural superlattice. The double heterojunction bipolar transistor according to claim 1, wherein the fourth semiconductor layer is formed of p-type GaN, and the third semiconductor layer is formed of AlGaN.

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