JPH11345812A - Compound semiconductor epitaxial wafer and compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize good transistor performance with a small leakage current by reducing the mobility in carriers injected to in a buffer layer and decreasing the current carried in the buffer layer of an FET. SOLUTION: Shallow donor impurity (Si) and shallow acceptor impurity (C), each with similar density, are implanted with a density of 1×10<16> cm<-3> or above concurrently. These impurities function as ion-based scattering sources for carriers implanted in the buffer layer 2 to reduce mobility in carriers. The function of decreased mobility becomes marked with an impurity density of 1×10<16> cm<-3> or above. Since the mobility in carriers is reduced, high breakdown strength and high gain of an FET can be realized. In addition, a mixed crystal ratio of Al is made 0.2 or larger to increase a band gap, while a leakage current is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a compound semiconductor epitaxial wafer and a compound semiconductor device used for a planar device such as a thin film semiconductor.

[0002]

2. Description of the Related Art Devices using compound semiconductors such as GaAs, that is, compound semiconductor devices, are used in various applications such as optical devices and high-frequency devices. A typical planar type device is a field effect transistor (FE) using GaAs or InGaAs for an active channel layer.
T). A typical example of the planar device is an FET having an LDD (Lightly Dopaed Drain) structure or a recess structure. F having the latter recess structure
FIG. 1 shows a cross section of the ET.

An AlGaAs buffer layer 2 is provided on a semi-insulating substrate 1, and an n-type G layer serving as a channel layer 3 is provided thereon.
It has a layer of aAsInP or InGaAs. Further, there is an n-type GaAs contact layer 4 for reducing the contact resistance of the electrode. These layers are usually manufactured by a molecular beam epitaxial growth method (MBE method), a metal organic chemical vapor deposition method (MOVPE method), or the like.

[0004] In the FET, a drain electrode 7 is connected to a source electrode 5.
Is controlled by applying a signal voltage to the gate electrode 6 to amplify the signal. At this time, it is ideal that the current flows only in the channel layer 3, but actually, the current also flows below the channel layer 3. This leakage current lowers the characteristics of the transistor, particularly, the gain and breakdown voltage. Buffer layer 2
Is provided for the purpose of suppressing this leakage current, and the performance of the buffer layer 2 greatly affects the performance of the transistor.

The most frequently used buffer layer 2 is:
GaAlAs for GaAs-based devices and InAlAs for InP-based devices. These materials have a larger band gap energy than GaAs, InGaAs, InP, or the like serving as a channel, so that an energy barrier is formed between the material and the channel layer 3. By utilizing this barrier, leakage current from the channel layer 3 is suppressed. Of course, the buffer layer 2 must be of a small conductivity. Normally, the concentration of impurities in the material, particularly impurities serving as shallow donors and acceptors, is minimized. For example, it is less than 1 × 10 ¹⁶ cm ⁻³ .

[0006]

SUMMARY OF THE INVENTION However, AlG
In the heterojunction buffer layer using aAs or InAlAs, although the leakage current is considerably suppressed, the leakage current cannot be completely eliminated. FET operating under high electric field
In, not a few carriers are injected into the buffer layer, and if it is an n-type carrier, it flows to the drain electrode,
This becomes a leakage current and flows in the buffer layer.
Suppressing this as much as possible leads to improved performance of the FET.

In order to reduce the injection of carriers into the buffer layer, it is necessary to increase the band gap. To this end, it is effective to increase the mixed crystal ratio of Al in the buffer layer. When the ratio is 0.3 or more, the crystallinity is disturbed, and the crystal of the channel layer grown thereon becomes poor, which also deteriorates the FET characteristics.

Accordingly, an object of the present invention is to solve the above-mentioned problems, to reduce the mobility of carriers injected into the buffer layer, and to reduce the current flowing through the buffer layer, thereby suppressing the leakage current and improving the current. An object of the present invention is to provide a compound semiconductor epitaxial wafer and a compound semiconductor device that can realize transistor performance.

[0009]

In order to achieve the above object, a compound semiconductor epitaxial wafer of the present invention is used for a planar (planar) type device, and is premised on a compound semiconductor epitaxial wafer having a buffer layer below a channel layer. And each is configured as follows.

(1) In the compound semiconductor epitaxial wafer according to claim 1, in the buffer layer, the buffer layer has shallow donor impurities (impurities to become shallow donors) and shallow acceptor impurities (impurities to become shallow acceptors).
At a concentration of 1 × 10 ¹⁶ cm ⁻³ or more at the same time.

Here, the expression that the buffer layer has a compound semiconductor layer means that the buffer layer is composed of a single compound semiconductor layer and that the buffer semiconductor layer is one of a plurality of layers constituting the buffer layer. This is a concept that includes both forms. The interpretation of “having” in the other claims is the same.

The gist of the present invention is that shallow acceptor impurities and donor impurities having close concentrations in the buffer layer are formed.
The ^purpose is to reduce the mobility of carriers injected into the buffer layer by adding 1 × 10 ¹⁶ cm ⁻³ or more, respectively.

When the concentrations of the shallow impurities are close to each other, the shallow impurities have a compensation relationship with each other, and almost all are ionized. These serve as ionic scattering sources of the injected carriers, and lower the mobility of the carriers in the buffer layer. The lowering capability is higher as the impurity concentration is higher, and the leakage current can be reduced. The effect of reducing the mobility of carriers injected into the buffer layer is as follows.
It becomes apparent when the impurity concentration is 1 × 10 ¹⁶ cm ⁻³ or more.

According to the first aspect of the present invention, GaAl
In addition to a semiconductor layer containing Al as a constituent element, such as As or InAlAs, other semiconductor layers such as GaAs, InP, InGaP, etc.
Even a semiconductor layer not containing l as a constituent element can be used as a buffer layer.

(2) In the compound semiconductor epitaxial wafer according to the second aspect, the buffer layer simultaneously contains shallow donor impurities and shallow acceptor impurities each having a concentration close to each other at a concentration of 1 × 10 ¹⁶ cm ⁻³ or more. Further, it has a compound semiconductor layer containing Al having an Al mixed crystal ratio of 0.2 or more. The buffer layer has an Al-containing compound semiconductor layer, and the Al mixed crystal ratio is 0.1.
The difference from claim 1 is that the number is 2 or more.

According to a second aspect of the present invention, the buffer layer is made of GaAs.
This is particularly effective when the semiconductor device has a compound semiconductor layer containing Al as a constituent element, such as lAs or InAlAs.
The reason is that when a donor impurity is added to these materials, a deep level called a DX center is formed, so that the conductivity of the materials is easily lowered.
Further, it has been suggested that even when an acceptor is added, there is a possibility that an AX center having a deep level still exists.

In general, the leakage current can be reduced by increasing the band gap, and the band gap is increased by increasing the Al mixed crystal ratio. That is, the donor ionization energy changes depending on the Al mixed crystal ratio X.
The activation energy starts to increase when X exceeds 0.2.
Reaches V. Therefore, the DX center becomes apparent
This is when the Al mixed crystal ratio X is 0.2 or more.

(3) The compound semiconductor epitaxial wafer according to claim 3, wherein the buffer layer contains shallow donor impurities and shallow acceptor impurities each at 1 × 10 ¹⁶ cm.
^-3 or more at the same time and the AlAs mixed crystal ratio is 0.
It has two or more AlGaAs layers. In that the buffer layer has a specific AlGaAs layer,
It differs from the first and second aspects.

In the case of AlGaAs, the DX center becomes apparent when the AlAs mixed crystal ratio is 0.2 or more. In this case, between the shallow concentration of donors [N _D] and the acceptor concentration concentration [N _A] and DX center [N _DX], if there is the following relationship, the crystal becomes high resistance.

[N _D ] − [N _A ] <[N _DX ] (1) Also, oxygen may be mixed into AlGaAs, which also has a deep level. Therefore, when taking into consideration the incorporation of oxygen, when the concentration _{[N O], [N D} ] - [N A] <[N DX] + [N O] ... (2) and high when it becomes It becomes a crystal of resistance.

[0021] Thus, in the compound semiconductor epitaxial wafer according to claim 3, the difference between the total concentration [N _D] of the shallow donor impurities and the total concentration [N _A] of the shallow acceptor impurities [N _A] - [N _D ] is usually A
It is preferable that the concentration be lower than the concentration of oxygen contained in lGaAs (claim 4).

Similarly, the compound semiconductor epi according to claim 3
In the case of a axial wafer, the above-mentioned shallow acceptor
Total concentration of pure substance [N_A] And the total concentration of said shallow donor impurities
[N _D] And the difference [N_A]-[N_D] Is the absolute value of AlG
DX center formed by the shallow donor impurity in aAs
Is preferably lower than the concentration of
5).

The donor ionization energy is AlA
s Since the mixed crystal ratio X increases from around 0.2,
It is preferable that X = 0.2 or more in order to reduce the leakage current itself.

(4) As the shallow donor impurity, S
i, Se, Ge, Sn, or Te may be included (claim 6), and the shallow acceptor impurity may include any of C, Be, Zn, Mn, or Mg (claim 6). Item 7).

(5) A compound semiconductor device according to the present invention is a compound semiconductor device (planar device) prepared using the compound semiconductor epitaxial wafer according to claim 1, 2, 3, 4, 5, 6, or 7. (Claim 8).

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the compound semiconductor epitaxial wafer of the present invention will be described.

FIG. 1 shows an epitaxial wafer for a GaAs power MESFET. An Al _x Ga _{1 -x} As layer is formed as a buffer layer 2 on a GaAs substrate 1, an n-type GaAs layer is formed thereon as a channel layer 3, and an n-type GaAs layer is formed as a contact layer 4 thereon. is there. Therefore, a multilayer epitaxial wafer having the buffer layer 2 below the channel layer 3 is obtained.

The buffer layer 2 may have at least one Al _x Ga _{1 -x} As layer. Therefore, a structure in which undoped GaAs layers and Al _x Ga _{1 -x} As layers are alternately stacked may be employed. Here, Al _x Ga _1-x As is Ga
Since As has a lattice constant substantially equal to As and has a larger band gap than GaAs, the use of Al _x Ga _{1 -x} As as the buffer layer reduces the leakage current flowing to the substrate side, rather than using GaAs as the buffer layer. Is effective in

Al _x Ga constituting the buffer layer 2
_{The 1-x} As layer contains 1 × 10 ¹⁶ Si as a shallow donor impurity and C as a shallow acceptor impurity.
Contain simultaneously at a concentration of cm ^-3 or more. The Al _x Ga _{1 -x} As layer forming the buffer layer 2 has an Al mixed crystal ratio X in the range of 0.2 or more, and the oxygen concentration contained in the Al _x Ga _{1 -x} As layer is extremely low. is there.

Al _{x G} a constituting this buffer layer 2
_{Since the 1-x} As layer simultaneously contains shallow donor impurities Si and shallow acceptor impurities C at a concentration of 1 × 10 ¹⁶ cm ⁻³ or more, the Al composition ratio of the Al _x Ga _1-x As buffer layer 2 is reduced. Can be reduced to 0.3 or more without deteriorating the frequency characteristics, and the leakage current flowing to the substrate side can be greatly reduced.

In order to confirm the effects of the present invention, an epitaxial wafer for a planar type device shown in FIG. 1 was manufactured by using a semi-insulating GaAs substrate 1 and by a metal organic chemical vapor deposition (MOVPE) method.

The buffer layer 2 has an AlAs mixed crystal ratio of 0.1.
3. AlGaAs having a thickness of 300 nm was used. The channel layer 3 is made of n-type GaAs having a concentration of 3 × 10 ¹⁷ cm ⁻³ .

The buffer layer 2 has a donor impurity of Si
And C as an acceptor impurity were added at the same concentration.
The added concentration is, as shown by plots c and d in FIG.
For both Si and C, two types of wafers were prepared, one with 1 × 10 ¹⁶ cm ⁻³ (point c in FIG. 3) and one with 1 × 10 ¹⁷ cm ⁻³ (point d in FIG. 3). .

On the other hand, as a comparative example, under the same conditions, S
When no additive was added without adding impurities of i and C, that is, when the additive concentration of Si and C was 1 × 10 ¹⁵ cm ⁻³ or less and the resistance was high (point a in FIG. 3), × 10 ¹⁵ cm ^-3
In this case (point b in FIG. 3), a wafer was prepared.

Next, using the wafers of these samples, a recess is formed by etching, and a source electrode 5, a gate electrode 6, and a drain electrode 7 are formed.
(FIG. 2) was fabricated, and the DC characteristics of the transistor were measured and compared. Each transistor was adjusted to have a threshold voltage of 2.5 V by recess etching. The gate length is 0.8 μm. The distance between the source and the gate and the distance between the drain and the gate are 1 μm.

FIG. 3 shows the relationship between the impurity concentration (cm ^-3 ) and the gate breakdown voltage (V). The gate breakdown voltage is determined by the gate current I
g is defined as the gate voltage at which Ig = 10 μm. When the additive concentration was 5 × 10 ¹⁵ cm ⁻³ (point b in FIG. 3) of the comparative example,
The gate withstand voltage when the gate withstand voltage is 18 V and no addition is performed (FIG. 3
(Point a in FIG. 3), but when the concentration of the added impurity is 1 × 10 ¹⁶ cm ⁻³ or more in this embodiment (points c and d in FIG. 3), the gate withstand voltage exceeds 20 V, which is 2 V As described above, the breakdown voltage is high.

FIG. 4 shows the impurity concentration (cm ^-3 ) and the FE
The relationship between the mutual conductance gm (mS / mm) of T and the drain conductance gd (mS / mm) is shown. Each has a drain voltage of 3 V and a drain current of 50 mA / mm
It shows the value when Again, when the impurity concentration is higher than 1 × 10 ¹⁶ cm ⁻³ , the transconductance g
m increases, and the drain conductance gd decreases.

In short, the buffer layer 2 has an AlGaAs layer containing shallow donor impurities Si and shallow acceptor impurities C at a concentration of 1 × 10 ¹⁶ cm ⁻³ or more, respectively, and having an Al composition ratio of 0.2 or more. By using the above technique, the withstand voltage of the field effect transistor can be increased. In this embodiment, the voltage can be increased by 2 V or more. In addition, the gain and saturation characteristics (mutual conductance and drain conductance) of the FET are improved.

In the above embodiment, the FET having the recess structure has been described, but the so-called planar type compound semiconductor FE is used.
T, ie LDD (Lightly Dopaed Drain) structure, BP
The present invention can be applied not only to an LDD (Buried p-layer LDD) structure, but also to a wide range of general planar devices having a buffer layer below a channel layer.

[0040]

As described above, according to the present invention, the following excellent effects can be obtained.

(1) According to the compound semiconductor epitaxial wafer of the first to seventh aspects, the buffer layer contains shallow donor impurities and shallow acceptor impurities each having a concentration close to each other at a concentration of 1 × 10 ¹⁶ cm ⁻³ or more. Since they are contained at the same time, they act as ionic scattering sources of the carriers injected into the buffer layer, and lower the mobility of the carriers. This effect of lowering the carrier mobility becomes apparent when the impurity concentration is 1 × 10 ¹⁶ cm ⁻³ or more. Since the mobility of carriers in the buffer layer is reduced, the withstand voltage of the transistor can be increased, and the gain and saturation characteristics (mutual conductance and drain conductance) can be improved.

(2) According to the compound semiconductor epitaxial wafer of the second aspect, the buffer layer is made of GaAlA.
Since a case of a compound semiconductor layer containing Al such as s and InAlAs is handled, when a donor impurity is added, a deep level called a DX center is formed, and the conductivity of the material can be easily reduced. . Further, the Al mixed crystal ratio of the buffer layer is set to 0.2 such that the DX center becomes apparent.
As described above, the band gap increases and the leakage current itself decreases.

(3) In the compound semiconductor epitaxial wafer according to the third aspect, since the buffer layer is made of an AlGaAs layer, the leakage current is smaller than when the buffer layer is made of GaAs.

[0044] (4) Compound semiconductor epitaxial wafer according to claim 4, the difference between the total concentration [N _D] shallow total concentration of the acceptor impurity [N _A] a shallow donor impurities [N _A] - [N _D ] Is lower than the concentration of oxygen usually contained in AlGaAs, so that the resistance of the buffer layer can be further increased.

[0045] (5) Similarly, the compound semiconductor epitaxial wafer according to claim 5, total concentration total concentration of [N _A] shallow donor impurities of the shallow acceptor impurities [N _D]
The difference between [N _A] - the absolute value of [N _D] is, since the below a concentration of DX centers the shallow donor impurities in AlGaAs is formed, making it possible to further increase in the resistance of the buffer layer it can.

(6) According to the eighth aspect, a compound semiconductor device (planar device) having a high breakdown voltage and a high gain can be obtained by using a compound semiconductor epitaxial wafer.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a compound semiconductor epitaxial wafer of the present invention.

FIG. 2 is a view showing an embodiment of a field-effect transistor using the compound semiconductor epitaxial wafer of the present invention.

FIG. 3 is a graph showing a relationship between an impurity concentration of a buffer layer and a gate breakdown voltage.

[FIG. 4] Doped impurity concentration and transconductance (gm)
6 is a graph showing a relationship between the resistance and drain conductance (gd).

FIG. 5 is a sectional view showing a field effect transistor using a conventional epitaxial wafer.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semi-insulating GaAs substrate 2 AlGaAs buffer layer 3 n-type GaAs channel layer 4 n-type GaAs contact layer 5 source electrode 6 gate current 7 drain electrode

Claims (8)

[Claims] In a compound semiconductor epitaxial wafer used for a planar type device and having a buffer layer below a channel layer, the buffer layer contains a shallow donor impurity and a shallow acceptor impurity each having a close concentration of 1 × 10 ¹⁶ cm. A compound semiconductor epitaxial wafer having a compound semiconductor layer simultaneously contained at a concentration of ^-3 or more. 2. A compound semiconductor epitaxial wafer used in a planar type device and having a buffer layer below a channel layer, wherein the buffer layer contains shallow donor impurities and shallow acceptor impurities each having a close concentration of 1 × 10 ¹⁶ cm. A compound semiconductor epitaxial wafer having a compound semiconductor layer containing Al at the same time at a concentration of ^-3 or more and having an Al mixed crystal ratio of 0.2 or more. 3. A compound semiconductor epitaxial wafer used for a planar type device and having a buffer layer below a channel layer, wherein the buffer layer contains shallow donor impurities and shallow acceptor impurities at 1 × 10 ¹⁶ cm ⁻³ , respectively.
It is contained simultaneously at the above concentrations, and the AlAs mixed crystal ratio is 0.1.
A compound semiconductor epitaxial wafer having two or more AlGaAs layers. 4. A total concentration of said shallow acceptor impurities [N
_A ] and the absolute value of the difference [N _A ] − [N _D ] between the shallow donor impurity total concentration [N _D ] is lower than the concentration of oxygen usually contained in AlGaAs. The compound semiconductor epitaxial wafer according to claim 3. 5. A total concentration of said shallow acceptor impurities [N
The difference between the total concentration [N _D] of the shallow donor impurities and _A] [N _A] - the absolute value of [N _D] has to be lower than the density of DX centers the shallow donor impurities in AlGaAs is formed 5. The compound semiconductor epitaxial wafer according to claim 4, wherein: 6. The method according to claim 6, wherein said shallow donor impurities are Si, S
6. The compound semiconductor epitaxial wafer according to claim 1, wherein the compound semiconductor epitaxial wafer contains any of e, Ge, Sn, and Te. 7. The method according to claim 7, wherein the shallow acceptor impurity is C,
6. The compound semiconductor epitaxial wafer according to claim 1, wherein the compound semiconductor epitaxial wafer contains one of Be, Zn, Mn and Mg. 8. The method of claim 1, 2, 3, 4, 5, 6, or 7.
A compound semiconductor device produced using the compound semiconductor epitaxial wafer described in the above.