JPH09246527A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve controllability of a conductivity type and specific resistance by realizing that an inert element is one kind of element among hydrogen, fluorine, oxygen and chlorine and a region wherein an inert element exists is a p-type region. SOLUTION: An InP buffer layer 22, an i-type InGaAs electron transit layer 23, an n<+> -type InAlAs electron supply layer 24, an i-type InGaP layer 25 and an n-type InAlAs layer 26 wherein Si and Fe are added are laminated one by one on an Fe doped semiinsulating InP substrate 21. Concentrations of Si and Fe are 5×10<17> cm<-3> and 1×10<17> cm<-3> , respectively. Since a region wherein an inert element exists reverses to a p-type region by adding an inert element (such as hydrogen) for making a donor element of a shallow donor level inert to a semiconductor layer wherein a donor element of a concentration Nd at a shallow donor level and an acceptor element of a concentration of Na at a shallow acceptor level are distributed approximately uniform having a relation of Nd>Na, a conductivity type and specific resistance immediately below a gate can be controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a compound semiconductor layer and used for an optoelectronic device.

[0002]

2. Description of the Related Art Generally, there are various types of optoelectronic devices, but semiconductor devices having a III-V group compound semiconductor thin layer containing In and Al, for example, as components are widely used.

This type of semiconductor device includes an InP high electron mobility transistor (hereinafter referred to as HEMT) having an InAlAs thin layer lattice-matched to an InP substrate. FIG. 11 is a sectional view schematically showing the structure of this HEMT. This HEMT is a Fe-doped semi-insulating InP substrate 1
On top, undoped InAlAs buffer layer 2, undoped InGaAs electron transit layer 3, undoped InAlAs
The spacer layer 4, the Si-doped n-type InAlAs electron supply layer 5, the undoped InAlAs Schottky contact layer 6, and the Si-doped n-type InGaAs ohmic contact layer 7 are sequentially stacked and formed.

When the drain electrode 8 and the source electrode 9 are formed on the ohmic contact layer 7, the region corresponding to the gate portion is removed so that the Schottky contact layer 7 in the gate portion is exposed. To be done. After that, the gate electrode 10 is formed on the exposed portion of the Schottky contact layer 7, and the whole is covered with a SiN protective film (not shown).

As described above, in the InP HEMT, the magnitude of energy discontinuity in the conduction band of the heterojunction is ΔE.
In order to increase ΔEc with InGaAs of the electron transit layer 3, the buffer layer 2, the spacer layer 4, the electron supply layer 5, the Schottky contact layer 6 and the like are made of InAlAs.
Is used.

InAl used for the electron supply layer 5
While As must be n-type doped,
InAlAs used for the other layers 2, 4, and 6 improves the extra leakage current and the pinch-off characteristics,
The resistance is preferably high, and the concentration of residual impurities that generate carriers such as electrons and holes is desirably controlled as low as possible.

However, in the Si-doped InAlAs electron supply layer 5 of the InP-based HEMT, F adhering to the InAlAs surface during the device fabrication process diffuses internally during the heat treatment, and this F bonds with the donor impurities to inactivate the donor. Therefore, there is a problem that carriers are compensated and electrical characteristics are deteriorated. F inside such a crystal
Diffusion occurs only in crystals containing In and Al,
It is considered to be a phenomenon caused by the combination of In and Al. In addition to chemicals such as ammonium fluoride used in the device manufacturing process, F is also mixed from the atmosphere, so F
It is virtually impossible to prevent the mixture of

On the other hand, InP-based HEMT buffer layer 2,
In the Schottky contact layer 6 and the spacer layer 4, for example, metal organic chemical vapor deposition (MOCV) suitable for mass production.
In the case of manufacturing by the method D), there is a problem that it is difficult to form an InAlAs layer having a low residual carrier concentration from the viewpoint of the purity of the raw material. It should be noted that the use of high-purity raw material causes a problem of extremely high cost.

On the other hand, as a related technique for solving this problem, it is known to dope impurities such as Fe forming a deep level acceptor to compensate for residual carriers. However, although there are reports of growth of a high-resistance Fe-doped InAlAs layer by the MOCVD method, there are few cases where it is used for an actual HEMT device. this is,
This is because the Fe-doped InAlAs layer formed by the MOCVD method has extremely narrow growth conditions for increasing the resistance and has a problem in reproducibility.

Controlling the conductivity type and resistivity of the semiconductor in this manner is an important technique in the device manufacturing process. There are roughly two types of this type of technology. One is a method of implanting a high energy element into a semiconductor like an ion implantation technique. The other is to expose the semiconductor surface to a gas atmosphere containing an impurity element as in the case of diffusing Zn into GaAs, or to directly contact the impurity element with GaAs to form an alloy electrode with AuGe, This is a method of diffusing during heat treatment.

Although these methods are used for actual device fabrication, they are still insufficient when it is desired to selectively change the conductivity type or resistivity in a device having a fine structure. In these methods, the distribution of impurity elements cannot be changed sharply,
Also, the impurity distribution is defined by the process parameters. The process parameters are, for example, acceleration energy in ion implantation and heat treatment temperature and time in thermal diffusion. Further, in the impurity distribution, for example, in the case of thermal diffusion, the controllability in the depth direction is poor, and the in-plane uniformity is not very good.

[0012]

As described above, in this type of semiconductor device, it is possible to use high-priced raw materials,
There is a problem that it is difficult to form high-resistance InAlAs layers 2, 4, and 6 having extremely low residual carrier concentration.

When InAlAs is grown by MOCVD, the residual carrier concentration achieved is 1 ×.
It is about 10 ¹⁵ cm ^-3 . When such an InAlAs layer is used for the buffer layer 2 such as HEMT, the spacer layer 4, and the Schottky contact layer 6, it adversely affects the device characteristics such as an increase in buffer leak current, pinch-off characteristics, and deterioration of noise characteristics. I have a problem to give.

On the other hand, in the electron supply layer 5, although it is desired to prevent F from being mixed so that carrier compensation is less likely to occur, there is a problem that it is practically impossible to prevent F from being mixed.

In summary, there is a problem that the technique for controlling the conductivity type and the resistivity of the semiconductor device is still insufficient. The present invention has been made in consideration of the above circumstances,
An object of the present invention is to provide a semiconductor device having improved conductivity type and controllability of resistivity.

A second object of the present invention is to provide a semiconductor device having a high resistance semiconductor layer having an extremely low residual carrier concentration. Further, a third object of the present invention is to provide a semiconductor device capable of preventing carrier compensation by fluorine mixed therein.

[0017]

The first gist of the present invention is:
Conduction is arbitrarily performed by adding an n-type donor impurity element and a p-type acceptor impurity element to the compound semiconductor, and intentionally adding a third impurity element such as H, O, F, or Cl. It is to control the mold and the resistivity. In particular, even when the donor concentration is higher than the acceptor concentration, the conductivity type can be controlled to the p-type by the third impurity element. This technique is used for layers that preferably have high resistance in device applications. For example, in HEMTs, one or more layers other than the electron supply layer, which are the buffer layer, the Schottky contact layer, and the spacer layer, are used. Applied.

The second skeleton of the present invention is In and Al.
By including B in the III-V compound semiconductor containing and, the carrier compensation by F is reduced. This technique is used for layers that need to be n-type doped for device applications, for example in HEMTs for electron supply layers.

Next, the first and second gist of the present invention will be described in detail. (Description of first skeleton) For example, for InAlAs,
Si, Sn, Se, S, etc. serve as donor elements, and Be,
Zn or the like becomes the acceptor element. Further, Fe becomes a deep acceptor and O becomes a deep donor.

In the semiconductor, if the shallow donor concentration is Nd and the shallow acceptor concentration is Na, the difference between them is | Nd-Na |.
Determines the carrier concentration and resistivity, and the higher concentration determines the conductivity type. Usually, heavy metals other than these and C and other light elements are present as residual impurities in the compound semiconductor. However, the residual concentration thereof is usually low, even 1 × 10 ¹⁷ cm ⁻³ or less even in the substrate, and the concentration becomes lower when epitaxially grown, which is lower than the main donor concentration and acceptor concentration. Although InAlAs that is not intentionally doped has a small amount of residual impurities and is n-type, if Fe is doped, InAlAs can be compensated for this small amount of donor and the resistance of InAlAs can be increased.

Now, halogen elements such as F and Cl and H,
O is a factor that hinders activation of the donor because it easily bonds to the donor element. For example, in InAlAs, if O is present, the electron concentration becomes lower than the donor concentration. It is considered that this is because O bonds with Si to form a deep level (eg, S. Narituka, T. Noda, A. Wa).
gai, S.Fujita, Y.Asizawa, J.Crystal Growth, vol.131, p.
186, 1993). Further, when F is mixed into n-type InAlAs, F binds to a donor element to inactivate it and lowers carrier concentration (for example, N. Hayafuji, Y. Yamamoto,
N.Yoshida, T.Sonoda, S.Takamiya, S.Mitsui, Appl.Phys.L
ett.vol.66, p.863, 1995 and Extended Abstract of the
7th International Conference on Indium Phoshide a
nd Related Materials, paper WP49 1995 pp265). Note that F is mixed into the crystal only inside the crystal containing In and Al.

By the way, the mechanism of such inactivation has not been clarified yet. The passivated state is quite stable thermally, and once passivated, it is not released at the process temperature of a typical compound semiconductor. On the other hand, acceptors are less susceptible to such inactivation.

Therefore, if the third impurity element is made to coexist in the region in which the donor having the concentration Nd and the acceptor having the concentration Na are simultaneously contained to inactivate the donor, even if Nd> Na, the inactivation is performed. Depending on the degree, increase the n-type resistance,
Alternatively, the conductivity type can be inverted to p-type. (Explanation of the second skeleton) B has a larger chemical bond energy with F than Si, Se, S, etc. which are n-type dopants of InAlAs (BF: 641 kJ / mol, Si-F: 592 kJ / mo).
l, Se-F: 322kJ / mol, SF: 298kJ / mol, Chemical Handbook Basics II, pp322). That is, in the InAlAs layer containing B, since the mixed F has a higher probability of being bonded to B than the n-type dopant described above, carrier compensation is less likely to occur.

Therefore, by adding B to the III-V group compound semiconductor containing In and Al, the carrier compensation by F can be reduced. The above is the outline of the present invention.
Subsequently, a third impurity element adding means applied to the present invention will be described. (Adding Means) As an adding means, an atmospheric gas during epitaxial growth may be used. For example, when InAlAs is grown by the MOCVD method, arsine AsH ₃ which is a raw material of a group V element and trimethylaluminum (CH ₃ ) ₃ Al and trimethylindium (CH ₃ ) ₃ In which are raw materials of a group III element are supplied. When used, since there is an active Al element, it is easy to mix O remaining in the carrier gas and the source gas. The mixing amount of O depends on the ratio of the raw material supply amount and the growth temperature, and can be controlled by changing the V / III ratio. Further, as a source material of O, a separate source material containing O may be used as a doping gas. As described above, in the method of adding the third impurity element during the epitaxial growth, the third impurity element is mixed into the entire surface of the wafer.

Next, a method of adding the third impurity element only to a specific region, not the entire surface of the wafer will be described. Since this method is difficult to realize by epitaxial growth, selective diffusion using a mask is used. That is, the surface of the semiconductor substrate is masked into a desired shape by the process, and then the semiconductor substrate is exposed to an atmosphere gas containing the third impurity element, so that the third impurity element diffuses into a specific region. To be done.

For example, FIG. 1A is a diagram showing a state before diffusion, in which the InP buffer layer 12 is formed on the InP substrate 11.
The n-type InAlAs layer 13 is sequentially stacked, and the n-type I
A mask layer 14 is selectively formed on the nAlAs layer 13.

Here, the mask layer 14 is a layer for partially exposing the surface of the InAlAs layer 13, and may be formed by etching an epitaxial growth layer such as an InGaAs layer or an InP layer, or , Si
It may be formed by stacking a protective film such as an O ₂ film or a SiN film and then etching.

In the structure of FIG. 1A, n-type InAl
It is assumed that the As layer 13 is simultaneously doped with a donor element having a concentration Nd and a p-type acceptor element having a concentration Na lower than the concentration Nd during the epitaxial growth.

At this time, if the third impurity element that inactivates the donor element is diffused from the surface, the donor is inactivated in the diffusion region 15 shown in FIG. 2B. For example, Nd = 2 × 10 ¹⁸ cm ⁻³ , Na = 1 × 10 ¹⁸ cm
^{With a value of -3} , the conductivity type of the diffusion region 15 can be inverted from n-type to p-type by sufficiently promoting the inactivation of the donor.

In addition, in the structure of FIG.
It is assumed that the nAlAs layer 13 is simultaneously doped with a donor element having a concentration of Nd and Fe serving as a deep acceptor for the donor during the epitaxial growth. However, the Fe concentration is NFe.

Similarly to the above, when the third impurity element for inactivating the donor element is diffused from the surface, FIG.
In the diffusion region 15 shown by (3), inactivation of the donor occurs.
For example, Nd = 1 × 10 ¹⁸ cm ^-3 and NFe = 1 × 10 ¹⁷ c
m ^-3 , if the inactivation of the donor is sufficiently promoted,
The conductivity type of the diffusion region 15 can be controlled from n-type to high resistance.

As described above, by controlling the shallow donor concentration Nd, the shallow acceptor concentration Na, and the deep acceptor Fe concentration NFe, the resistivity and conduction type can be arbitrarily changed during the process.

As described above, B is preferably added at the same time during the epitaxial growth of the semiconductor layer containing In and Al from the viewpoint of providing a steep depth direction profile in the device. For example, like HEMT,
In a device having a multi-layer structure, it is impossible to contain B only in the electron supply layer by ion implantation, but it is sufficiently possible by epitaxial growth.

Based on the above-described gist of the present invention and the means for adding an impurity element, the following means for solving the problems are specifically realized. The invention corresponding to claim 1 is such that a donor element having a concentration of Nd at a shallow donor level and an acceptor element having a concentration of Na at a shallow acceptor level have a relationship of Nd> Na and are substantially uniformly distributed, and A semiconductor device comprising a semiconductor layer containing an inactivating element for inactivating a donor element having a shallow donor level, wherein the inactivating element is hydrogen (H), fluorine (F), oxygen ( O) and chlorine (Cl), and the region where the inactivating element is present is a p-type region.

Further, in the invention corresponding to claim 2, the donor element having a concentration of Nd at a shallow donor level and the acceptor element having a concentration of Nda at a deep acceptor level have a relationship of Nd> Nda and are substantially uniform. A semiconductor device having a semiconductor layer that is distributed and contains an inactivating element for inactivating the donor element of the shallow donor level, wherein the inactivating element is hydrogen, fluorine, oxygen, or chlorine. The semiconductor device is any one of the elements, and the region in which the passivating element is present has a higher resistance than the other regions in the semiconductor layer.

Further, the invention according to claim 3 is a semiconductor device comprising a III-V group compound semiconductor layer containing at least indium (In) and aluminum (Al), wherein the compound semiconductor layer comprises: The semiconductor device contains boron (B) at a ratio of 0.5% or less with respect to the concentration of its own group III element.

The semiconductor layer corresponding to claim 3 is B
When the composition other than is almost the same, the same electrical characteristics as the conventional semiconductor layer are obtained. This is because B is a group III element,
This is because it does not serve as either a donor or an acceptor in the III-V group compound semiconductor.

Similarly, the B concentration of the semiconductor layer corresponding to claim 3 is a value that does not change Eg and ΦB of the conventional semiconductor layer. FIG. 2 is a diagram showing the degree of carrier inactivation by F corresponding to the doping concentration of B. As shown in the figure, the B concentration required to prevent carrier compensation is about the doping concentration. The doping concentration is generally 0.1% or less of the group III composition of the host crystal, and
It does not change Eg, ΦB, etc. of As. Here, the B concentration may be 0.1% or more of the group III composition of the host crystal, but from the viewpoint of improving the crystallinity, it is desirable to suppress the hatching due to lattice mismatch. That is, in the case of the InAlAs layer, the B concentration is preferably 0.5% or less of the group III composition. (Operation) Therefore, the invention corresponding to claim 1 takes the concentration Nd at a shallow donor level by taking the above means.
To inactivate the donor element of the shallow donor level with respect to the semiconductor layer in which the donor element of 3 and the acceptor element of concentration Na at the shallow acceptor level have a relationship of Nd> Na and are almost uniformly distributed. When the passivating element is added, the region where the passivating element exists is inverted to the p-type region, so that the conductivity type immediately below the gate and the controllability of the resistivity can be improved.

Further, in the invention according to claim 2, the donor element having a concentration of Nd at the shallow donor level and the acceptor element having a concentration of Nda at the deep acceptor level have a relationship of Nd> Nda and are substantially uniform. By adding an inactivating element for inactivating the donor element having a shallow donor level to the distributed semiconductor layer, the area where the inactivating element exists is more than the other area in the semiconductor layer. Since the resistance is also increased, a high resistance semiconductor layer having an extremely low residual carrier concentration can be realized.

Furthermore, the invention corresponding to claim 3 is In
Since B is contained in the III-V group compound semiconductor crystal containing Al and Al, the binding of B to F prevents the compensation of carriers by F.

[0041]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) In the present embodiment, Si, F
By adding e and F, the resistance of InAlAs immediately below the gate is increased.

FIG. 3 shows an F according to the first embodiment of the present invention.
It is sectional drawing which shows the structure of ET typically. This FET
Is an InP buffer layer 22, an i-type InGaAs electron transit layer 23, and n + on a Fe-doped semi-insulating InP substrate 21.
Type InAlAs electron supply layer 24, i type InGaP layer 2
5, the n-type InAlAs layer 26 is sequentially stacked. Note that Si and Fe are added to the n-type InAlAs layer 26.

A plurality of n layers are formed on the n-type InAlAs layer 26.
A + type InGaAs ohmic contact layer 27 is selectively formed, and a drain electrode 28 or a source electrode 29 is individually formed on each n + type InGaAs ohmic contact layer 27.

The n-type InAlAs layer 26 has n +
The region sandwiched by the InGaAs ohmic contact layers 27 is made into a high resistance region 30 by diffusion of F, and a gate electrode 31 is formed on this high resistance region 30.

Next, the manufacturing method and operation of the above FET will be described. First, the structure shown in FIG. 4A is epitaxially grown by the MOCVD method. As the growth raw material, trimethylgallium (CH ₃ ) ₃ Ga, trimethylaluminum (CH ₃ ) ₃ Al, trimethylindium (CH ₃ ) ₃ In, arsine AsH ₃ , phosphine PH ₃ , and disilane Si ₂ as a dopant raw material.
H ₆ and ferrocene CP ₂ Fe are used.

That is, as shown in FIG.
An undoped InP buffer layer 22 and an undoped InGaAs electron transit layer 2 on a doped semi-insulating InP substrate 21.
3. The Si-doped n + type InAlAs electron supply layer 24 and the undoped i-type InGaP layer 25 are grown. continue,
Si is added at 5 × 10 ¹⁷ cm ⁻³ and Fe is added at 1 × 10 ¹⁷ cm ^{−3 at} the same time to grow the n-type InAlAs layer 26. Then, a Si-doped n + type InGaAs ohmic contact layer 27 is grown.

The FET is manufactured by a very general process. The part where the FET is not formed is etched up to the InP substrate 21 to separate the elements between the FETs. Continuing, A
After vapor deposition of uGeNi, heat treatment is performed in a nitrogen atmosphere to form a drain electrode 28 and a source electrode 29, which are alloy ohmic electrodes, as shown in FIG. 4B.

Thereafter, as shown in FIG. 4C, a resist 32 is applied, and a gate formation port is opened by photolithography. As shown in FIG.
The nGaAs ohmic contact layer 27 is selectively removed by etching. In addition, at the time of etching,
A mixed solution of citric acid and H ₂ O ₂ that can selectively etch only the InGaAs ohmic contact layer 27 is used so that the etching stops at the n-type InAlAs layer 26.

Subsequently, after exposing the wafer surface to the HF atmosphere for 5 minutes, the gate metal is vapor-deposited and the gate electrode 31 is formed by lift-off. Then, in a nitrogen atmosphere,
Heat treatment is performed at 300 ° C. for 15 minutes. The F remaining on the wafer surface when exposed to the HF atmosphere by this heat treatment
Diffuse to inactivate Si in InAlAs. If the n-type InAlAs layer is doped with only Si, the carrier concentration of the n-type InAlAs will only decrease. However, in the present embodiment, the n-type InAlAs layer 26 is doped with Fe, which is a deep acceptor, at a high concentration in addition to Si, so that the region in which F is diffused becomes the high resistance region 10.

The FET manufactured in this manner has the following advantages (1) to (3), which are different from the conventional ones. (1) Since the n-type InAlAs immediately below the gate electrode has a high resistance, the Schottky barrier height ΦB becomes high,
The gate leak current can be reduced. (2) Since the n-type InAlAs near the gate also has a high resistance, the gate breakdown voltage can be improved. (3) Since the n-type InAlAs near the ohmic electrode is the same epitaxial growth layer as the n-type InAlAs layer 6 near the gate, Si is not inactivated, so that the n-type conductivity and the low resistivity can be obtained. keeping. As a result, a low source resistance can be maintained. (Second Embodiment) Next, an FET according to a second embodiment of the present invention will be described with reference to FIG.
Detailed description of the same parts as those in the first embodiment will be omitted, and only different parts will be described here.

That is, this embodiment is a modification of the first embodiment, and a part of the n-type InAlAs layer is p-type.
It is an inversion of the mold layer. Specifically, in the manufacturing method according to the first embodiment, instead of ferrocene CP ₂ Fe,
When n-type InAlAs is epitaxially grown using dimethylzinc as a Zn dopant gas, 1 × 1
Zn of about 0 ¹⁷ cm ^{-3 is} doped at the same time as Si as described above.

The high resistance region 30 of the n-type InAlAs layer 26 shown in FIG. 3 becomes a p-type region in the second embodiment by going through the same steps as in the first embodiment. The FET manufactured in this way is different from the conventional one.
It has the following advantages (1) to (2). (1) Since the n-type InAlAs immediately below the gate electrode is inverted to the p-type, the gate can operate with a pn junction instead of the Schottky, the gate breakdown voltage can be increased, and the gate leak current can be reduced. (2) Since the n-type InAlAs near the ohmic electrode is the same epitaxial growth layer as the n-type InAlAs near the gate, Si is not inactivated.
It retains n-type conductivity and low resistivity. As a result, a low source resistance can be maintained. (Third Embodiment) Next, a heterojunction bipolar transistor (hereinafter referred to as HB) according to a third embodiment of the present invention.
(T) will be described. In this embodiment,
It shows application to HBT, and the resistance of the n-type InAlAs emitter layer is increased by adding Si, Fe and O.

FIG. 5 is a sectional view schematically showing the structure of this HBT. In this HBT, an n + type InGaAs collector contact layer 42 is formed on a semi-insulating InP substrate 41, and this n + type InGaAs collector contact layer 4 is formed.
A collector electrode 43 and an n-type InGaAs collector layer 44 are selectively formed on the second electrode 2.

On the n-type InGaAs collector layer 44, p is formed.
The p-type InGaAs layer 45 is formed, and p + -type InGaA is formed.
A base electrode 46 and a thin n-type InA are formed on the s layer 45.
The lAs emitter layer 47 is selectively formed. The n-type InAlAs emitter layer 47 has Si and Fe added during epitaxial growth, and has a shallow region 47a in which O is diffused in a later step in the side surface portion.

S is formed on the n-type InAlAs emitter layer 47.
i-doped n-type InAlAs emitter layer 48, n + -type In
AlAs emitter contact layer 49, emitter electrode 50
Are sequentially laminated.

Next, the manufacturing method and operation of the above HBT will be described. By MOCVD method, FIG.
The structure shown in is grown epitaxially. The growth raw material is trimethylgallium (CH ₃ ) ₃ Ga, (CH ₃ )
₃ Al, (CH ₃ ) ₃ In, arsine AsH ₃ , phosphine PH ₃ , and disilane Si as a dopant raw material.
₂ H ₆ and ferrocene CP ₂ Fe are used.

As shown in FIG. 6A, an n + type InGaAs collector contact layer 42, an n type InGaAs collector layer 44, p are formed on a Fe-doped semi-insulating InP substrate 41.
A + type InGaAs base layer 45 is grown. continue,
Thin InAlAs emitter layer 47, S doped with 4 × 10 ¹⁷ cm ⁻³ Si and 1 × 10 ¹⁷ cm ⁻³ Fe
n-type InAlAs emitter layer 4 doped only with i
8. Grow n-type InGaAs emitter contact layer 49.

FIG. 6B is a process diagram showing a stage in the middle of the process in which the base layer 45 is etched. As shown, the n-type InGaAs emitter contact layer 49
A resist 52 is applied on top of it via a SiO ₂ film 51. The hatching on both sides of the device is the insulating region 53 formed by ion implantation.

Next, the wafer surface is exposed to an oxygen plasma atmosphere for a short time. At this time, oxygen diffuses from the surface and inactivates Si, so that the resistance of the shallow region 47a is increased as shown in FIG. 6C. Subsequently, a base electrode metal is vapor-deposited, lifted off, and then heat-treated to form a base electrode 46 which is an alloy electrode.

Hereinafter, the collector electrode 43 and the emitter electrode 5
0 is formed and the HBT is completed. HBT like this
According to the method, the shallow region 47 which is the side surface of the emitter layer 47
Since a has a high resistance, that is, the exposed surface of InAlAs is depleted, this portion functions as a guard ring. Therefore, it is possible to prevent undesired recombination on the surface and prevent the reduction of the current gain of the HBT. (Fourth Embodiment) Next, an InP HEMT according to a fourth embodiment of the present invention will be described.

In this embodiment, the addition of F makes the Schottky contact layer and the buffer layer have high resistance, and
The F is confined in the Schottky contact layer and the buffer layer by sandwiching the added Schottky contact layer and the buffer layer with semiconductor layers other than n-type InAlAs, respectively.

FIG. 7 is a sectional view schematically showing the structure of this InP HEMT. This InP HEMT is Fe
On the doped semi-insulating InP substrate 61, 300 nm thick F
Doped InAlAs buffer layer 62, 25 nm thick undoped InGaAs electron transit layer 63, 3 nm thick F-doped InAlAs spacer layer 64, 3 nm thick undoped InP hole barrier layer / F diffusion preventing layer 65, 10 nm Si-doped InAlAs electron supply layer 66, 5 nm thick undoped InAlGaAs layer and F diffusion prevention layer 67, 1
An F-doped InAlAs Schottky contact layer 68 having a thickness of 5 nm is sequentially stacked.

A plurality of Si-doped n-type InGaAs is formed on the F-doped InAlAs Schottky contact layer 68.
The ohmic contact layer 69 is selectively formed, and each S
i-doped n-type InGaAs ohmic contact layer 69
The drain electrode 70 or the source electrode 71 is individually formed on the top.

In the F-doped InAlAs Schottky contact layer 68, the gate electrode 72 is formed on the region sandwiched by the Si-doped n-type InGaAs ohmic contact layers 69.

Here, n-type In is used as both diffusion prevention layers.
Other semiconductor layers different from AlAs are used, for example:
GaAs, AlGaAs, InGaAs, InAlGa
As, InP, AlInP, InGaP, InGaAl
III-V containing at least one of Ga such as P and P
Group compound semiconductors can be appropriately used. The diffusion prevention layer utilizes the property that fluorine F does not diffuse into the semiconductor layers other than n-type InAlAs.

Next, the manufacturing method and operation of the above InP HEMT will be described. First, crystal growth is performed on the Fe-doped semi-insulating InP substrate 61 by the MOCVD method. I at growth temperature of 650 ° C and growth pressure of 70 torr
It is grown so as to be lattice-matched on the nP substrate. The growth raw materials include trimethylindium (CH ₃ ) ₃ In, trimethylgallium (CH ₃ ) ₃ Ga, trimethylaluminum (CH ₃ ) ₃ Al, arsine AsH ₃ , phosphine P.
H ₃ and disilane Si as a raw material for Si
₂ H ₆ is used.

First, the Fe-doped semi-insulating InP substrate 61.
A 300 nm thick undoped InAlAs buffer layer 62 ^* is formed on top. Next, this undoped InAlA
The s buffer layer 62 ^* is exposed to the atmosphere of fluorine gas or fluorine compound gas for 10 minutes. As the fluorine compound gas, there is, for example, CF ₄ , or CF ₄ is replaced by N ₄ .
_It may be diluted with ₂ gases.

Then, this wafer is left in an MO atmosphere at 400 ° C. for 10 minutes in an As atmosphere to remove F
Are diffused into the undoped InAlAs buffer layer 62 ^* , so that the undoped InAlAs buffer layer 62 ^* becomes the F-doped InAlAs buffer layer 62.

Thereafter, an undoped InGaAs electron transit layer 63 with a thickness of 25 nm and an undoped InAlAs spacer layer 64 ^* with a thickness of 3 nm are sequentially laminated on the F-doped InAlAs buffer layer 62.

Here, as described above, this wafer is a MOC.
The undoped InAlAs spacer layer 64 is left in the VD apparatus at 400 ° C. for 10 minutes in an As atmosphere so that F is undoped.
^* Diffused in this undoped InAl
The As spacer layer 64 ^* becomes the F-doped InAlAs spacer layer 64.

Next, on the F-doped InAlAs spacer layer 64, a 3 nm thick undoped InP hole barrier layer / F diffusion preventing layer 65 and a 10 nm thick Si-doped n-type I layer are formed.
nAlAs electron supply layer 66, 5 nm thick undoped In
An AlGaAs layer / F diffusion preventing layer 67 and a 15 nm thick undoped InAlAs Schottky contact layer 68 ^* are sequentially formed.

This wafer was left in an MOCVD apparatus at 400 ° C. for 10 minutes in an As atmosphere in the same manner as described above, and F was diffused into the undoped InAlAs Schottky contact layer 68 ^* , whereby the undoped InAlAs was diffused. The Schottky contact layer 68 ^* becomes the F-doped InAlAs Schottky contact layer 68.

Next, on the F-doped InAlAs Schottky contact layer 68, Si-doped n-type InGaA is formed.
The s ohmic contact layer 69 is formed. For the wafer having the laminated structure thus obtained, HEMT
The part where no is formed is etched up to the InP substrate 61 to isolate the HEMT. A drain electrode 70 and a source electrode 71 are formed on the Si-doped n-type InGaAs ohmic contact layer 69.

Next, the gate region is patterned by the electron beam direct writing method, and the ohmic contact layer 69 in the gate region is removed by recess etching to expose the F-doped InAlAs Schottky contact layer 69 in the gate region.

A gate length of 0.1 is formed on the exposed portion of the F-doped InAlAs Schottky contact layer 69.
A μm T-shaped gate electrode 72 is formed. Finally, the entire surface is covered with a SiN protective film.

According to the HEMT manufactured in this way,
Good high frequency characteristics can be obtained. (Fifth Embodiment) Next, an InP HEMT according to a fifth embodiment of the present invention will be described. FIG. 8 is a sectional view schematically showing the structure of this InP-based HEMT.
The same parts as those in FIG. 7 are designated by the same reference numerals and detailed description thereof will be omitted, and only different parts will be described here.

That is, the present embodiment is a modification of the fourth embodiment, in which only the buffer layer 62 is a layer whose resistance is increased by the addition of F. Doped InAlAs Schottky contact layer 68
The F-doped InAlAs spacer layer 64 is made into the undoped layers 68 ^* and 64 ^* without adding F, and accordingly, the undoped InP hole barrier layer / F diffusion prevention layer 65 and the undoped InAlGaAs layer / F diffusion prevention are also formed. The layers 67 and 67 are omitted.

Even with such a structure, F-doped InA
With respect to the lAs buffer layer 62, the same effect as that of the fourth embodiment can be obtained. (Sixth Embodiment) Next, a channel dope FET according to a sixth embodiment of the present invention will be described. In addition,
In the present embodiment, the resistance of InAlAs is increased by the addition of F, and the In of F by the sandwiching of layers other than InAlAs
Confinement in AlAs is applied to a channel-doped FET.

FIG. 9 is a sectional view schematically showing the structure of this channel-doped FET. This channel dope FET
Is F-doped InAl on the Fe-doped InP substrate 81.
An As buffer layer 82, a Si-doped n-type InGaAs electron transit layer 83, and an F-doped InAlAs Schottky contact layer 84 are sequentially stacked.

A plurality of Si-doped n-type InGs are formed on the F-doped InAlAs Schottky contact layer 84.
The aAs ohmic contact layer 85 is selectively formed, and the drain electrode 86 or the source electrode 87 is individually formed on each Si-doped n-type InGaAs ohmic contact layer 85.

In the F-doped InAlAs Schottky contact layer 84, the gate electrode 88 is formed on the region sandwiched by the Si-doped n-type InGaAs ohmic contact layers 85.

Even with such a structure, the resistance of the buffer layer 82 and the Schottky contact layer 84 can be increased, as in the fifth embodiment. (Seventh Embodiment) Next, a HEMT structure according to a seventh embodiment of the present invention will be described.

In this embodiment, the addition of B prevents the inactivation of the donor due to the incorporation of F, and makes the electron supply layer stable n-type. FIG. 10 is a sectional view schematically showing this HEMT structure. This HEMT structure is Fe
On the doped semi-insulating InP substrate 91, an undoped InP buffer layer 92 with a thickness of 300 nm, an undoped InGaAs electron transit layer 93 with a thickness of 20 nm, an undoped InAlAs spacer layer 94 with a thickness of 3 nm, and an Si / B-doped n-type InAlAs electron supply with a thickness of 20 nm. Layer 95, 20 nm thick undoped InAlAs Schottky contact layer 96,
A 20 nm thick Si-doped n-type InGaAs ohmic contact layer 97 is sequentially formed.

Here, Si / B-doped n-type InAlAs
The electron supply layer 95 has a B concentration of 5 × 10 ¹⁸ cm ⁻³ . n-type InGaAs ohmic contact layer 97
Has a donor concentration of 5 × 10 ¹⁸ cm ⁻³ .

Next, the manufacturing method and operation of such a HEMT structure will be described. The crystal growth of each layer is as described above.
MOC under conditions of growth temperature of 650 ° C and growth pressure of 70 torr
The VD method is performed so as to be lattice-matched on the InP substrate. Trimethyl indium (C
H ₃ ) ₃ In, trimethylgallium (CH ₃ ) ₃ Ga,
Trimethyl aluminum (CH ₃ ) ₃ Al, arsine A
sH ₃ and phosphine PH ₃ are used, triethylboron is used as the B dopant, and disilane Si ₂ H ₆ is used as the Si dopant.

Specifically, on the Fe-doped semi-insulating InP substrate 91, an undoped InP buffer layer 92, an undoped InGaAs electron transit layer 93, and an undoped InAl.
As spacer layer 94, Si / B-doped n-type InAlAs
An electron supply layer 95, an undoped InAlAs Schottky contact layer 96, and a Si-doped n-type InGaAs ohmic contact layer 97 are sequentially formed.

According to such a structure, since B is added to the Si.B-doped n-type InAlAs electron supply layer 95 even if F is mixed in during the process, B is bonded to F, so that The carrier compensation due to F can be reduced, so that the n-type layer can be stably realized even if a process involving heat treatment is used.

Next, the influence of the heat treatment was examined for the HEMT structure according to this embodiment and the conventional HEMT structure. It should be noted that the conventional HEMT structure has a structure in which B is not added.
It is provided with an nAlAs electron supply layer.

Here, for both HEMT structures, the ohmic contact layer was removed by etching, heat treatment was performed at 280 ° C. for 10 minutes in a nitrogen atmosphere, and the sheet carrier concentration before and after the heat treatment was examined by hole measurement.

As a result, in the HEMT structure of this embodiment, the sheet carrier concentration after the heat treatment was reduced by 5% as compared with that before the heat treatment. On the other hand, in the conventional HEMT structure, the sheet carrier concentration after the heat treatment was reduced by 30% as compared with that before the heat treatment. That is, the HEMT structure of the present embodiment was significantly less affected by the heat treatment.

Further, there was no significant difference in the sheet electron concentration and the mobility before the heat treatment between the HEMT structure of this embodiment and the conventional HEMT structure. Also, both HEMTs
A HEMT was manufactured using the structure and the gate breakdown voltage was examined, but no significant difference was observed. Therefore, the Si / B-doped InAlAs electron supply layer according to the present embodiment has substantially the same electrical characteristics and E as the conventional B-undoped InAlAs electron supply layer.
It is considered to have physical properties such as g and ΦB. (Other Embodiments) In the first embodiment, Si
Although the case where the inactivation of CF _{4 is performed in the} step of exposing to HF vapor has been described, the present invention is not limited to this, and CF ₄ may be used instead of HF vapor.
By exposing to gas plasma and oxygen plasma, F, O
Even if the configuration is diffused and replaced, the same effects can be obtained by implementing the present invention in the same manner.

In the second embodiment, the case where Si is inactivated in the step of exposing it to oxygen plasma has been described, but the present invention is not limited to this, and CF is used instead of oxygen plasma.
Even if the composition is such that F and O are diffused and replaced by exposing to _4- gas plasma and HF vapor, the same effects can be obtained by carrying out the present invention in the same manner.

Furthermore, in the first to third embodiments,
Although the case where the present invention is applied to the FET or the HBT has been described, the present invention is not limited to this, and may be applied to the formation of a current constriction layer of a laser diode or a general element isolation means, and the same embodiment of the present invention can be performed to achieve the same effect. The effect can be obtained.

Further, in the first to third embodiments, I
Although the case of applying to nAlGaAs has been described, the present invention is not limited to this, and GaAs, AlGaAs, InGaP, InA.
Even if the present invention is applied to other III-V group compound semiconductors such as IP, the same effects can be obtained by carrying out the present invention in the same manner.

Further, in the fourth embodiment, the case where F is added to all the InAlAs layers other than the electron supply layer has been described, but the present invention is not limited to this, and the buffer layer and the shot layer may be used depending on the application of the device. Even if the F-doped InAlAs is used for any one or two of the key contact layer and the spacer layer, the same effects can be obtained by carrying out the present invention in the same manner. In this case, the F diffusion preventing layer is appropriately provided so as to be adjacent to the F-doped InAlAs.

In the first to seventh embodiments, I
Although the case of applying to nAlAs has been described, the present invention is not limited to this, and InAlP, InAlSb, InAlAsP, InAl containing P and Sb in the V group instead of InAlAs.
InAlGaAs, InAlGaP, InAlGa containing Ga in the group III may be applied.
You may apply to Sb etc.

Furthermore, in the first to seventh embodiments,
Although the case where the device is manufactured using the MOCVD method has been described, the present invention is not limited to this, and the present invention can be applied even if the device is manufactured using another thin film growth method such as the MBE method (molecular beam epitaxy method). The same effect can be obtained by carrying out similarly.

In the first to seventh embodiments, n
Although the case where Si is used as the type dopant has been described, the present invention is not limited to this, and the same effects can be obtained by implementing the present invention in the same manner even if the composition uses Se, S, Sn, or the like as the n-type dopant. . In addition, the present invention can be modified in various ways without departing from the scope of the invention.

[0099]

As described above, according to the invention of claim 1, the donor element having a concentration of Nd at the shallow donor level and the acceptor element having a concentration of Na at the shallow acceptor level are Nd>
An inactivating element exists by adding an inactivating element for inactivating a donor element having a shallow donor level to a semiconductor layer having a relationship of Na and being almost uniformly distributed. Since the region is inverted to the p-type region, it is possible to provide a semiconductor device capable of improving the controllability of conductivity type and resistivity.

According to the second aspect of the invention, the donor element having a concentration of Nd at the shallow donor level and the acceptor element having a concentration of Nda at the deep acceptor level have a relationship of Nd> Nda and are substantially uniform. By adding an inactivating element for inactivating the donor element having a shallow donor level to the distributed semiconductor layer, the area where the inactivating element exists is more than the other area in the semiconductor layer. Also increases the resistance,
It is possible to provide a semiconductor device having a high resistance semiconductor layer having an extremely low residual carrier concentration.

Further, according to the invention of claim 3, since B is contained in the III-V group compound semiconductor crystal containing In and Al, B is bonded to F, whereby carrier compensation by F is performed. It is possible to provide a semiconductor device that can prevent the above.

[Brief description of drawings]

FIG. 1 is a sectional view for schematically explaining the principle of the present invention.

FIG. 2 is a diagram showing a correspondence relationship between the degree of carrier inactivation by fluorine and the doping concentration of boron according to the present invention.

FIG. 3 is a cross-sectional view schematically showing the structure of the FET according to the first embodiment of the present invention.

FIG. 4 is a process cross-sectional view for explaining the method for manufacturing the FET in the same embodiment.

FIG. 5 is a sectional view schematically showing the configuration of an HBT according to a third embodiment of the present invention.

6A to 6C are process cross-sectional views for explaining the method for manufacturing the HEMT according to the same embodiment.

FIG. 7 is an InP-based HE according to a fourth embodiment of the present invention.
Sectional drawing which shows the structure of MT typically.

FIG. 8 is an InP-based HE according to a fifth embodiment of the present invention.
Sectional drawing which shows the structure of MT typically.

FIG. 9 is a sectional view schematically showing the structure of a channel-doped FET according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view schematically showing a HEMT structure according to a seventh embodiment of the present invention.

FIG. 11 is a sectional view schematically showing the configuration of a conventional InP HEMT.

[Explanation of symbols]

21, 41, 61, 81, 91 ... Fe-doped semi-insulating property I
nP substrate. 22, 92 ... InP buffer layer. 23, 63, 83, 93 ... i-type InGaAs electron transit layer. 24, 66 ... n + type InAlAs electron supply layer. 25 ... i-type InGaP layer. 26 ... n-type InAlAs layer. 27, 69, 85, 97 ... n + type InGaAs ohmic contact layer. 28, 70, 86 ... Drain electrodes. 29, 71, 87 ... Source electrodes. 30 ... High resistance region. 31, 72, 88 ... Gate electrodes. 32, 52 ... Resist. 42 ... n + type InGaAs collector contact layer. 43 ... Collector electrode. 44 ... n-type InGaAs collector layer. 45 ... p + type InGaAs base layer. 46 ... Base electrode. 47 ... n-type InAlAs emitter layer. 47a ... Shallow area. 48 ... Si-doped n-type InAlAs emitter layer. 49 ... n + type InAlAs emitter contact layer. 50 ... Emitter electrode. 51 ... SiO ₂ film. 53 ... Insulation area. 62, 82 ... F-doped InAlAs buffer layer. 64 ... F-doped InAlAs spacer layer. 64 ^* , 94 ... Undoped InAlAs spacer layer. 65 ... Undoped InP hole barrier layer and F diffusion preventing layer. 67 ... Undoped InAlGaAs layer and F diffusion prevention layer. 68, 84 ... F-doped InAlAs Schottky contact layer. 68 ^* , 96 ... Undoped InAlAs Schottky contact layer. 95 ... Si.B-doped n-type InAlAs electron supply layer.

Front page continuation (72) Inventor Yasuo Ashizawa, No. 1, Komukai Toshiba-cho, Sachi-ku, Kawasaki City, Kanagawa Prefecture

Claims (3)

[Claims] 1. A donor element having a concentration of Nd at a shallow donor level and an acceptor element having a concentration of Na at a shallow acceptor level are substantially uniformly distributed in a relationship of Nd> Na, and the shallow donor level is provided. A semiconductor device comprising a semiconductor layer containing an inactivating element for inactivating the donor element of, wherein the inactivating element is any one element of hydrogen, fluorine, oxygen and chlorine. A semiconductor device in which the region where the passivation element is present is a p-type region. 2. A donor element having a concentration of Nd at a shallow donor level and an acceptor element having a concentration of Nda at a deep acceptor level are substantially uniformly distributed with a relationship of Nd> Nda,
A semiconductor device comprising a semiconductor layer containing an inactivating element for inactivating a donor element of the shallow donor level, wherein the inactivating element is any one of hydrogen, fluorine, oxygen and chlorine. A semiconductor device, which is a kind of element and has a region in which the passivation element is present has a higher resistance than other regions in the semiconductor layer. 3. A semiconductor device comprising a III-V group compound semiconductor layer containing at least indium and aluminum, wherein the compound semiconductor layer has a concentration of 0.5% or less with respect to its own group III element concentration. A semiconductor device containing boron in a ratio of.