JP2010199568A - Method for manufacturing semiconductor substrate, and semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control p-type carrier concentration of a group III-V compound semiconductor while reducing usage of a group V raw material. <P>SOLUTION: The method includes the steps of: installing a base wafer in a reaction vessel; and epitaxially growing a group III-V compound semiconductor on the base wafer while supplying an impurity gas including a group III raw material composed of a p-type group III organic metal compound, a group V raw material composed of a group V element, and impurities which are doped in a semiconductor to be donors. In the step of epitaxially growing the p-type group III-V compound semiconductor on the base wafer, flow rate of the impurity gas and flow rate ratio of the group V raw material to the group III raw material are set so that a product of N×d (cm<SP>-2</SP>) of the residual carrier concentration N (cm<SP>-3</SP>) and the thickness d (cm) of the p-type group III-V compound semiconductor is equal to or smaller than 8.0×10<SP>11</SP>. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate manufacturing method and a semiconductor substrate.

  In recent years, field effect transistors (referred to as FETs), high electron mobility transistors (referred to as HEMTs), and heterojunction bipolar transistors (referred to as HBTs) using Group 3-5 compound semiconductors such as GaAs, AlGaAs, and InGaAs. ) Etc. are manufactured. A compound semiconductor epitaxial substrate is used for manufacturing these electronic devices. The compound semiconductor epitaxial substrate is manufactured by growing a crystal of a group 3-5 compound semiconductor on a semi-insulating substrate such as a GaAs substrate by an epitaxial growth method. As the epitaxial growth method, a liquid phase method, a molecular beam epitaxial growth method, a metal organic chemical vapor deposition method (referred to as MOCVD method), or the like is used.

  Patent Document 1 describes a compound semiconductor epitaxial wafer having an AlGaAs buffer layer between a semi-insulating GaAs substrate and an n-type GaAs active layer. The buffer layer suppresses a leakage current that degrades the characteristics of the FET. The buffer layer also reduces the influence of the substrate or impurities on the substrate on the FET characteristics. The buffer layer of Patent Document 1 is formed by metal organic vapor phase epitaxy (referred to as MOVPE method), and donor impurities and acceptor impurities having close concentrations are added.

Patent Document 2 describes a Group 3-5 compound semiconductor device having a p-type buffer layer formed by the MOVPE method. In Patent Document 2, paying attention to the relationship between the film thickness in the p-type buffer layer and the p-type carrier concentration, the product of the film thickness and the p-type carrier concentration is set to 1 × 10 ¹⁰ to 1 × 10 ¹² cm ^{−. By} setting it to ² , the leakage current of the group 3-5 compound semiconductor device is reduced.
Patent Document 1 Japanese Patent Laid-Open No. 11-345812 Patent Document 2 Japanese Patent Laid-Open No. 2007-67359

  Patent Document 1 does not describe the crystal growth conditions of the buffer layer. Usually, when a Group 3-5 compound semiconductor is formed using the MOVPE method or the MOCVD method, a Group 5 such as P and As is used. The raw material is supplied in a very excessive amount as compared with Group 3 raw materials such as Al, Ga, and In. As a result, the manufacturing cost of the compound semiconductor epitaxial wafer increases. In Patent Document 2, the p-type carrier concentration of the p-type buffer layer when oxygen or a transition metal is doped is controlled. However, Patent Document 2 does not consider the supply amount of the Group 5 raw material.

  In order to reduce the manufacturing cost, it is preferable to reduce the supply amount of the Group 5 raw material. However, if the supply amount of the Group 5 raw material is simply reduced for the purpose of reducing the manufacturing cost, the p-type carrier concentration of the Group 3-5 compound semiconductor becomes too large. As a result, excess acceptor impurities that can no longer be ionized remain, and the Group 3-5 compound semiconductor cannot exhibit sufficient performance as a buffer layer.

  Specifically, in the MOVPE method or the MOCVD method, the Group 3 raw material is supplied as an organometallic compound such as trimethyl gallium and trimethyl aluminum. Carbon contained in the organometallic compound is taken into the crystal of the compound semiconductor during crystal growth. The carbon concentration of the Group 3-5 compound semiconductor increases as the ratio of the Group 5 material to the Group 3 material during crystal growth decreases. Since carbon behaves as an acceptor impurity in the crystal of the group 3-5 compound semiconductor, the p-type carrier concentration of the group 3-5 compound semiconductor increases as the carbon concentration increases. As a result, the group 3-5 compound semiconductor cannot exhibit sufficient performance as a buffer layer.

  More specifically, if p-type carriers remain in the group 3-5 compound semiconductor, the residual capacity of the group 3-5 compound semiconductor increases, and thus the leakage current of the group 3-5 compound semiconductor increases. As a result, the breakdown voltage of the group 3-5 compound semiconductor is lowered. In addition, carrier mobility in a semiconductor device such as an FET formed in a Group 3-5 compound semiconductor is lowered.

  In order to prevent excessive acceptor impurities from being ionized and prevent the Group 3-5 compound semiconductor from exhibiting sufficient performance as a buffer layer, the Group 3-5 compound semiconductor is reduced while the supply amount of the Group 5 material is reduced. It is preferable to maintain the p-type carrier concentration at an appropriate value. Accordingly, an object of the present invention is to provide a method for producing a Group 3-5 compound semiconductor capable of reducing the amount of Group 5 raw material used without impairing the physical properties of the Group 3-5 compound semiconductor.

In order to solve the above-mentioned problems, in the first aspect of the present invention, a step of placing a base substrate inside a reaction vessel, and the reaction vessel comprising a group 3 element organometallic compound 3 Supplying a group 5 source gas consisting of a group 5 source gas and an impurity gas containing an impurity which is doped into the semiconductor and becomes a donor to epitaxially grow a p-type group 3-5 compound semiconductor on the base substrate And in the step of epitaxially growing the p-type group 3-5 compound semiconductor on the base substrate, the flow rate of the impurity gas and the flow rate ratio of the group 5 source gas to the group 3 source gas are set to be those of the p-type group 3-5 compound semiconductor. Provided is a method for manufacturing a semiconductor substrate, wherein a product N × d (cm ⁻² ) of a residual carrier concentration N (cm ⁻³ ) and a thickness d (cm) is set to 8.0 × 10 ¹¹ or less. Is done. Here, the “p-type group 3-5 compound semiconductor” is a group 3-5 compound semiconductor in which the p-type carrier concentration is higher than the n-type carrier concentration.

In the step of epitaxially growing the p-type group 3-5 compound semiconductor on the base substrate, the residual capacity per unit area is 0.5 nF by capacitance voltage measurement using a Schottky electrode in contact with the active layer on the p-type group 3-5 compound semiconductor. The flow rate of the impurity gas and the flow rate ratio of the Group 5 source gas to the Group 3 source gas may be set so as to be less than / cm ² .

Moreover, it is preferable to set the flow ratio of the Group 5 source gas to the Group 3 source gas to 50 or less. Furthermore, the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the flow rate of the impurity gas is preferably 9.0 × 10 ⁶ or less. In the method for manufacturing a compound semiconductor epitaxial substrate, the impurity may include at least one element selected from the element group consisting of Si, Se, Ge, Sn, S, and Te. In the manufacture of the compound semiconductor epitaxial substrate, a p-type group 3-5 compound semiconductor and an active layer may be stacked in this order on the base substrate.

In the second aspect of the present invention, the base substrate and the base substrate are doped into a group 3 source gas composed of an organometallic compound of a group 3 element, a group 5 source gas composed of a group 5 element, and a semiconductor. A p-type group 3-5 compound semiconductor epitaxially grown by supplying an impurity gas containing an impurity serving as a donor, and the p-type group 3-5 compound semiconductor has a residual carrier concentration N (cm ⁻³ ) and a thickness. A semiconductor substrate having a product d × cm (N × d (cm ⁻² )) of 8.0 × 10 ¹¹ or less is provided.

In the above semiconductor substrate, the residual capacity per unit area is preferably less than 0.5 nF / cm ² in the capacity voltage measurement using the Schottky electrode in contact with the active layer on the p-type group 3-5 compound semiconductor. In the above semiconductor substrate, the p-type group 3-5 compound semiconductor is epitaxially grown with the ratio of the flow rate difference between the group 5 source gas and the group 3 source gas to the impurity gas flow rate being 9.0 × 10 ⁶ or less. Preferably it is.

  In the above semiconductor substrate, it is preferable that the p-type group 3-5 compound semiconductor is epitaxially grown under the condition that the ratio of the group 5 source gas to the group 3 source gas is 50 or less. In the semiconductor substrate, the donor impurity may include at least one element selected from the element group consisting of Si, Se, Ge, Sn, S, and Te. In the above semiconductor substrate, a p-type group 3-5 compound semiconductor and an active layer may be stacked in this order on the base substrate.

An example of the section of compound semiconductor epitaxial substrate 100 is shown roughly. An example of the manufacturing method of the compound semiconductor epitaxial substrate 100 is shown roughly. An example of a section of semiconductor device 300 is shown roughly. An example of the section of compound semiconductor epitaxial substrate 400 is shown roughly. An example of the section of compound semiconductor epitaxial substrate 500 is shown roughly. An example of a section of semiconductor device 600 is shown roughly. The result of the capacitance voltage measurement in the compound semiconductor epitaxial substrate of Example 1 is shown. The result of the capacitance voltage measurement in the compound semiconductor epitaxial substrate of Example 1 is shown. The result of the capacitance voltage measurement in the compound semiconductor epitaxial substrate of the comparative example 2 is shown. The result of the capacitance voltage measurement in the compound semiconductor epitaxial substrate of the comparative example 2 is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Hereinafter, embodiments will be described with reference to the drawings. In the description of the drawings, the same or similar parts may be denoted by the same reference numerals, and redundant description may be omitted. The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio, and the like may be different from the actual ones. In addition, for convenience of explanation, there may be a case where the drawings have different dimensional relationships or ratios.

FIG. 1 schematically shows an example of a cross section of a compound semiconductor epitaxial substrate 100 according to an embodiment. As shown in FIG. 1, the compound semiconductor epitaxial substrate 100 includes a base substrate 102 and a group 3-5 compound semiconductor 104. The compound semiconductor epitaxial substrate 100 is an example of a semiconductor substrate. The base substrate 102 includes, for example, a Group 3-5 compound semiconductor such as GaAs or a Group 4 semiconductor represented by Si _x Ge _1-x (0 ≦ x ≦ 1).

  The group 3-5 compound semiconductor 104 is a p-type group 3-5 compound semiconductor. The Group 3-5 compound semiconductor 104 is formed by, for example, the MOCVD method. The Group 3-5 compound semiconductor 104 has a thickness of 10 nm to 3000 nm, for example. The group 3-5 compound semiconductor 104 may have a plurality of layers.

  The group 3-5 compound semiconductor 104 is supplied with a group 3 source gas composed of an organometallic compound of a group 3 element, a group 5 source gas composed of a group 5 element, and an impurity gas containing an impurity serving as a donor on one side of the base substrate 102. The main surface 103 is supplied, and a group 3-5 compound semiconductor is crystal-grown on the main surface 103. The impurity is doped into the group 3-5 compound semiconductor and acts as a donor, so that the n-type carrier concentration of the group 3-5 compound semiconductor 104 is increased.

  The smaller the ratio of the Group 5 source to the Group 3 source during crystal growth, the greater the carbon concentration of the Group 3-5 compound semiconductor, and the p-type carrier concentration in the Group 3-5 compound semiconductor 104 increases. However, when the n-type carrier concentration of the group 3-5 compound semiconductor 104 increases due to impurities acting as donors, the p-type carriers are compensated by the increased n-type carriers. As a result, since the residual p-type carrier concentration in the group 3-5 compound semiconductor 104 is reduced, the group 3-5 compound semiconductor 104 exhibits sufficient performance as a buffer layer.

  Specifically, when the p-type carrier of the group 3-5 compound semiconductor 104 decreases, the residual capacity of the group 3-5 compound semiconductor 104 decreases, and thus the leakage current of the group 3-5 compound semiconductor 104 decreases. As a result, the breakdown voltage of the group 3-5 compound semiconductor 104 is improved. In addition, carrier mobility in a semiconductor device such as an FET formed in the group 3-5 compound semiconductor 104 is increased. That is, as the residual p-type carrier concentration of the group 3-5 compound semiconductor 104 is reduced, the group 3-5 compound semiconductor 104 has a high breakdown voltage and serves as a buffer layer suitable for forming a semiconductor device having high mobility. Function.

  The “residual p-type carrier concentration” is the carrier concentration of the Group 3-5 compound semiconductor 104 when the p-type carrier concentration is higher than the n-type carrier concentration. Similarly, the carrier concentration when the p-type carrier concentration is smaller than the n-type carrier concentration is referred to as a residual n-type carrier concentration. As described above, the amount of the Group 5 source material used for manufacturing the Group 3-5 compound semiconductor 104 is reduced by supplying the impurity gas containing the impurity serving as a donor together with the Group 3 source gas and the Group 5 source gas. Can do.

  FIG. 2 schematically shows an example of a method for manufacturing the compound semiconductor epitaxial substrate 100 according to an embodiment. As shown in FIG. 2, the base substrate 102 is prepared in S202. In step S <b> 204, the group 3-5 compound semiconductor 104 is epitaxially grown on the main surface 103 of the base substrate 102.

  Specifically, a group 3 source gas containing an organometallic compound of a group 3 element, a group 5 source gas containing a group 5 element, and an impurity gas containing an impurity serving as a donor are supplied to one main surface 103 of the base substrate 102. And a p-type group 3-5 compound semiconductor is crystal-grown on the main surface 103. The amount of the n-type carrier that compensates for the p-type carrier of the Group 3-5 compound semiconductor varies depending on the flow rate of the impurity gas supplied together with the Group 3 source gas and the Group 5 source gas. Therefore, the residual p-type carrier concentration can be set to an appropriate value by controlling the flow rate of the impurity gas according to the flow rate ratio of the flow rate of the Group 5 source gas to the flow rate of the Group 3 source gas.

  Here, in this specification, “the flow rate of the Group 3 source gas” represents the volume flow rate of the Group 3 source gas. “The flow rate of the Group 5 source gas” represents the volume flow rate of the Group 5 source gas. The “impurity gas flow rate” represents the volume flow rate of the impurity gas. The “flow ratio of the Group 5 source gas to the group 3 source gas” represents a value obtained by dividing the “group 5 source gas flow rate” by the “group 3 source gas flow rate”. The flow rate ratio is calculated in terms of “flow rate ratio of Group 5 source gas to group 3 source gas flow rate” at 0 ° C. and 101.3 kPa (1 atm).

  The group 3 source gas is a source gas composed of an organometallic compound of a group 3 element. As an example, the Group 3 source gas is supplied into the reaction vessel together with the carrier gas. The group 3 source gas includes, for example, an organometallic compound having an alkyl group such as trimethylgallium (referred to as TMG), trimethylaluminum (referred to as TMA), trimethylindium (referred to as TMI), or the like. Carbon number of the said alkyl group is 1-3, for example.

The group 3 source gas can be supplied as follows. First, a raw material container containing an organometallic compound is placed in a thermostatic bath, and the temperature is adjusted so that the organometallic compound reaches a predetermined temperature. Next, a carrier gas such as H _{2 is} introduced into the raw material container to bubble the organometallic compound. Thereby, the organometallic compound is vaporized. The carrier gas flowing out from the raw material container contains an amount of the organometallic compound according to the saturated vapor pressure of the organometallic compound at the temperature of the thermostat and the pressure in the raw material container.

  When the Group 3 source gas is supplied to the reaction container together with the carrier gas, the flow rate of the Group 3 source gas is based on the flow rate of the carrier gas supplied to the source container, and the constant temperature bath in which the source container is installed. It can be calculated using the saturated vapor pressure of the organometallic compound at the temperature and the pressure in the raw material container. When a plurality of organometallic compounds are used as the Group 3 raw material, the “flow rate of the Group 3 source gas” represents a value obtained by summing the flow rates of the plurality of organometallic compounds. For example, when a compound semiconductor is formed using a first group 3 source gas containing TMA and a second group 3 source gas containing TMG as the group 3 source gas, the "group 3 source gas flow rate" This is the sum of the flow rate of the first group 3 source gas and the flow rate of the second group 3 source gas.

  The group 5 source gas is a source gas made of a compound containing a group 5 element. As an example, the Group 5 source gas is supplied into the reaction vessel together with the carrier gas. The group 5 source gas contains a hydride of a group 5 element such as arsine. The carbon contained in the organometallic compound of the Group 5 element is less likely to be incorporated into the crystal of the Group 3-5 compound semiconductor 104 as compared to the carbon contained in the organometallic compound of the Group 3 element. Therefore, the group 5 source gas may contain an organometallic compound of a group 5 element such as monoalkylarsine. The organometallic compound of Group 5 element is, for example, an organometallic compound in which at least one hydrogen of a hydride of Group 5 element is substituted with an alkyl group having 1 to 4 carbon atoms.

  The group 5 source gas is supplied in the same manner as the group 3 source gas. Further, the flow rate of the group 5 source gas is calculated in the same manner as the flow rate of the group 3 source gas. When a plurality of Group 5 element compounds are used, the flow rate of the Group 5 source gas is calculated by summing the flow rates of the plurality of Group 5 element compounds.

  The impurity gas contains an impurity serving as a donor. The impurity gas may include a carrier gas. The impurity serving as a donor is, for example, at least one element selected from the element group consisting of Si, Se, Ge, Sn, S, and Te. The impurity gas may include a hydride having the above element or an alkylate having the above element and an alkyl group having 1 to 3 carbon atoms.

  Since the impurity behaves as a donor impurity in the crystal of the group 3-5 compound semiconductor 104, the n-type carrier concentration of the group 3-5 compound semiconductor 104 is increased. When the flow rate ratio of the group 5 source gas to the group 3 source gas is set to a low value of 50 or less, the carbon contained in the group 3 source gas is taken into the crystal of the group 3-5 compound semiconductor 104, and is p-type. Carrier concentration increases. However, by supplying the impurity gas together with the group 3 source gas and the group 5 source gas, the p-type carrier is compensated for by the n-type carrier, so that an increase in the residual p-type carrier concentration can be suppressed.

  Further, by adjusting the flow rate of the Group 3 source gas, the flow rate of the Group 5 source gas, and the flow rate of the impurity gas, the concentrations of the acceptor impurity and the donor impurity in the Group 3-5 compound semiconductor 104 can be controlled. Therefore, the residual p-type carrier concentration of the group 3-5 compound semiconductor 104 can be controlled while reducing the amount of the group 5 material used.

Specifically, in the stage of epitaxially growing the Group 3-5 compound semiconductor 104 on the base substrate 102, the flow rate of the impurity gas and the flow rate ratio of the Group 5 source gas to the Group 3 source gas are set to be those of the Group 3-5 compound semiconductor 104. The product N × d (cm ⁻² ) of the residual carrier concentration N (cm ⁻³ ) and the thickness d (cm) is set to 8.0 × 10 ¹¹ or less. With this setting, p-type carriers generated according to the flow rate ratio of the Group 5 source gas to the Group 3 source gas are compensated by the impurity gas. As a result, the group 3-5 compound semiconductor 104 having sufficient performance as a buffer layer can be crystal-grown while reducing the amount of group 5 raw material used.

  In this specification, “residual carrier concentration of group 3-5 compound semiconductor 104” means a value obtained by subtracting n-type carrier concentration from p-type carrier concentration. The carrier concentration can be calculated from the capacitance-voltage characteristics (referred to as CV characteristics) of the group 3-5 compound semiconductor 104. “Thickness of the group 3-5 compound semiconductor 104” indicates an average film thickness of a region suitable for a buffer layer of a semiconductor device such as an FET. The average film thickness is, for example, an arithmetic average of film thicknesses at five points in the above region. The film thickness can be calculated by observation using SEM or TEM.

In order to reduce the flow rate of the Group 5 source gas, it is preferable to supply the Group 3 source gas and the Group 5 source gas so that the flow rate ratio of the Group 5 source gas to the Group 3 source gas is 50 or less. That is, the flow rate ratio of the group 5 source gas to the group 3 source gas is 50 or less, and the film thickness of the group 3-5 compound semiconductor 104 is multiplied by the carrier concentration of the group 3-5 compound semiconductor 104. It may be set to be 8.0 × 10 ¹¹ cm ⁻² or less. Crystal growth of the Group 3-5 compound semiconductor 104 under the above conditions greatly reduces the amount of Group 5 source gas used while controlling the concentration of acceptor impurities and donor impurities in the Group 3-5 compound semiconductor 104 can do.

  If the flow rate ratio of the Group 5 source gas to the Group 3 source gas is set to 30 or less, the group 5 source gas flow rate can be further reduced. Therefore, it is more preferable to set the flow rate ratio to 30 or less. In addition, since the group 3 source gas and the group 5 source gas are required for crystal growth of the group 3-5 compound semiconductor 104, the flow rate ratio of the group 5 source gas to the group 3 source gas is 0.1 or more. Preferably there is.

In the stage of epitaxially growing the Group 3-5 compound semiconductor 104 on the base substrate 102, the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the flow rate of the impurity gas is set to 9.0 × 10 ⁶ or less. Is preferred. The ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the impurity gas flow rate may be 8.4 × 10 ⁶ or less. Crystal growth of the Group 3-5 compound semiconductor 104 having sufficient performance as a buffer layer is performed by setting the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the impurity gas flow rate to the value. Can do.

  Here, “the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the flow rate of the impurity gas” is the “difference between the flow rate of the Group 5 source gas and the group 3 source gas” The value divided by "flow rate". Further, the above ratio is calculated in terms of “the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the flow rate of the impurity gas” at 0 ° C. and 101.3 kPa (1 atm). When the impurity gas is diluted with another gas such as hydrogen, the flow rate of the impurity gas is calculated by conversion when the impurity gas concentration is 100%.

  By using “ratio of flow rate difference between Group 5 source gas and Group 3 source gas with respect to the flow rate of impurity gas” as an index indicating the relationship between the flow rates of impurity gas, Group 5 source gas, and Group 3 source gas, It becomes easy to grasp the relationship between the p-type carrier concentration caused by the flow rate ratio and the flow rate difference between the group 5 source gas and the group 3 source gas and the n-type carrier concentration caused by the impurity gas. In addition, given the value of “the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the flow rate of the impurity gas”, either of the impurity gas, the Group 5 source gas, and the Group 3 source gas By determining the flow rate, the flow rates of other gases can be uniquely determined.

  In the present embodiment, the case of controlling the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas with respect to the impurity gas flow rate has been described. Further, the growth temperature, pressure, crystal growth rate, etc. of the reaction vessel are controlled. May be. The growth temperature of the reaction vessel at the time of crystal growth is preferably selected in a temperature range where the raw material supply rate is controlled so that the reaction decomposition rate of the raw material does not change even if the growth temperature changes. For example, the growth temperature can be selected according to the carrier concentration of the n-GaAs layer that is a Group 3-5 compound semiconductor.

  The growth pressure during crystal growth is set based on the relationship between the in-plane uniformity of the 3-5 group compound semiconductor 104 to be grown and the raw material efficiency. Specifically, the lower the growth pressure, the better the in-plane uniformity, but the lower the raw material efficiency. Therefore, an optimal growth pressure that balances these two factors is set. Furthermore, the crystal growth rate of the Group 3-5 compound semiconductor 104 is determined by the flow rate of the Group 3 source gas under the condition of source supply rate-limiting. For example, the crystal growth rate is near the center of the control range of a gas flow meter installed in the growth apparatus, and a growth rate condition is set at a flow rate with good linearity between the gas flow rate and the growth rate.

  FIG. 3 schematically illustrates an example of a cross section of a semiconductor device 300 according to an embodiment. The semiconductor device 300 includes a base substrate 102, a group 3-5 compound semiconductor 104, and an active layer 310 in this order. The group 3-5 compound semiconductor 104 can be formed in the same manner as the compound semiconductor epitaxial substrate 100. The active layer 310 is, for example, a group 3-5 compound semiconductor.

  FIG. 4 schematically shows an example of a cross section of a compound semiconductor epitaxial substrate 400 according to another embodiment. The compound semiconductor epitaxial substrate 400 includes a base substrate 102, a group 3-5 compound semiconductor 104, an active layer 310, and a contact layer 420 in this order. The compound semiconductor epitaxial substrate 400 is an example of a semiconductor substrate.

The base substrate 102 includes, for example, a Group 3-5 compound semiconductor such as GaAs or a Group 4 semiconductor represented by Si _x Ge _1-x (0 ≦ x ≦ 1). The base substrate 102 may be a semi-insulating GaAs substrate. In the base substrate 102, the crystallographic plane orientation of the surface of the base substrate 102 is tilted from the crystallographic plane orientation of one (100) plane or a plane equivalent to the (100) plane, and the magnitude of the tilt. May be a semi-insulating single-crystal GaAs substrate having an angle of 0.05 ° to 1 °. The base substrate 102 is a laminated substrate in which a Group 3-5 compound semiconductor such as GaAs is formed on an Si substrate, an SOI (silicon-on-insulator) substrate, a Ge substrate, or a GOI (germanium-on-insulator) substrate. Also good.

  For example, the Group 3-5 compound semiconductor 104 supplies a group 3 source gas, a group 5 source gas, and an impurity gas to a reduced pressure barrel type reaction vessel in which the base substrate 102 is installed. It is obtained by growing a group 3-5 compound semiconductor on the surface 103. At this time, by supplying the group 3 source gas and the group 5 source gas so that the flow rate ratio of the group 5 source gas to the group 3 source gas is 50 or less, more preferably 30 or less, The p-type carrier concentration of the group 3-5 compound semiconductor 104 can be controlled while reducing the amount used. In addition to the Group 3 source gas, the Group 5 source gas, and the impurity gas, a carrier gas, a balance gas, and other source gases may be supplied to the reaction vessel.

The flow rate of the impurity gas and the flow rate ratio of the Group 5 source gas to the Group 3 source gas are determined by the residual capacity per unit area caused by the residual charge in the capacitance voltage measurement using the Schottky electrode of the compound semiconductor epitaxial substrate 400. It is preferably set to be less than 0.5 nF / cm ² . The flow rate of the impurity gas and the flow rate ratio of the Group 5 source gas to the Group 3 source gas is such that the flow rate ratio of the Group 5 source gas to the Group 3 source gas is 50 or less, and the Group 3-5 compound semiconductor 104 A unit obtained by multiplying the film thickness by the carrier concentration of the Group 3-5 compound semiconductor 104 is 8.0 × 10 ¹¹ cm ⁻² or less, and in the capacitance voltage measurement of the compound semiconductor epitaxial substrate 400, The residual capacity per area may be set to be less than 0.5 nF / cm ² .

  The capacitance voltage measurement of the Group 3-5 compound semiconductor 104 is performed by, for example, applying a voltage to a Schottky electrode in contact with the active layer 310 formed by removing the contact layer 420 of the compound semiconductor epitaxial substrate 400 by etching or the like. it can. Al, Ag, Au, Cu, or the like can be used as the Schottky electrode. Note that the Schottky electrode is not shown in FIG.

  For example, the Schottky electrode can be formed by forming the inner electrode and the outer electrode surrounding the inner electrode and spaced apart from the inner electrode on the surface of the active layer 310. An opening may be formed inside the outer electrode. The inner electrode is formed, for example, inside the opening. The center of the inner electrode and the center of the outer electrode may substantially coincide. The center of the opening may be substantially coincident with the center of the outer electrode. The center of the opening and the center of the inner electrode may substantially coincide.

The shape of the inner electrode is, for example, a circle. The shape of the opening may be similar to the shape of the inner electrode. The size of the opening is preferably larger than the inner electrode. The area of the outer electrode is preferably 10 times or more, more preferably 1000 times or more the area of the inner electrode. The area of the outer electrode may be 2 cm ² or more. The outer shape of the outer electrode is not particularly limited, and may be similar to the shape of the inner electrode.

  The outwardly extending shape of the outer electrode may be a regular polygon. For example, a circular inner electrode, a circular opening, and a square outer electrode are formed so that their centers coincide. Capacitance voltage measurement can be performed by applying a voltage between the inner electrode and the outer electrode. According to this method, the capacitance value of each material can be calculated using the area value of the inner electrode and the value of the interval between the inner electrode and the outer electrode.

  The active layer 310 includes, for example, a group 3-5 compound semiconductor such as GaAs, AlGaAs, InGaP, and InGaAs. The active layer 310 may have strained InGaAs. The active layer 310 functions as, for example, an FET active layer. The contact layer 420 may include a Group 3-5 compound semiconductor such as GaAs and InGaAs.

  FIG. 5 schematically shows an example of a cross section of a compound semiconductor epitaxial substrate 500 according to yet another embodiment. The compound semiconductor epitaxial substrate 500 includes a base substrate 502, a buffer layer 504, a back side electron supply layer 506, a back side spacer layer 508, a channel layer 510, a front side spacer layer 512, a front side electron supply layer 514, a barrier layer 516, and A contact layer 520 is provided in this order. The compound semiconductor epitaxial substrate 500 is an example of a semiconductor substrate. The buffer layer 504 is formed by crystal growth on one main surface 503 of the base substrate 502. The channel layer 510 is an example of an active layer.

  The base substrate 502 and the base substrate 102 have the same configuration. The buffer layer 504 and the group 3-5 compound semiconductor 104 have the same configuration. The buffer layer 504 may include a plurality of layers. At least some of the plurality of layers in the buffer layer 504 may have a configuration similar to that of the group 3-5 compound semiconductor 104. The buffer layer 504 has a thickness of 10 nm or more and 3000 nm or less, for example. The channel layer 510 and the active layer 310 have the same configuration. Contact layer 520 has a configuration similar to that of contact layer 420. Therefore, description of the base substrate 502, the buffer layer 504, the channel layer 510, and the contact layer 520 is omitted.

  The back side electron supply layer 506 and the front side electron supply layer 514 supply electrons to the channel layer 510. The back side electron supply layer 506 and the front side electron supply layer 514 may include a Group 3-5 compound semiconductor such as AlGaAs. The back side spacer layer 508 and the front side spacer layer 512 may include a compound semiconductor having a wider band gap than that of the compound semiconductor included in the channel layer 510. The barrier layer 516 includes a Group 3-5 compound semiconductor such as AlGaAs. In the barrier layer 516, a gate electrode of an electronic element such as an FET is formed. The contact layer 520 includes a Group 3-5 compound semiconductor such as GaAs or InGaAs.

  The capacitance voltage measurement of the compound semiconductor epitaxial substrate 500 when the capacitance is formed by the buffer layer 504 is performed by, for example, removing the contact layer 520 by etching and applying a voltage to a pair of Schottky electrodes formed on the barrier layer 516. Can be implemented. Al, Ag, Au, Cu, or the like can be used as the Schottky electrode. Note that the Schottky electrode is not shown in FIG.

  FIG. 6 schematically shows an example of a cross section of a semiconductor device 600 according to another embodiment. The semiconductor device 600 is, for example, a HEMT. The semiconductor device 600 includes a base substrate 502, a buffer layer 504, a back side electron supply layer 506, a back side spacer layer 508, a channel layer 510, a front side spacer layer 512, a front side electron supply layer 514, and a barrier layer 516 in this order. Prepare. The semiconductor device 600 includes a contact layer 622 and a contact layer 624 that are in contact with the barrier layer 516, and a control electrode 636. The semiconductor device 600 includes a drain electrode 632 in contact with the contact layer 622 and a source electrode 634 in contact with the contact layer 624.

  For example, the drain electrode 632 and the source electrode 634 form an ohmic junction with the contact layer 622 and the contact layer 624. For example, the contact layer 622 and the contact layer 624 include a Group 3-5 compound semiconductor such as GaAs and InGaAs. The control electrode 636 controls the current flowing through the drain electrode 632 and the source electrode 634. The drain electrode 632, the source electrode 634, and the control electrode 636 may be a semiconductor such as aluminum, copper, gold, silver, platinum, tungsten, other metals, and alloys thereof, or highly doped silicon. .

  For example, the semiconductor device 600 is manufactured by the following procedure. First, the compound semiconductor epitaxial substrate 500 shown in FIG. 5 is prepared. Next, part of the contact layer 520 of the compound semiconductor epitaxial substrate 500 is removed by patterning by etching or the like to form a contact layer 622 and a contact layer 624, and the barrier layer 516 is exposed. Thereafter, the drain electrode 632, the source electrode 634, and the control electrode 636 are formed, whereby the semiconductor device 600 can be manufactured.

  Although the case where the semiconductor device is a HEMT has been described in the present embodiment, the semiconductor device is not limited to a HEMT. The semiconductor device may be a light emitting element, a light receiving element, or a semiconductor circuit as well as an electronic device such as an HBT or FET.

Example 1
The compound semiconductor epitaxial substrate 500 was manufactured by the following procedure. A semi-insulating GaAs single crystal substrate was prepared as the base substrate 502. The prepared GaAs single crystal substrate was placed in a vacuum barrel type MOCVD furnace. Next, p-Al _0.25 Ga _0.75 As having a thickness of 500 nm was formed as the buffer layer 504. For the formation of p-Al _0.25 Ga _0.75 As, TMA as the first group 3 source gas and TMG as the second group 3 source gas were used as the group 3 source gas. A source gas containing arsine (AsH ₃ ) was used as the group 5 source gas. A gas containing disilane (Si ₂ H ₆ ) was used as the impurity gas. The flow rate of the impurity gas was set so that the flow rate of disilane was 6.20 × 10 ⁻⁵ cm ³ / min in terms of 101.3 kPa and 0 ° C. High purity hydrogen was used as a carrier gas.

In the formation of the buffer layer 504, the first Group 3 source gas, the second Group 3 source gas, and the Group 5 source gas are adjusted so that the flow rate ratio of the Group 5 source gas to the group 3 source gas is 30. And supplied to the MOCVD furnace. Specifically, the flow rate of the first Group 3 source gas was set so that the flow rate of TMA was 2.7 cm ³ / min in terms of 101.3 kPa and 0 ° C. The flow rate of the second group 3 source gas was set so that the flow rate of TMG was 10.6 cm ³ / min in terms of 101.3 kPa and 0 ° C. The flow rate of the Group 5 source gas was set so that the flow rate of arsine was 400 cm ³ / min in terms of 101.3 kPa and 0 ° C. As other crystal growth conditions, a condition in which the growth pressure in the MOCVD furnace was 10.13 kPa, the growth temperature was 650 ° C., and the growth rate was 1 to 3 μm / hr was selected.

The flow rate difference between the Group 5 source gas and the Group 3 source gas was 386.7 cm ³ / min. Therefore, the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the flow rate of the impurity gas was 6.24 × 10 ⁶ . Further, the flow rate ratio of the group 5 source gas to the impurity gas flow rate was 6.45 × 10 ⁶ .

Next, n-Al _0.22 Ga _0.78 As having a thickness of 3 nm was formed as the back-side electron supply layer 506. The residual n-type carrier concentration of the back side electron supply layer 506 was 3 × 10 ¹⁸ cm ⁻³ . Next, i-Al _0.22 Ga _0.78 As having a thickness of 3 nm was formed as the back-side spacer layer 508.

Next, a strained InGaAs layer was formed as the channel layer 510. As a strained InGaAs layer, i-In _0.20 Ga _0.80 As having a thickness of 14 nm was formed. As a group 3 source gas of i-In _0.20 Ga _0.80 As, a first group 3 source gas containing TMI and a second group 3 source gas containing TMG were used.

Next, i-Al _0.22 Ga _0.78 As having a thickness of 3 nm was formed as the front spacer layer 512. Next, n-Al _0.22 Ga _0.78 As having a thickness of 9 nm was formed as the front-side electron supply layer 514. The residual n-type carrier concentration of the front-side electron supply layer 514 was 3 × 10 ¹⁸ cm ⁻³ . Finally, i-Al _0.22 Ga _0.78 As having a thickness of 50 nm was formed as the barrier layer 516.

FIG. 7 shows the results of capacitance voltage measurement on the compound semiconductor epitaxial substrate of Example 1. The horizontal axis in FIG. 7 indicates the bias voltage [V]. The vertical axis represents the capacitance [F]. FIG. 8 shows a diagram in which the vertical axis in the result of the capacitive voltage measurement shown in FIG. 7 is converted into a capacitance [F / cm ² ] per unit area. The capacitance voltage measurement was performed by forming a Schottky electrode on the surface of the barrier layer 516.

As the Schottky electrode, an outer electrode having an opening and an inner electrode arranged inside the opening were formed. The shape of the inner electrode was a circle having a diameter of 500 μm. The shape of the opening of the outer electrode was a circle having a diameter of 540 μm. The outer electrode has a circular shape. The area of the outer electrode was 2 cm ² or more. The inner electrode, outer electrode, and aperture were designed to be centered. Al was used as the material for the outer and inner electrodes. Capacitance voltage measurement was performed by applying a voltage between the inner electrode and the outer electrode.

As shown in FIG. 7, the residual capacity was less than 1 pF. Further, as shown in FIG. 8, the residual capacity per unit area is less than a value obtained by dividing 1 pF by the area of the inner electrode (2.0 × 10 ⁻³ cm ² ), that is, less than 0.5 nF / cm ² . is there. In the capacitance voltage measurement, the electrostatic capacitance decreased sharply at a bias voltage in the range of about 2.6 V to about 3.1 V, and good pinch-off characteristics were exhibited. The pinch-off voltage was -2.8V. Here, the pinch-off voltage represents a voltage when the n-type carrier concentration is 1 × 10 ¹⁵ cm ⁻³ .

  The p-type carrier concentration and the residual p-type carrier concentration of the buffer layer 504 were calculated using the capacitance voltage measurement results. Here, the p-type carrier concentration of the buffer layer 504 represents the p-type carrier concentration of the buffer layer 504 when formed without doping disilane. Further, the residual p-type carrier concentration of the buffer layer 504 represents the p-type carrier concentration after being compensated by the n-type carrier by doping disilane.

The buffer layer 504 had a p-type carrier concentration of 3.3 × 10 ¹⁶ cm ⁻³ and a residual p-type carrier concentration of 5.0 × 10 ¹⁵ cm ⁻³ . That is, the value obtained by multiplying the film thickness of the buffer layer 504 by the residual p-type carrier concentration of the buffer layer 504 was 2.5 × 10 ¹¹ cm ⁻² , which was 8.0 × 10 ¹¹ cm ⁻² or less.

  In addition, the breakdown voltage of the buffer layer 504 was measured. In the breakdown voltage measurement, the breakdown voltage due to electron conduction and the breakdown voltage due to hole conduction were measured. The breakdown voltage measurement was performed according to the following procedure. First, 130 nm was etched from the surface of the compound semiconductor epitaxial substrate 500 to expose the buffer layer 504. Next, a counter electrode was placed on the exposed buffer layer. The distance between the counter electrodes was 5 μm. The width of the counter electrode was 200 μm. An AuGe / Ni / Au electrode was used for pressure resistance measurement by electron conduction. An AuZn electrode was used for the pressure resistance measurement by hole conduction. The withstand voltage due to electron conduction was 22V, the withstand voltage due to hole conduction was 48V, and a good buffer withstand voltage was obtained.

Furthermore, the hole measurement of the compound semiconductor epitaxial substrate 500 was implemented. Hall measurement was performed by the Van der Pauw method. The two-dimensional electron gas concentration at 300 K was 2.4 × 10 ¹² cm ⁻² . The electron mobility at 300 K was 7600 cm ² / Vs. The two-dimensional electron gas concentration at 77 K was 2.5 × 10 ¹² cm ⁻² . The electron mobility at 77 K was 24000 cm ² / Vs.

(Example 2)
As Example 2, the compound semiconductor epitaxial substrate 500 having the same structure as that of Example 1 was manufactured by setting the flow rate ratio of the Group 5 source gas to the flow rate of the Group 3 source gas to 30 and decreasing the flow rate of the impurity gas. The compound semiconductor epitaxial substrate 500 of Example 2 was manufactured in the same manner as the compound semiconductor epitaxial substrate 500 of Example 1 except that the buffer layer 504 was formed by reducing the flow rate of the impurity gas. Specifically, the flow rate of the impurity gas was set so that the flow rate of disilane was 5.40 × 10 ⁻⁵ cm ³ / min in terms of standard conditions of 101.3 kPa and 0 ° C.

The flow rate difference between the Group 5 source gas and the Group 3 source gas in Example 2 was 386.7 cm ³ / min, as in Example 1. Since the flow rate of the impurity gas disilane is 5.40 × 10 ⁻⁵ cm ³ / min, the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the impurity gas flow rate is 7.16 × 10 ⁶ . there were. The flow rate ratio of the Group 5 source gas to the impurity gas flow rate was 7.41 × 10 ⁶ .

In the compound semiconductor epitaxial substrate 500 of Example 2, the p-type carrier concentration of the buffer layer 504, that is, the p-type carrier concentration of the buffer layer 504 when formed without doping disilane is 3.3 × 10 ¹⁶ cm ^−3. Met. Further, the residual p-type carrier concentration, that is, the p-type carrier concentration after being compensated by the n-type carrier by doping disilane was 8.0 × 10 ¹⁵ cm ⁻³ . That is, the value obtained by multiplying the film thickness of the buffer layer 504 by the carrier concentration of the buffer layer 504 was 4.0 × 10 ¹¹ cm ⁻² , which was smaller than 8.0 × 10 ¹¹ cm ⁻² .

  The withstand voltage due to electron conduction of the buffer layer 504 of Example 2 was 23V, and the withstand voltage due to hole conduction was 37V. Although the breakdown voltage due to hole conduction was lower than the breakdown voltage of the buffer layer 504 of Example 1, a sufficiently good buffer breakdown voltage was obtained.

Example 3
As Example 3, the compound semiconductor epitaxial substrate having the same structure as in Example 1 and Example 2 with the flow rate ratio of the Group 5 source gas to the flow rate of the Group 3 source gas being 30 and the impurity gas flow rate being further reduced 500 was produced. The compound semiconductor epitaxial substrate 500 of Example 3 was manufactured in the same manner as the compound semiconductor epitaxial substrate 500 of Example 1 and Example 2 except that the buffer layer 504 was formed by reducing the flow rate of the impurity gas. Specifically, the flow rate of the impurity gas was set so that the flow rate of disilane was 4.58 × 10 ⁻⁵ cm ³ / min in terms of standard conditions of 101.3 kPa and 0 ° C.

The flow rate difference between the Group 5 source gas and the Group 3 source gas in Example 3 was 386.7 cm ³ / min, as in Example 1. Since the flow rate of disilane, which is an impurity gas, is 4.58 × 10 ⁻⁵ cm ³ / min, the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the flow rate of the impurity gas is 8.44 × 10 ⁶ . there were. Further, the flow rate ratio of the Group 5 source gas to the impurity gas flow rate was 8.73 × 10 ⁶ .

In the compound semiconductor epitaxial substrate 500 of Example 3, the p-type carrier concentration of the buffer layer 504, that is, the p-type carrier concentration of the buffer layer 504 when formed without doping disilane is 3.3 × 10 ¹⁶ cm ^−3. Met. Further, the residual p-type carrier concentration, that is, the p-type carrier concentration after being compensated by the n-type carrier by doping disilane was 1.4 × 10 ¹⁶ cm ⁻³ . That is, a value obtained by multiplying the film thickness of the buffer layer 504 by the carrier concentration of the buffer layer 504 was 7.0 × 10 ¹¹ cm ⁻² , which was smaller than 8.0 × 10 ¹¹ cm ⁻² .

  The withstand voltage due to electron conduction of the buffer layer 504 of Example 2 was 25V, and the withstand voltage due to hole conduction was 26V. Although the withstand voltage due to hole conduction was further lower than the withstand voltage of the buffer layer 504 of Example 2, a sufficiently good buffer withstand voltage was obtained.

(Comparative Example 1)
As Comparative Example 1, a compound semiconductor epitaxial substrate having a structure similar to that of Example 1 was manufactured with a flow rate ratio of the Group 5 source gas to the group 3 source gas being 70. The compound semiconductor epitaxial substrate of Comparative Example 1 is the compound semiconductor epitaxial substrate of Example 1 except that the flow rate ratio of the Group 5 source gas to the group 3 source gas is 70 and the buffer layer is formed without supplying the impurity gas. It was produced under the same conditions as 500. Specifically, the flow rate of the first Group 3 source gas was set so that the flow rate of TMA was 2.7 cm ³ / min in terms of standard conditions of 101.3 kPa and 0 ° C. The flow rate of the second group 3 source gas was set so that the flow rate of TMG was 10.6 cm ³ / min in terms of standard conditions of 101.3 kPa and 0 ° C. The flow rate of the Group 5 source gas was set so that the flow rate of arsine was 930 cm ³ / min in terms of standard conditions of 101.3 kPa and 0 ° C.

In the compound semiconductor epitaxial substrate of Comparative Example 1, the buffer layer had a p-type carrier concentration of 5 × 10 ¹⁵ cm ⁻³ . That is, the value obtained by multiplying the thickness of the buffer layer by the carrier concentration of the buffer layer was 2.5 × 10 ¹¹ cm ⁻² , which was 8.0 × 10 ¹¹ cm ⁻² or less. In Comparative Example 1, the residual p-type carrier concentration is equal to the p-type carrier concentration.

About the compound semiconductor epitaxial substrate of the comparative example 1, the capacity voltage measurement was implemented similarly to the compound semiconductor epitaxial substrate of the example 1. As a result, the residual capacity was less than 1 pF, and the residual capacity per unit area was 0.5 nF / cm ² , indicating good pinch-off characteristics. In the capacitance voltage measurement, the pinch-off voltage, that is, the voltage when the n-type carrier concentration is 1 × 10 ¹⁵ cm ⁻³ was −2.9 V.

  With respect to the buffer layer of Comparative Example 1, withstand voltage measurement was performed in the same manner as the buffer layer 504 of Example 1. The withstand voltage due to electron conduction was 26V, the withstand pressure due to hole conduction was 42V, and a good buffer withstand voltage was obtained.

For the compound semiconductor epitaxial substrate of Comparative Example 1, hole measurement was performed in the same manner as the compound semiconductor epitaxial substrate 500 of Example 1. The two-dimensional electron gas concentration at 300 K was 2.4 × 10 ¹² cm ⁻² . The electron mobility at 300 K was 7600 cm ² / Vs. The two-dimensional electron gas concentration at 77 K was 2.5 × 10 ¹² cm ⁻² . The electron mobility at 77 K was 25000 cm ² / Vs.

(Comparative Example 2)
As Comparative Example 2, a compound semiconductor epitaxial substrate having the same structure as in Example 1 was manufactured by setting the flow rate ratio of the Group 5 source gas to the flow rate of the Group 3 source gas to 30 and decreasing the flow rate of the impurity gas. The compound semiconductor epitaxial substrate of Comparative Example 2 was manufactured in the same manner as the compound semiconductor epitaxial substrate 500 of Example 1 except that the buffer layer was formed by reducing the flow rate of the impurity gas. Specifically, the flow rate of the impurity gas was set so that the flow rate of disilane was 4.12 × 10 ⁻⁵ cm ³ / min in terms of standard conditions of 101.3 kPa and 0 ° C.

The flow rate difference between the Group 5 source gas and the Group 3 source gas in Comparative Example 2 was 386.7 cm ³ / min, as in Example 1. Since the flow rate of the impurity gas disilane is 4.12 × 10 ⁻⁵ cm ³ / min, the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the impurity gas flow rate is 9.39 × 10 ⁶ . there were. The flow rate ratio of the Group 5 source gas to the impurity gas flow rate was 9.71 × 10 ⁶ .

In the compound semiconductor epitaxial substrate of Comparative Example 2, the p-type carrier concentration of the buffer layer, that is, the original p-type carrier concentration without doping disilane was 3.3 × 10 ¹⁶ cm ⁻³ . Further, the residual p-type carrier concentration, that is, the p-type carrier concentration after being compensated by the n-type carrier concentration was 2.0 × 10 ¹⁶ cm ⁻³ . That is, the value obtained by multiplying the thickness of the buffer layer 504 by the carrier concentration of the buffer layer 504 was 1.0 × 10 ¹² cm ⁻² , which was larger than 8.0 × 10 ¹¹ cm ⁻² .

FIG. 9 shows the results of capacitance voltage measurement on the compound semiconductor epitaxial substrate of Comparative Example 2. FIG. 10 shows a diagram in which the vertical axis in the result of the capacitive voltage measurement shown in FIG. 9 is converted into a capacitance [F / cm ² ] per unit area. For the compound semiconductor epitaxial substrate of Comparative Example 2, the capacitance voltage measurement was performed in the same manner as the compound semiconductor epitaxial substrate 500 of Example 1. As shown in FIG. 9, p-type carriers remained, resulting in a residual capacity of 17 pF. By dividing the residual capacity of 17 pF by the area of the inner electrode (2.0 × 10 ⁻³ cm ² ), the residual capacity per unit area was calculated to be 8.7 nF / cm ² .

9 and 10 are compared with FIGS. 7 and 8, it can be seen that the pinch-off characteristics are deteriorated. Specifically, after the residual capacitance was reduced to 17 pF within a bias voltage range of about 2.6 V to about 3.0 V, the residual capacitance was further reduced at a bias voltage of about 4.5 V or more. Since the energy level of the p-type carrier is deep, it is considered that the p-type carrier remains at a voltage of about 4.5 V or less. The pinch-off voltage in Comparative Example 2, that is, the voltage when the n-type carrier concentration was 1 × 10 ¹⁵ cm ⁻³ was −2.5V.

  With respect to the buffer layer of Comparative Example 2, withstand voltage measurement was performed in the same manner as the buffer layer 504 of Example 1. The breakdown voltage due to electron conduction was 23V, and the breakdown voltage due to hole conduction was 7V. Compared with Example 1, Example 2, Example 3, and Comparative Example 1, it can be seen that the hole conduction breakdown voltage is greatly reduced.

For the compound semiconductor epitaxial substrate of Comparative Example 2, hole measurement was performed in the same manner as the compound semiconductor epitaxial substrate 500 of Example 1. The two-dimensional electron gas concentration at 300 K was 2.1 × 10 ¹² cm ⁻² . The electron mobility at 300 K was 7600 cm ² / Vs. The two-dimensional electron gas concentration at 77 K was 2.1 × 10 ¹² cm ⁻² . The electron mobility at 77 K was 25000 cm ² / Vs. It is considered that the neutral region was generated by the p-type carrier and the two-dimensional electron gas concentration was lowered.

Table 1 shows the buffer growth conditions in each of Example 1 to Comparative Example 2. Table 2 shows the results of buffer growth in each of Example 1 to Comparative Example 2. The n breakdown voltage in Table 2 indicates the breakdown voltage due to electron conduction. The p breakdown voltage indicates a breakdown voltage due to hole conduction. Table 3 shows the active layer characteristics in each of Example 1 to Comparative Example 2.

  As is apparent from Table 2, the breakdown voltage due to hole conduction is significantly reduced in Comparative Example 2. Further, as apparent from Table 3, the residual capacity per unit area is significantly reduced in Comparative Example 2.

  Therefore, Comparative Example 2 is compared with Example 3. Between Comparative Example 2 and Example 3, the flow rate of disilane which is an impurity gas is different. That is, the ratio of the difference between the flow rate of the Group 5 source gas and the flow rate of the Group 3 source gas with respect to the flow rate of disilane differs between Comparative Example 2 and Example 3. When the difference between the flow rate of the group 5 source gas and the flow rate of the group 3 source gas with respect to the flow rate of disilane is not an appropriate amount, the residual p-type carrier concentration exceeds the appropriate value and the residual capacity increases. It is considered that the breakdown voltage due to conduction decreases.

The ratio of the difference between the flow rate of the Group 5 source gas and the flow rate of the Group 3 source gas to the flow rate of disilane in Example 3 is 8.44 × 10 ⁶ , whereas the Group 5 source material with respect to the flow rate of disilane in Comparative Example 2 The ratio of the difference between the gas flow rate and the Group 3 source gas flow rate is 9.39 × 10 ⁶ . Therefore, it is considered that a compound semiconductor having good buffer performance grows when the ratio of the difference between the flow rate of the group 5 source gas and the flow rate of the group 3 source gas with respect to the flow rate of disilane is about 9.0 × 10 ⁶ or less. . The ratio of the difference between the flow rate of the Group 5 source gas and the flow rate of the Group 3 source gas to the flow rate of disilane may be 8.44 × 10 ⁶ or less.

Further, the flow rate of the Group 5 source gas with respect to the flow rate of disilane in Example 3 is 8.73 × 10 ⁶ , whereas the flow rate ratio of the Group 5 source gas with respect to the flow rate of disilane in Comparative Example 2 is 9.71 × 10 ⁶ . Therefore, when the flow rate ratio of the group 5 source gas to the flow rate of the group 3 source gas is 30, it is good when the flow rate ratio of the group 5 source gas to the flow rate of disilane is about 9.0 × 10 ⁶ or less. It is considered that a compound semiconductor having a good buffer performance will grow. When the flow rate ratio of the group 5 source gas to the flow rate of the group 3 source gas is 30, the flow rate ratio of the group 5 source gas to the flow rate of disilane may be 8.73 × 10 ⁶ or less.

Further, the product of the residual carrier concentration and the film thickness in Example 3 is 7.0 × 10 ¹¹ , whereas the product of the residual carrier concentration and the film thickness in Comparative Example 2 is 1.0 × 10 ^12. It is. Therefore, it is considered that a compound semiconductor having good buffer performance grows when the product of the residual carrier concentration and the film thickness is 8.0 × 10 ¹¹ or less. The product of the residual carrier concentration and the film thickness may be 7.0 × 10 ¹¹ or less.

  As described above, the compound semiconductor epitaxial substrates of Example 1, Example 2, and Example 3 were less than the compound semiconductor epitaxial substrate of Comparative Example 1 by reducing the Group 5 source gas by about 60%. The device characteristics equivalent to those of the compound semiconductor epitaxial substrate of Comparative Example 1 are shown. On the other hand, as shown in Comparative Example 2, sufficient characteristics cannot be obtained simply by reducing the Group 5 source gas. That is, by adopting the configuration according to the present invention, a Group 3-5 compound semiconductor showing good device characteristics was obtained despite the significant reduction in the amount of Group 5 source gas used. Thereby, the manufacturing cost of the compound semiconductor epitaxial substrate and the semiconductor device can be greatly reduced.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, and method shown in the claims, the specification, and the drawings is particularly “before”, “prior”, etc. It should be noted that it can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  100 compound semiconductor epitaxial substrate, 102 base substrate, 103 main surface, 104 3-5 group compound semiconductor, 300 semiconductor device, 310 active layer, 400 compound semiconductor epitaxial substrate, 420 contact layer, 500 compound semiconductor epitaxial substrate, 502 base substrate, 503 main surface, 504 buffer layer, 506 back side electron supply layer, 508 back side spacer layer, 510 channel layer, 512 front side spacer layer, 514 front side electron supply layer, 516 barrier layer, 520 contact layer, 600 semiconductor device, 622 contact layer, 624 contact layer, 632 drain electrode, 634 source electrode, 636 control electrode

Claims (12)

Installing a base substrate inside the reaction vessel;
An impurity gas containing a group 3 source gas composed of an organometallic compound of a group 3 element and a group 5 source gas composed of a compound containing a group 5 element, and an impurity doped into a semiconductor to serve as a donor. And epitaxially growing a p-type group 3-5 compound semiconductor on the base substrate,
In the step of epitaxially growing the p-type group 3-5 compound semiconductor on the base substrate, the flow rate of the impurity gas and the flow rate ratio of the group 5 source gas to the group 3 source gas are set as the p-type group 3-5 compound. A product N × d (cm ⁻² ) of the residual carrier concentration N (cm ⁻³ ) and thickness d (cm) of the semiconductor is set to 8.0 × 10 ¹¹ or less.
A method for manufacturing a semiconductor substrate. In the step of epitaxially growing the p-type group 3-5 compound semiconductor on the base substrate, a flow rate ratio of the group 5 source gas to the group 3 source gas is set to 50 or less.
A method for manufacturing a semiconductor substrate according to claim 1. In the step of epitaxially growing the p-type group 3-5 compound semiconductor on the base substrate, the residual per unit area by capacitance voltage measurement using a Schottky electrode in contact with the active layer on the p-type group 3-5 compound semiconductor is further provided. Setting the flow rate of the impurity gas and the flow rate ratio of the Group 5 source gas to the Group 3 source gas so that the capacity is less than 0.5 nF / cm ² ;
The manufacturing method of the semiconductor substrate of Claim 1 or 2. In the step of epitaxially growing the p-type group 3-5 compound semiconductor on the base substrate, a ratio of a flow rate difference between the group 5 source gas and the group 3 source gas to a flow rate of the impurity gas is 9.0 × 10 ⁶ or less. Set to
The manufacturing method of the semiconductor substrate as described in any one of Claim 1 to 3. The impurity gas contains at least one element selected from the element group consisting of Si, Se, Ge, Sn, S, and Te.
The manufacturing method of the semiconductor substrate as described in any one of Claim 1 to 4. The p-type group 3-5 compound semiconductor and further an active layer are stacked in this order on the base substrate.
The method for manufacturing a semiconductor substrate according to claim 1. A base substrate;
On the base substrate, a group 3 source gas composed of an organometallic compound of a group 3 element, a group 5 source gas composed of a group 5 element, and an impurity gas containing an impurity doped into a semiconductor and serving as a donor are supplied on the base substrate. An epitaxially grown p-type group 3-5 compound semiconductor, and
In the p-type group 3-5 compound semiconductor, a product N × d (cm ⁻² ) of a residual carrier concentration N (cm ⁻³ ) and a thickness d (cm) is 8.0 × 10 ¹¹ or less.
Semiconductor substrate. The p-type group 3-5 compound semiconductor was epitaxially grown under the condition that the ratio of the group 5 source gas to the group 3 source gas was 50 or less.
The semiconductor substrate according to claim 7. In the capacitance voltage measurement using a Schottky electrode in contact with the active layer on the p-type group 3-5 compound semiconductor, the residual capacitance per unit area is less than 0.5 nF / cm ² .
The semiconductor substrate according to claim 7 or 8. The p-type Group 3-5 compound semiconductor was epitaxially grown under the condition that the ratio of the flow rate difference between the Group 5 source gas and the Group 3 source gas to the flow rate of the impurity gas was 9.0 × 10 ⁶ or less.
The semiconductor substrate as described in any one of Claim 7 to 9. Including at least one element selected from the element group consisting of Si, Se, Ge, Sn, S and Te as a donor impurity;
The semiconductor substrate according to claim 7. The p-type group 3-5 compound semiconductor and further an active layer are stacked in this order on the base substrate.
The semiconductor substrate according to any one of claims 7 to 11.

Images