JP4984511B2 - III-V compound semiconductor device - Google Patents

Description

  The present invention relates to a group III-V compound semiconductor device such as a field effect transistor (FET) or a high electron mobility transistor (HEMT), and particularly to an improvement of a buffer layer thereof.

  In order to improve the performance of the transistor, it is important to use a material that can transmit more majority carriers at a higher speed. GaAs (gallium arsenide) and InGaAs (indium gallium arsenide) are characterized by higher electron mobility than Si (silicon). Taking advantage of this feature, GaAs and InGaAs are often used in high-speed devices. A representative example is HEMT (High Electron Mobility Transistor).

  Field effect transistors such as FETs and HEMTs generally use an epitaxial wafer in which a buffer layer is epitaxially grown on a semi-insulating GaAs substrate and an active layer is epitaxially grown thereon.

  A rough structure of the HEMT is shown in FIG. The HEMT includes a buffer layer, a channel layer, a spacer layer, a carrier supply layer, and a contact layer that are crystal-grown on a substrate. The contact layer is a layer for forming an electrode. The carrier supply layer is a layer for generating free electrons and supplying them to the channel layer. The channel layer is a layer through which free electrons flow and needs to be highly pure.

  The buffer layer is provided in order to prevent the defect layer generated at the interface between the substrate and the epitaxial crystal from affecting the active layer. If the buffer layer has a low resistance, current leaks from the active layer to the buffer layer. Therefore, the buffer layer is required to be a high resistance epitaxial crystal. In order to increase the resistance of the buffer layer, it is necessary to lower the impurity concentration of the buffer layer or increase the hetero barrier.

Conventionally, when the current leaks to the buffer layer, the device characteristics are remarkably deteriorated. Therefore, in the field effect semiconductor device manufactured by epitaxially growing the p-type buffer layer and the channel layer on the p-type semiconductor substrate, the leak current is suppressed. It is disclosed that the acceptor concentration of the p-type buffer layer is 5 × 10 ¹⁵ / cm ³ to 5 × 10 ¹⁶ / cm ³ (see, for example, Patent Document 1).
JP-A-10-116837 (paragraph 0019)

  However, no p-type concentration has been discussed in relation to the Al mixed crystal ratio and film thickness of the buffer layer.

  As a result of diligent research efforts by the present inventors, the following has been found. That is, the problem is that a low resistance conductive layer exists at the interface between the semi-insulating substrate and the epitaxial layer of the epitaxial wafer manufactured by the crystal growth method described above. When a field effect transistor such as a HEMT is manufactured using such an epitaxial wafer, a leakage current flows between the source electrode and the drain electrode through the conductive layer at the interface between the epitaxial layer and the substrate, thereby deteriorating the electrical characteristics of the transistor. The reason why the low resistance layer is formed is that silicon existing everywhere in the atmosphere and dopant raw material remaining in the growth furnace adhere to the surface of the substrate before growth and exist after growth. It is thought to become a mold carrier.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to further reduce the leakage current (less than 1 × 10 ⁻⁹ A) between the electrodes by making the buffer structure appropriate, thereby increasing the breakdown voltage and improving the performance. An object of the present invention is to provide a group III-V compound semiconductor device which realizes the fabrication.

By limiting the range of the Nd product of the Al _x Ga _1-x As layer as the lowermost layer of the buffer layer, the leakage current between the electrodes is reduced.

  In order to achieve the above object, the present invention is configured as follows.

The invention according to claim 1, on a semi-insulating substrate, Ba Ffa layer in order from the lower layer, the channel layer, a spacer layer, the carrier supply layer, Schottky layer, the group III-V compound semiconductor device having a contact layer, the semi the insulating substrate is a GaAs substrate, the buffer layer, a GaAs layer and without addition of additive-free Al _x Ga _1-x As layer (0 ≦ x ≦ 1) GaAs / stacked alternately Al _x Ga _1- a lamination portion heterostructures _x as grown two or more times, p-type buffer Al _x Ga _1-x as provided as the lowermost layer of the buffer layer beneath the stack portion (0.3 ≦ x ≦ 1) The channel layer is an i-type In _0.20 Ga _0.80 As layer having a thickness of 20 nm and a carrier concentration of 1 × 10 ¹⁶ / cm ³ or less , and the spacer layer has a thickness of 3 nm and a carrier concentration of 1 × 10 ¹⁶ / cm ³ or less of the i-type a A _0.25 Ga _0.75 As layer, the carrier supply layer has a thickness of 250 nm, n-type Al _0.25 Ga _0.75 As layer having a carrier concentration ³ × 10 ¹⁸ / cm 3, the Schottky layer has a thickness of 50 nm, the carrier An i-type Al _0.25 Ga _0.75 As layer with a concentration of 1 × 10 ¹⁶ / cm ³ or less , the contact layer is an n-type GaAs layer with a thickness of 100 nm and a carrier concentration of 3 × 10 ¹⁸ / cm ³ , and the channel layer The spacer layer, the carrier supply layer, and the Schottky layer have a HEMT structure .

The invention of claim 2 is the group III-V compound semiconductor device according to claim 1 Symbol placement, and product (Nd product of film thickness and the oxygen or a transition metal or p-type carrier concentration of both the p-type buffer layer Is in the range of 1 × 10 ¹⁰ to 1 × 10 ¹² / cm ² .

A third aspect of the present invention, the group III-V compound semiconductor device according to claim 2, wherein the p-type carrier concentration, characterized in that oxygen or a transition metal, or both is by doped.

According to a fourth aspect of the present invention, in the III-V compound semiconductor device according to any one of the first to third aspects, the thickness of the p-type Al _x Ga _1-x As layer inserted as the p-type buffer layer is 2 ˜50 nm.

<Key points of the invention>
The present invention provides a p-type Al _x Ga _1-x As (0.3 ≦ x ≦ 1) layer portion as the lowermost layer of a buffer layer in a III-V compound semiconductor device such as an FET or HEMT. In order to lift the band with the p-type, it is possible to suppress the leakage current flowing to the buffer layer side. That is, even with the same Nd product, the leakage current can be reduced by increasing the mixed crystal ratio x in p-type Al _x Ga _1-x As to 0.3 or more. FIG. 6 shows how the leakage current decreases as the mixed crystal ratio x is increased to x = 0.35, x = 0.55, and x = 0.75.

In the present invention, the product (Nd product) of the thickness of the p-type buffer layer, which is the lowermost layer of the buffer layer, and the p-type carrier concentration of the p-type buffer layer is 1 × 10 ¹⁰ to 1 × 10 ¹² / cm. ^{Be in} the range of ² . FIG. 7 shows this optimum range. Thus, by defining the thickness of the buffer layer and the p-type concentration of the lowermost layer, it is possible to reduce the leakage current, and to realize a high breakdown voltage and high performance of the field effect transistor.

  According to the present invention, leakage current when a low voltage is applied can be reduced. That is, by increasing the resistance of the III-V compound semiconductor crystal in the buffer layer, it is possible to realize a high breakdown voltage and high performance of a III-V compound semiconductor device such as an FET or HEMT.

  Hereinafter, the present invention will be described based on the illustrated embodiments.

As an embodiment of the present invention, the structure of a HEMT epitaxial wafer is shown in FIG. A group III organometallic source gas and a group V source gas are fed into the reactor as a mixed gas of high-purity hydrogen carrier gas, and the source material is thermally decomposed near the substrate heated in the reactor and is epitaxially grown on the substrate. Using a metal organic vapor phase epitaxy (hereinafter referred to as MOVPE method), a p-type Al _x Ga _1-x As layer having a certain range of Nd product is inserted into the lowermost layer of the buffer layer, thereby increasing the height. A III-V compound semiconductor crystal having high resistance and high withstand voltage is grown. The substrate temperature during growth is 650 ° C., the growth furnace pressure is 76 Torr, and the dilution gas is hydrogen. A GaAs substrate was used as the substrate.

The buffer layer 2 is provided on the semi-insulating GaAs substrate 1 by the MOVPE method, and the i-type In _0.20 Ga _0.80 As (thickness 20 nm, carrier concentration 1 × 10 ¹⁶ / cm ³ or less) is formed thereon as the channel layer 3. Is provided. Furthermore, an i-type Al _0.25 Ga _0.75 As layer (thickness 3 nm, carrier concentration 1 × 10 ¹⁶ / cm ³ or less) is used as the spacer layer 4, and an n-type Al _0.25 Ga _0.75 As (thickness) is used as the carrier supply layer 5. 250 nm, carrier concentration 3 × 10 ¹⁸ / cm ³ ), and an i-type Al _0.25 Ga _0.75 As (thickness 50 nm, carrier concentration 1 × 10 ¹⁶ / cm ³ or less) as a gate contact layer (Schottky layer) 6 thereon An n-type GaAs (thickness: 100 nm, carrier concentration: 3 × 10 ¹⁸ / cm ³ ) was provided as a contact layer 7 thereon.

The buffer layer 2 includes a laminated portion 2b in which a heterostructure of GaAs / Al _x Ga _1-x As in which GaAs layers and Al _x Ga _1-x As layers (0 ≦ x ≦ 1) are alternately stacked is grown twice or more. And p-type Al _x Ga _1-x As (0.3 ≦ x ≦ 1) provided as the lowermost layer 2a of the buffer layer under the laminated portion. Here, p-type Al _0.50 Ga _0.50 As (thickness 10 nm, carrier concentration 2 × 10 ¹⁷ / cm ³ ) was provided as the lowermost layer 2 a of the buffer layer 2. And the product of the film thickness (10 nm) of the lowermost layer 2a in this buffer layer 2 and the p-type carrier concentration by doping oxygen or transition metal is in the range of 1 × 10 ¹⁰ to 1 × 10 ¹³ / cm ² . I paid. As the transition metal, any one of Ti (titanium), Cr (chromium), Fe (iron), Co (cobalt), Ni (nickel), Cu (copper), and Zn (zinc) is selectively used. did.

In the above, for the growth of the p-type Al _0.50 Ga _0.50 As layer, which is the lowermost layer 2a of the buffer layer 2, Ga (CH ₃ ) ₃ (trimethylgallium), Al (CH ₃ ) ₃ (trimethylaluminum) and AsH ₃ ( arsine), each of those flow rate 5.3 cm ³ / min, was 2.20cm ³ / min and 250 cm ³ / min.

Ga (CH ₃ ) ₃ and AsH ₃ were used for growing the i-type GaAs layer of the buffer layer 2. The flow rate of Ga (CH ₃ ) ₃ is 10.5 cm ³ / min. The flow rate of AsH ₃ is 315 cm ³ / min.

Ga (CH ₃ ) ₃ , Al (CH ₃ ) _3, and AsH ₃ are used for growing the i-type Al _0.25 Ga _0.75 As layer of the buffer layer 2, the spacer layer 4, and the gate contact layer 6. 5.3 cm ³ / min, 1.43 cm ³ / min and 630 cm ³ / min.

Ga (CH ₃ ) ₃ , In (CH ₃ ) ₃ and AsH ₃ are used for growing the i-type In _0.20 Ga _0.80 As layer of the channel layer 3, and their flow rates are 5.3 cm ³ / min and 2.09 cm, respectively. ³ / min and 500 cm ³ / min.

For the growth of the n-type Al _0.25 Ga _0.75 As layer of the carrier supply layer 5, in addition to Ga (CH ₃ ) ₃ , Al (CH ₃ ) ₃ , AsH ₃ used for the growth of i-type Al _0.25 Ga _0.75 As, Si ₂ H ₆ was used. The flow rate of Si ₂ H ₆ is 7.78 × 10 ⁻³ cm ³ / min. The flow rate other than Si ₂ H ₆ is the same as that of the i-type Al _0.25 Ga _0.75 As layer.

For the growth of the n-type GaAs layer of the contact layer 7, Si ₂ H ₆ was used in addition to Ga (CH ₃ ) ₃ and AsH ₃ used for the growth of i-type GaAs. The flow rate of Si ₂ H ₆ is 1.47 × 10 ⁻⁴ cm ³ / min.

<Reason for optimum conditions>
In order to confirm the effect of the present invention, the leakage current of the epitaxial wafer doped with oxygen or transition metal was measured in the range of 1 × 10 ⁹ to 2 × 10 ¹² / cm ² in terms of Nd product. The measurement diagram is shown in FIG. 2, and the results are shown in FIGS.

  The method of measurement is as shown in FIG. 2. In order to perform the measurement, the contact layer, carrier supply layer, spacer layer, and channel layer are partially removed, and two electrodes are attached to the contact layer surface. The value of the current that flows when a voltage is applied across both ends is measured.

The measurement results of the leakage current are as shown in FIGS. 3 to 5. As the Nd product of the lowermost layer 2a of the buffer layer is increased to 1 × 10 ⁹ to 2 × 10 ¹² / cm ² , the leakage current decreases. .

FIG. 6 shows the relationship between the Nd product and the leakage current when a voltage is applied (applied voltage: 20 V). As shown in FIG. 6, the mixed crystal ratio in p-type Al _x Ga _1-x As is increased. By doing so, the amount of leakage current can be reduced even with the same Nd product.

Here, FIG. 6 shows the Nd product with the Al composition x of the p-type buffer layer (the lowermost layer 2a) made of AlGaAs being x = 0.35, x = 0.55, and x = 0.75 as parameters. And the relationship between the leakage current when a voltage is applied (applied voltage: 20 V). Notice the right edge of these curves. In a region where the Nd product of the buffer layer is larger than the right end of the buffer layer, that is, the mixed crystal ratio is x = 0.35, the Nd product = 2 × 10 ¹² / cm ² , the mixed crystal ratio is x = 0.55, and the Nd product = When 1 × 10 ¹¹ / cm ² , the mixed crystal ratio is greater than x = 0.75 and the Nd product = 8 × 10 ¹¹ / cm ² , oxygen or transition metal diffuses into the active layer, and the active layer and buffer layer In the vicinity, traveling electrons may be scattered by impurities due to oxygen or transition metal. If the p-type buffer layer (lowermost layer 2a) is too thick, the resistance is lowered. If the p-type buffer layer is too thin, the original function of the buffer layer is to prevent the defect layer from affecting the active layer at the interface between the substrate and the epitaxial crystal. It will not run out. The optimum range of the Nd product of the buffer layer at each mixed crystal ratio is shown in FIG.

As can be seen from FIG. 7, as the optimum range with a small leakage current, Al _x Ga _1-x As in the lowermost layer of the buffer layer should have a mixed crystal ratio x in the range of 0.3 to 1.0. Also, the uppermost layer constituting the buffer layer is not doped in order to avoid traveling electrons from being scattered by oxygen or transition metal in the vicinity of the active layer and buffer layer due to diffusion of oxygen or transition metal into the active layer. An undoped epitaxial crystal is desirable.

<Other embodiments and modifications>
In the group III-V compound semiconductor crystal constituting the semiconductor device of the present invention, the group III element includes In (indium) in addition to Ga (gallium) and Al (aluminum), and the group V element includes As (arsenic). ) And P (phosphorus). With these combinations, III-V compound semiconductor crystals can be formed from binary crystals such as InGaAs, AlInAs, AlGaInAs, GaP, AlP, InP, AlGaP, GaInP, and AlGaIn in addition to GaAs and Al _x Ga _1-x As. It can be applied to quaternary crystals.

  Note that the product of the film thickness and the carrier concentration can be defined even when the HBT buffer layer is grown.

  The present invention can be applied not only to electronic devices such as FETs and HEMTs, but also to semiconductor integrated circuits centering on them, and can also be used for light emitting / receiving elements and laser-embedded resistive layers.

It is a figure which shows the cross-section of HEMT which concerns on one Embodiment of this invention. It is a figure which shows the method of applying a voltage and measuring the leakage current of a buffer layer. It is a figure which shows the relationship between Nd product and leakage current in case of the mixed crystal ratio 0.35 which concerns on one Embodiment of this invention. It is a figure which shows the relationship between Nd product and leak current in the case of the mixed crystal ratio 0.55 which concerns on one Embodiment of this invention. It is a figure which shows the relationship between Nd product and leak current in the case of the mixed-crystal ratio 0.75 which concerns on one Embodiment of this invention. It is a figure which shows the relationship between Nd product of the buffer layer lowest layer of HEMT which concerns on a prototype, and leakage current. It is a figure which shows the optimal condition of Nd product when changing the mixed crystal ratio of this invention. It is a figure which shows the cross-section of HEMT to which this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 2a Bottom layer 2b Laminated part 3 Channel layer 4 Spacer layer 5 Carrier supply layer 6 Gate contact layer 7 Contact layer 9 Electrode

Claims (4)

A semi-insulating substrate, Ba Ffa layer in order from the lower layer, the channel layer, a spacer layer, the carrier supply layer, Schottky layer, the group III-V compound semiconductor device having a contact layer,
The semi-insulating substrate is a GaAs substrate;
The buffer layer, GaAs layer and Al _x Ga _1-x As layer of additive-free additive-free (0 ≦ x ≦ 1) alternately stacked GaAs / Al _x Ga _1-x As heterostructure least twice the is composed of a grown laminated portion, and the p-type buffer layer of Al _x Ga _1-x as provided as the lowermost layer of the buffer layer beneath the stacked portion (0.3 ≦ x ≦ 1),
The channel layer is an i-type In _0.20 Ga _0.80 As layer having a thickness of 20 nm and a carrier concentration of 1 × 10 ¹⁶ / cm ³ or less ,
The spacer layer is an i-type Al _0.25 Ga _0.75 As layer having a thickness of 3 nm and a carrier concentration of 1 × 10 ¹⁶ / cm ³ or less ,
The carrier supply layer is an n-type Al _0.25 Ga _0.75 As layer having a thickness of 250 nm and a carrier concentration of 3 × 10 ¹⁸ / cm ³ .
The Schottky layer is an i-type Al _0.25 Ga _0.75 As layer having a thickness of 50 nm and a carrier concentration of 1 × 10 ¹⁶ / cm ³ or less ,
The contact layer is an n-type GaAs layer having a thickness of 100 nm and a carrier concentration of 3 × 10 ¹⁸ / cm ³ .
The III-V group compound semiconductor device , wherein the channel layer, the spacer layer, the carrier supply layer, and the Schottky layer have a HEMT structure . In group III-V compound semiconductor device according to claim 1 Symbol placement,
The product of the thickness of the p-type buffer layer and the p-type carrier concentration of the p-type buffer layer (Nd product) is in the range of 1 × 10 ¹⁰ to 1 × 10 ¹² / cm ^2. III-V group compound semiconductor device. The group III-V compound semiconductor device according to claim 2 ,
The III-V group compound semiconductor device, wherein the p-type carrier concentration is obtained by doping oxygen, a transition metal, or both. In the III-V compound semiconductor device according to any one of claims 1 to 3 ,
A III-V group compound semiconductor device, wherein the p-type Al _x Ga _1-x As layer inserted as the p-type buffer layer has a thickness of 2 to 50 nm.

Images