JP2008192830A - Third-fifth group compound semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a group III-V compound semiconductor device sufficiently suppressing buffer leak current, and also to provide a manufacturing method for the semiconductor device. <P>SOLUTION: The group III-V compound semiconductor device (1) includes an additive-free buffer layer (12) formed between a single layer substrate (11) and a channel layer (13). In the interface between the single layer substrate (11) and the additive-free buffer layer (12), an oxygen δ doping layer (12a) is formed on the surface of additive-free buffer layer (12) that is closer to the single layer substrate (11), or in the additive-free buffer layer (12). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a group III-V compound semiconductor device and a method for manufacturing the same, and more particularly to a group III-V compound semiconductor device suitable for a field effect transistor (FET) or a high electron mobility transistor (HEMT) which is a kind of FET, and It relates to the manufacturing method.

  Compound semiconductors such as gallium arsenide (GaAs) and indium gallium arsenide (InGaAs) have a feature of higher electron mobility than silicon (Si). Taking advantage of these features, GaAs and InGaAs are often used in devices that require high-speed operation and high-efficiency operation. A representative example is HEMT.

FIG. 5 shows a cross-sectional structure of a conventional HEMT10. This HEMT10 is a semi-insulating substrate (
On the GaAs substrate 11, an additive-free buffer layer (GaAs layer or A1 GaAs layer) 12, channel layer (InGaAs layer) 13, spacer layer (AlGaAs layer) 14, carrier supply layer (A
lGaAs layer) 15, Schottky layer (AlGaAs layer or GaAs layer) 16 and contact layer (InGaAs layer) 17 are epitaxially grown in sequence, and contact layer 17 is selectively etched to expose a part of Schottky layer 16, The source electrode 102 and the drain electrode 103 are formed on the remaining contact layer 17, and the gate electrode 101 is formed on the exposed portion of the Schottky layer 16.

The buffer layer 12 made of GaAs or A1GaAs is required to have a high resistance. The reason is as follows.
In the operation of the HEMT, a source-drain current flows through the channel layer 13 by changing the thickness of the channel layer 13 by a depletion layer extending from the Schottky interface of the gate electrode 101 to the channel layer 13 when a gate voltage is applied. Controlled by current. When a voltage that depletes the channel layer 13 is applied, no current flows between the source and the drain. This state is called pinch-off. The current flowing between the source and the drain at the time of pinch-off is called a buffer leakage current and is required to be 1 × 10 ⁻⁹ A or less. For this reason, the carrier concentration of the buffer layer 12 is kept low, and the specific resistance of the buffer layer 13 is increased. Conventionally, the carrier concentration of the additive-free buffer layer 12 is generally set to 1 × 10 ¹⁵ cm ⁻³ or less.

Conventionally, in a compound semiconductor wafer for a transistor, there has been a proposal that oxygen is uniformly doped into a buffer layer to increase the resistance of the buffer layer and suppress a buffer leakage current (for example, Patent Document 1).
JP 2000-312000 A

However, according to the conventional HEMT10 shown in FIG. 5, as a result of fabricating and evaluating the device, it was found that a buffer leakage current of 1 × 10 ⁻⁶ A flows. The carrier concentration of the additive-free buffer layer 12 made of GaAs or AlGaAs is 1 × 10 ¹⁵ cm ⁻³ for p-type. This carrier concentration depends on the epitaxial growth conditions. To lower the carrier concentration, it is effective to increase the growth temperature and increase the V / III flow rate ratio during growth.
Even if these methods are used, it is difficult to achieve a carrier concentration of 5 × 10 ¹⁴ cm ⁻³ or less, and the buffer leak current cannot be suppressed to 1 × 10 ⁻⁹ A or less. In addition, in the additive-free buffer layer 12 which is an epitaxial layer, since there is no deep energy level like EL2, a decrease in carrier concentration due to a compensation mechanism such as a semi-insulating GaAs substrate cannot be expected, and high resistance is not achieved. It can't be.
Further, in the structure using the buffer layer uniformly doped with oxygen, the leakage current cannot be sufficiently reduced, and there is a problem in long-term reliability.

An object of the present invention is to provide a group III-V compound semiconductor device capable of sufficiently suppressing a buffer leakage current when a device is manufactured and a method for manufacturing the same.

In order to solve the above problems, the present invention is configured as follows.
A first aspect of the present invention includes an additive-free buffer layer between the single crystal substrate and the channel layer.
In the group V compound semiconductor device, an oxygen δ doping layer at an interface between the single crystal substrate and the additive-free buffer layer, at an interface of the additive-free buffer layer on the single-crystal substrate side, or in the additive-free buffer layer The III-V compound semiconductor device is characterized in that is formed.

According to a second aspect of the present invention, in the group III-V compound semiconductor device according to the first aspect, the additive-free buffer layer is a GaAs layer or an A1 GaAs layer.

According to a third aspect of the present invention, in the III-V group compound semiconductor device according to the first aspect or the second aspect, the oxygen δ doping layer is 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ^−3. And an oxygen concentration in the range of 10 nm to 100 nm.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a group III-V compound semiconductor device in which an epitaxial layer including an additive-free buffer layer and a channel layer is grown on a single-crystal substrate, the single-crystal substrate and the additive-free buffer. A group III-V compound semiconductor comprising a step of forming an oxygen δ-doping layer at an interface of the layer, at an interface of the additive-free buffer layer on the single crystal substrate side, or in the additive-free buffer layer It is a manufacturing method of an apparatus.

According to a fifth aspect of the present invention, in the method for manufacturing a group III-V compound semiconductor device according to the fourth aspect, the oxygen δ doping layer is formed by supplying an oxygen gas.

  According to the present invention, the buffer leak current can be sufficiently suppressed when the device is manufactured by having the oxygen δ doving layer. Therefore, an FET (field effect transistor) excellent in switching characteristics can be manufactured.

Embodiments of a III-V compound semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a HEMT which is a first embodiment of a III-V compound semiconductor device according to the present invention. This HEMTl is formed on a semi-insulating substrate 11 made of GaAs with an oxygen δ doping layer (a layer in which AlGaAs layer is highly doped with δ) 12a, an additive buffer layer (GaAs layer or AlGaAs layer) 12, A channel layer (InGaAs layer) 13, a spacer layer (AlGaAs layer) 14, a carrier supply layer (AlGaAs layer) 15, a Schottky layer (AlGaAs layer or GaAs layer) 16 and a contact layer (InGaAs layer) 17 are sequentially epitaxially grown. The contact layer 17 is selectively etched to expose a part of the Schottky layer 16, the source electrode 102 and the drain electrode 103 are formed on the remaining contact layer 17, and the gate is formed on the exposed part of the Schottky layer 16. The electrode 101 is formed.

  Here, the contact layer 17 is a layer that forms an ohmic junction with the source electrode 102 and the drain electrode 103. The Schottky layer 16 is a layer that forms a Schottky junction with the gate electrode 101. The carrier supply layer 15 is a layer that is doped with n-type impurities and emits free electrons to be supplied to the channel layer 13. The channel layer 13 is a layer through which free electrons flow and needs to be highly pure. The spacer layer 14 is a layer that inhibits free electrons in the channel layer 13 from being ion-scattered by n-type impurities in the carrier supply layer 15. The additive-free buffer layer 12 is a layer formed to prevent deterioration of device characteristics due to residual impurities on the surface of the substrate 11.

In the operation of the HEMT1, the current between the source and the drain is mainly a current flowing through the channel layer 13, and the current flowing through the channel layer 13 extends from the Schottky interface of the gate electrode 101 to the channel layer 13 when a gate voltage is applied. It is controlled by changing the thickness of the channel layer 13 in the depletion layer. The buffer leak current flowing between the source and the drain when the pinch-off voltage is applied to deplete the channel layer 13 is required to be 1 × 10 ⁻⁹ A or less.

According to the structure of the HEMT 1 of this embodiment described above, the oxygen δ doping layer is formed by forming the oxygen δ doping layer 12a at the interface between the semi-insulating substrate 11 and the additive-free buffer layer 12 that is an epitaxial layer. 12a acts as a resistance layer, and the buffer leakage current can be suppressed to 1 × 10 ⁻⁹ A or less.
In the first embodiment, the oxygen δ doping layer 12a is formed on the AlGaAs layer, but may be formed on the GaAs layer.

FIG. 2 shows a cross-sectional structure of a HEMT according to the second embodiment of the present invention.
In the first embodiment, the oxygen δ doping layer 12a is formed at the interface between the substrate 11 and the additive-free buffer layer 12, but in the HEMT 2 of the second embodiment, as shown in FIG. 12 (intermediate region of the additive-free buffer layer 12), an oxygen δ doping layer 12a is formed. Other configurations and structures are the same as those of the first embodiment shown in FIG.

Also by the structure of the HEMT 2 in FIG. 2, by forming the oxygen δ doping layer 12a in the additive-free buffer layer 12, the oxygen δ doping layer 12a acts as a resistance layer, and the buffer leakage current is reduced to 1 × 10 ⁻⁹ A. It becomes possible to suppress to the following.

  Compared with the oxygen δ-doping layer and the conventional oxygen uniform doping buffer layer, the oxygen δ-doping layer can be doped with oxygen at a higher concentration and can realize higher resistance. Furthermore, in the oxygen δ doping layer, oxygen can be doped efficiently in a narrow range, and the memory effect of oxygen remaining in the furnace can be suppressed.

  In addition, since the oxygen δ-doping layer can reduce the thickness of the buffer layer, the oxygen δ-doping layer is adopted in the structure in which the epitaxial layer having the HBT structure is interposed between the substrate and the epitaxial layer having the HEMT structure. Then, the HEMT structure epitaxial layer and the HBT structure epitaxial layer can be electrically separated (longitudinal direction), and the step between the HEMT device and the HBT device can be reduced.

  As the epitaxial growth technique, metal organic vapor phase epitaxy (MOVPE) and molecular beam vapor phase epitaxy (MBE) are used. MBE is a growth technique with excellent crystal controllability, but throughput is not increased because maintenance for maintaining the epitaxial growth environment in a high vacuum is essential. Therefore, MOVPE is often used in industrial production.

Hereinafter, a method for manufacturing a III-V compound semiconductor device using MOVPE will be briefly described.

FIG. 3 shows a MOVPE apparatus 20 used for epitaxial growth. The MOVPE apparatus 20 includes a reaction furnace 21 to which an exhaust unit 26 having a vacuum pump and an exhaust apparatus (not shown) is connected. The reaction furnace 21 includes a susceptor 22 on which a substrate 27 is placed, a heater 23 that heats the susceptor 22, a control shaft 24 that rotates and moves the susceptor 22, and a raw material that is obliquely or horizontally directed toward the substrate 27. A quartz nozzle 25 for supplying gas is provided. In addition, the reaction furnace 21 includes a TMG gas generator 31 that generates trimethylgallium (TMG) gas, a TMA gas generator 32 that generates trimethylaluminum (TMA) gas, and AsH ₃ gas as a source gas supply system. AsH ₃ gas generator 33 for generating, TMI gas generator 34 for generating trimethylindium (TMI) gas, and Si ₂ H ₆ gas generator for generating disilane (Si ₂ H ₆ ) gas for doping Si 35 and an O ₂ gas generator 36 that generates oxygen gas (O ₂ ) for doping oxygen is connected. The source gas supply system of the reaction furnace 21 is provided with a mass flow controller (not shown) for controlling the flow rate of the source gas. Hydrogen is used as the carrier gas (dilution gas). Further, the combination of raw material gases supplied to the reaction furnace 21 is changed according to the epitaxial layer grown on the substrate 27.

  The substrate 27 on which the epitaxial layer is grown is set on the susceptor 22 in the growth furnace 21, and the substrate 27 is heated by the heater 23. When the source gas is supplied into the growth furnace 21, the source gas is decomposed by heat, and an epitaxial layer grows on the substrate 27.

When i-GaAs is grown, trimethylgallium (Ga (CH ₃ ) ₃ ) as a Ga raw material and arsine (AsH ₃ ) as an As raw material are supplied to the substrate 27. In addition, another example of the Ga material is triethylgallium (Ga (CH ₃ CH ₂ ) ₃ ). Other examples of As raw materials include trimethylarsenide (As (CH ₃ ) ₃ ) and tertiary butylarsine (TBA).

When growing i-Al _0.25 Ga _0.75 As, Ga (CH ₃ ) ₃ , AsH _3, and trimethylaluminum (Al (CH ₃ ) ₃ ) as an Al source are supplied to the substrate 27. In addition, another example of the Al material is triethylaluminum (Al (CH ₃ CH ₂ ) ₃ ).

When growing i-In _0.20 Ga _0.80 As, Ga (CH ₃ ) ₃ , AsH _3, and trimethylindium (In (CH ₃ ) ₃ ) as an In raw material are supplied into the growth reactor 21.

In the case of growing n-Al _0.25 Ga _0.75 As, Ga (CH ₃ ) ₃ , AsH ₃ , Al (CH ₃ ) ₃ and disilane (Si ₂ H ₆ ) as an n-type dopant raw material are growth furnaces. 21 is supplied. Note that Si or S having a small diffusion coefficient in GaAs is often used for the carrier supply layer (n-Al _0.25 Ga _0.75 As).

When growing n-InGaAs, Ga (CH ₃ ) ₃ , In (CH ₃ ) ₃ , AsH ₃ and Si ₂ H ₆ as an n-type dopant material are supplied into the growth reactor 21.

Examples of n-type dopant elements include Si, S, selenium (Se), and tellurium (Te). Examples of the Si raw material include monosilane (SiH ₄ ) and disilane (Si ₂ H ₆ ). S raw material is hydrogen sulfide (H ₂ S). Se and Te raw materials include hydrogen selenide (H ₂ Se), hydrogen telluride (
H ₂ Te).
An oxygen gas is used as the oxygen dopant.

In addition, in the III-V group compound semiconductor device of the said embodiment, although HEMT was demonstrated,
The present invention is not limited to this, and can be applied to all of various FETs having a buffer layer.

Next, examples of the present invention will be described.
In this example, an HEMT epitaxial wafer shown in Table 1 below used for the HEMT1 (FIG. 1) of the first embodiment was manufactured. The substrate temperature during growth was 650 ° C., the pressure in the growth furnace was 10108 Pa (76 Torr), and hydrogen was used as the dilution gas. A GaAs substrate was used as the substrate.

In Table 1, “n−” and “i−” in the name of the epitaxial layer indicate that the epitaxial layer is n-type and semi-insulating, respectively.

An i-GaAs layer was grown directly on the semi-insulating GaAs substrate. Ga (CH ₃ ) ₃ and AsH ₃ were used for the growth of the i-GaAs layer. The flow rate of Ga (CH ₃ ) ₃ is 10.5 cm ³ / min, and the flow rate of AsH ₃ is 315 cm ³ / min. The growth rate was 0.4 nm / second.

Next, the i-GaAs layer was doped with oxygen by δ. At δ doping, Ga (C
The supply of H ₃ ) ₃ and AsH ₃ was stopped and oxygen was supplied. The flow rate of oxygen was 32 cm ³ / min. As a result of SIMS (secondary ion mass spectrometry) measurement, it was found that oxygen uptake was advanced by stopping the supply of the group V raw material. The oxygen concentration in the oxygen δ-doping layer (GaAs) was 2 × 10 ²⁰ cm ⁻³ and the thickness was 40 nm.

Next, an i-GaAs layer (buffer layer) was grown. The raw material flow rate was the same as that grown immediately above the substrate. That is, the flow rate of Ga (CH ₃ ) ₃ was 10.5 cm ³ / min, and the flow rate of AsH ₃ was 315 cm ³ / min.

Ga (CH ₃ ) ₃ , Al (CH ₃ ) ₃ and AsH ₃ were used for the growth of the i-Al _0.25 Ga _0.75 As layer (buffer layer, spacer layer and Schottky layer). The flow rates of Ga (CH ₃ ) ₃ , Al (CH ₃ ) ₃ and AsH ₃ were 5.3 cm ³ / min, 1.43 cm ³ / min and 630 cm ³ / min, respectively. The growth rate was 0.3 nm / second.

Ga (CH ₃ ) ₃ , In (CH ₃ ) ₃ and AsH ₃ were used for the growth of the i-In _0.20 Ga _0.80 As layer (channel layer). _{Ga (CH 3) 3, In} (CH 3) 3 and each flow AsH ₃ 5.3 cm ³ / min, it was 2.09cm ³ / min and 500 cm ³ / min. The growth rate was 0.5 nm / second.

For the growth of the n-Al _0.25 Ga _0.75 As layer (carrier supply layer), i-Al _0.25
In addition to Ga (CH ₃ ) ₃ , Al (CH ₃ ) ₃ and AsH ₃ used for the growth of Ga _0.75 As, Si ₂ H ₆ was used as an n-type dopant material. The flow rate of the dopant Si ₂ H ₆ is 7.
78 × 10 ⁻³ cm ³ / min. The flow rates of raw materials other than the dopant Si ₂ H ₆ are the same as in the case of the i-Al _0.25 Ga _0.75 As layer.

For the growth of the n-GaAs layer (Schottky layer), Ga (
In addition to CH ₃ ) ₃ and AsHs, Si ₂ H ₆ was used as an n-type dopant. Dopant S
The flow rate of i ₂ H ₆ is 1.47 × 10 ⁻⁴ cm ³ / min. The flow rates of raw materials other than the dopant Si ₂ H ₆ are the same as in the i-GaAs layer.

In the n-In _{0 → 0.50} Ga _{1 → 0.50} As layer (contact layer), the InAs mixed crystal ratio changes from 0 to 0.50, and In (CH ₃ ), Ga (CH ₃ ) ₃ , AsH ₃ , Si ₂ H
₆ was used. _{In (CH 3) 3, Ga} (CH 3) 3, AsH 3, each flow rate of growth at the start of the _Si 2 _{H 6} is 0 cm ³ / min, 5.3 cm ³ / min, 500 cm ³ / min, 1.2 × 10 ^-1 cm ³ / min, also each growth at the end of the flow rate 8.3 cm ³ / min, 5.3 cm ³ / min, 500 cm ³ / min, was 1.6 cm ³ / min.

In (CH ₃ ) ₃ , Ga (CH ₃ ) ₃ , AsH ₃ , and Si ₂ H ₆ were used for the growth of the n-In _0.50 Ga _0.50 As layer (contact layer), and their flow rates were respectively 8.3cm ³ / minute, 5.3cm ³ / minute, 500cm ³ / minute, was 1.6cm ³ / min. Growth rate is 0.5n
m / sec.

FIG. 4 shows the results of measuring the gate voltage Vg and the source-drain current Ids for the HEMT fabricated using the epitaxial wafer of Table 1 obtained by the method of the above example. As shown in FIG. 4, the buffer leakage current when the pinch-off voltage was applied was 1 × 10 ⁻⁹ A or less, and it was confirmed that it had excellent switching characteristics.

Next, the optimum range for the oxygen concentration and thickness of the oxygen δ-doping layer was investigated. The results are shown in Table 2. The device reliability test in Table 2 is a measurement of the rate of change of the current gain β before and after flowing a current of 100 kA / cm ² .

As shown in Table 2, it was found that the oxygen concentration and thickness of the oxygen δ doping layer had the following influence on the device characteristics. When the oxygen concentration is less than 1 × 10 ¹⁹ cm ⁻³ and the thickness is less than 10 nm, the leakage current exceeds about 1 × 10 ⁻⁹ A and does not function sufficiently as a high resistance buffer layer. Further, when the oxygen concentration is 1 × 10 ²¹ cm ⁻³ or more and the thickness is greater than 100 nm, the leakage current exceeds 1 × 10 ⁻⁹ A, and the crystal of the epitaxial layer grown on the oxygen δ doping layer It has been found that the reliability deteriorates when the device is manufactured.

1 is a longitudinal sectional view showing a HEMT according to a first embodiment of the present invention. It is a longitudinal cross-sectional view which shows HEMT of the 2nd Embodiment of this invention. It is a schematic block diagram which shows the MOVPE apparatus for producing a III-V group compound semiconductor device. It is a figure which shows the relationship between the source-drain current and gate voltage in HEMT of an Example. It is a longitudinal cross-sectional view which shows the conventional HEMT.

Explanation of symbols

1, 2 HEMT
11 substrate 12 additive-free buffer layer 12a oxygen δ doping layer 13 channel layer 14 spacer layer 15 carrier supply layer 16 Schottky layer 17 contact layer 20 MOVPE apparatus 21 reactor 22 susceptor 23 heater 24 control shaft 25 quartz nozzle 26 exhaust part 27 substrate 31 TMG gas generator 32 TMA gas generator 33 AsH ₃ gas generator 34 TMI gas generator 35 Si ₂ H ₆ gas generator 36 O ₂ gas generator 101 Gate electrode 102 Source electrode 103 Drain electrode

Claims (5)

In a III-V compound semiconductor device including an undoped buffer layer between a single crystal substrate and a channel layer,
An oxygen δ doping layer is formed at an interface between the single crystal substrate and the additive-free buffer layer, at an interface of the additive-free buffer layer on the single-crystal substrate side, or in the additive-free buffer layer. III-V group compound semiconductor device.   2. The III-V compound semiconductor device according to claim 1, wherein the additive-free buffer layer is a GaAs layer or an A1 GaAs layer. The oxygen δ-doping layer has an oxygen concentration in the range of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ and a thickness in the range of 10 nm to 100 nm. 3. The III-V compound semiconductor device according to 2. In a method for manufacturing a group III-V compound semiconductor device in which an epitaxial layer including an additive-free buffer layer and a channel layer is grown on a single crystal substrate,
Forming an oxygen δ-doping layer at the interface between the single crystal substrate and the additive-free buffer layer, at the interface between the additive-free buffer layer and the single-crystal substrate, or in the additive-free buffer layer. A method for producing a III-V compound semiconductor device.   5. The method of manufacturing a group III-V compound semiconductor device according to claim 4, wherein the oxygen [delta] doping layer is formed by supplying oxygen gas.