JPH03286540A - Velocity-modulation type field-effect transistor - Google Patents

Abstract

PURPOSE:To enable carrier transportation characteristics to be improved drastically by forming a channel layer which form first and second quantum wells which differ in saturation velocity and low electric field mobility of a carrier sandwiching a potential barrier layer with such a thickness that the carrier can transmit owing to tunnel effect. CONSTITUTION:1mum thick I-type (non-doped) Al0.48In0.52As buffer layer 2, 150Angstrom thick I-type InP quantum well channel layer 3, 50Angstrom thick I-type Al0.45In0.52As potential barrier layer 4, 100Angstrom thick I-type In0.53Ga0.47As quantum well channel layer 5, a 500Angstrom thick N-type Al0.48In0.52As electron supply layer 6 with an impurity concentration of 2X10<18>cm<-3> and 200Angstrom thick N-type In0.53Ga0.47As cap layer 7 are allowed to grow continuously on an InP substrate 1 by a molecular beam epitaxial growth method, etc. A gate electrode 8 forming a Schottky junction is formed at the center of a recessed part and a source electrode 9 and a drain electrode 10 which are in ohmic contact are formed at both sides.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a field effect transistor (FET) using a heterojunction.
ET), especially F with improved carrier transport properties.
It concerns the ET structure.

[Conventional technology]

An FET whose channel is a two-dimensional electron gas layer generated at the heterojunction interface between two semiconductor layers with different energy band gaps is called HEMT (High Electron
Mobility Transistor).

This is because the electron supply layer, which has a high carrier scattering and low mobility, is separated from the channel layer, so extremely high carrier mobility can be obtained.

Under actual operating conditions, a voltage of, for example, 2V is applied between the source and drain, so a high electric field is generated in a direction parallel to the channel.

In particular, in a submicron element with a gate length of 0225 μm, the electric field strength reaches 80 kV on average.

Movement in momentum space occurs due to acceleration, and the conduction band electrons, which were traveling in the first valley with high drift velocity (electron mobility) at low energies, move to the second valley with low electron mobility at high energies). Intervalle
y transfer), the effective electron velocity decreased significantly, and the inherent high low-field mobility of HEMT could not be fully utilized.

Okichina and Sugiyama proposed a method for alleviating the deterioration of carrier transport characteristics caused by such an electric field effect in Japanese Patent Publication No. 14971/1983.

As a prior art, the FET structure will be explained with reference to FIG.

Semi-insulating GaAs substrate 1a, two-dimensional electron gas (2DEG)
), a type I (non-doped) GaAs channel layer 2a, a type A CGaAs potential barrier layer 3a,
Type I GaAs channel layer (quantum well layer) 4a, type A,
RGaAs spacer layer 5a, N-type AfflGaAs electron supply layer 6a, N-type GaAs surface packed crystal (cap) layer 7a
It consists of

Furthermore, a gate electrode 8 forming a Schottky junction with the surface crystal layer 7a, and a source electrode 9 and a drain electrode 10 forming ohmic contacts are formed.

FIG. 6 shows a band diaphragm under the gate of this device.

In the region where the channel electric field is low, the 2DEG is a ■-type Ga
It is generated only in the A s channel layer 2a.

When the electrons are further accelerated, the I-type GaAs channel layer 4
Real space transition to a (Rea I 5pace trans
fer) to disperse the electron concentration in the thin layer channel at high electric fields, thereby alleviating the increase in channel electric field and the accompanying velocity saturation.

[Problem to be solved by the invention]

In the conventional technology, the real space transition of electrons in a high electric field is used to suppress an increase in electron concentration in a channel and alleviate electric field concentration.

However, in order to suppress the saturation of the electron velocity based on this principle, it is necessary to reduce the electric field strength to several kV/cm or less.

In a device with a gate length of 0.25 μm, this corresponds to o and iv in terms of drain voltage, and such low voltage operation of the FET is not practical due to problems such as noise margin. In order to take advantage of the characteristics of such devices, low temperatures, which are far from practical, must be used.
Low voltage operation is required.

[Means to solve the problem]

The velocity modulated field effect transistor of the present invention has first and second quantum wells with different carrier saturation velocities and low field mobilities, sandwiching a potential barrier layer thick enough to allow carriers to pass through by tunneling. A channel layer of eggplant is formed.

[Effect]

Figure 4 shows the electric field strength dependence of electron drift velocity in major compound semiconductors.

InP can be used as a channel to improve the saturation speed, but InP has low low electric field mobility and high low electric field mobility.
7A s has a low saturation rate.

Real space transition type F with two channels like the conventional technology
In the ET structure, InGaAs with high low electric field mobility is used as the first channel layer in which electrons travel under a low electric field, and InP with high saturation speed is used as the second channel layer in which electrons travel under a high electric field. If used, effectively InG
It becomes possible to achieve both the low electric field mobility of aAs and the saturation speed of InP.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

I-type (non-doped) AJ7o, as
I no, 52As buffer layer 2, 150mm thick type InP quantum well channel layer 3, 50mm thick type A 4
o, 4g I n 0.52A S potential barrier layer 4, thickness 100 people mold ■n. 3. Gao47A
S quantum well cha quantum well channel made 52X1018cm
-', thickness 500 people N type A 1 (1,4g I n
092AS electron supply layer 6, thickness 200 N-type In (
,,51Ga (1,47A) S cap layer 7 is continuously grown.

A gate electrode 8 forming a Schottky junction is formed in the center of the recessed portion, and a source electrode 9 and a drain electrode 10 forming ohmic contact are formed on both sides thereof.

A band diagram of this FET in a thermal equilibrium state is shown in FIG.

E, , E2 are ■-type InP channel layer 3, I-type InG
a As is each electronic ground level of the channel layer 5.

Since there is a conduction band discontinuity of about 230 meV between I n O,53G a 6.47A S and InP,
The bottom of the conduction band of the InGaAs quantum well layer 5 is deeper than the bottom of the InP quantum well layer 3 by about 230 meV.

FIG. 3(a) is a potential band diagram illustrating the operating state of the source end under the gate, and FIG. 3(b) is a potential band diagram illustrating the operating state of the drain end under the gate.

Since the source-train voltage (Vd, 〉 and gate-source voltage (V, , ) are applied, a potential difference V, , (X) occurs between the pseudo Fermi level in the channel and the Fermi level of the gate. .

When X=O, Vgc(X) is V as shown in Figure 3(a), and when X=L, it is V as shown in Figure 3(b).
) as shown in V,. (L,)=V,, -V0miV,d
becomes.

Assuming that subbands E and E2 intersect when V, , = Vc (constant), the channel and source are approximately at the same potential near the source under the gate, and V gcξV gs.

When Vo>Ve, E2 becomes El as shown in Figure 3(a).
Since the energy is lower, almost all the electrons travel in the I-type InGaAs channel layer 5.

Near the drain under the gate, the drain-source voltage v
d, y gc becomes smaller, and V□CξV□=V
g 11 V dB.

Therefore, V□×V. Then, as shown in Figure 3(b),
El has lower energy than E2, and is type InP
The occupancy probability of the channel layer 3 becomes higher than the occupancy probability of the ■type ■nGaAs channel layer 5.

Under bias conditions such as V□ and Vc<Vg, many electrons travel through the ■-type InGaAs channel layer 5 near the source under the gate, but conversely, many electrons travel through the I-type InP channel layer 3 near the drain. Starts running.

In this way, it has become possible to achieve both the high low electric field mobility of InGaAs and the high saturation speed of InP.

In this example, Gao47I no, 53A s
/ Although InP-based semiconductors were used, similar effects can be obtained by combining other compound semiconductors.

〔Effect of the invention〕

In a field effect transistor in which a pair of quantum well layers arranged adjacent to each other with a tunnel barrier in between are used as channels, and carriers can be transferred from one quantum well layer to the other quantum well layer by a field effect, the negative quantum well layer is By constructing the quantum well layer with a material with high low-field carrier mobility and configuring the other quantum well layer with a material with high carrier saturation mobility, we were able to significantly improve the carrier transport characteristics of field-effect transistors. .

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of the present invention, and FIG. 2 is a potential band diagram at thermal equilibrium of an embodiment of the present invention.
FIG. 3(a) is a potential band diagram showing the operation of the source end under the gate in one embodiment of the present invention, and FIG. 3(b) is a potential band diagram showing the operation of the drain end under the gate in one embodiment of the present invention. Figure 4 is a graph showing the dependence of electron drift velocity on electric field strength, and Figure 5 is a graph showing the dependence of electron drift velocity on electric field strength.
A cross-sectional view of the ET, FIG. 6, is a potential band diagram of a high performance FET according to the prior art. 1... InP substrate, 1a... Semi-insulating GaAs substrate, 2-I type A, &InAsInAsInAsInAs parafluid 11. channel layer, 3... type InP channel layer,
3a...I type AJGaAs barrier layer, 4...I type A
JInAs barrier layer, 4a--I type GaAs
Channel layer, 5...1 type InGaAs channel layer,
5a・I type AJGaAs spacer layer, 6・N type AJ
InAs electron supply layer, 6a--N-type AfIGaAs electron supply layer, 7...N-type InGaAs cap layer, 7a
...N-type GaAs surface crystal layer, 8...gate electrode,
9... Source electrode, 10... Drain electrode, 11.
11a... Two-dimensional electron gas channel, 12... Ionized donor 13... Lower end of conduction band, 14... Fermi level, 14a... Electron density distribution, 15...
Pseudo-Fermi level, 16...quantization level.

Claims (1)

[Claims] 1. A first layer that serves as a channel layer with a potential barrier layer having a thickness that allows carriers to pass through by tunneling effect;
In a field effect transistor in which a second quantum well layer is formed and a charge is controlled by applying an electric field parallel to the channel layer, the distribution of carriers traveling in the channel layer changes as the channel electric field increases. A transition can be made from the well layer to the second quantum well layer, and the saturation velocity of carriers in the second quantum well layer is higher than the saturation velocity of carriers in the first quantum well layer. Velocity modulated field effect transistor. 2. The velocity modulated field effect transistor according to claim 1, wherein the low electric field mobility of carriers in the first quantum well layer is larger than the low electric field mobility of carriers in the second quantum well layer. 3. The first quantum well layer is I_xGa_1_-_xAs(
3. The velocity modulation field effect transistor according to claim 2, wherein 0≦x≦1) and the second quantum well layer is InP.