KR960015324B1 - Field effect transistor - Google Patents
Field effect transistor Download PDFInfo
- Publication number
- KR960015324B1 KR960015324B1 KR1019930013819A KR930013819A KR960015324B1 KR 960015324 B1 KR960015324 B1 KR 960015324B1 KR 1019930013819 A KR1019930013819 A KR 1019930013819A KR 930013819 A KR930013819 A KR 930013819A KR 960015324 B1 KR960015324 B1 KR 960015324B1
- Authority
- KR
- South Korea
- Prior art keywords
- channel
- field effect
- effect transistor
- graded
- ingaas
- Prior art date
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 239000000470 constituent Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 230000027756 respiratory electron transport chain Effects 0.000 claims 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 18
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 17
- 230000004888 barrier function Effects 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 230000004807 localization Effects 0.000 description 3
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
제 1 도는 종래의 이중구조 FET의 구조도.1 is a structural diagram of a conventional dual structure FET.
제 2 도는 종래의 이중구조 FET의 동작특성을 밴드다이어그램으로 나타낸 도면.2 is a band diagram showing the operation characteristics of a conventional dual structure FET.
제 3 도는 본 발명의 FET구조를 밴드다이어그램으로 나타낸 도면.3 is a band diagram showing the FET structure of the present invention.
제 4 도는 본 발명의 실시예들을 도시한 도면.4 illustrates embodiments of the present invention.
본 발명은 MODFET(Modulation-doped field deefect transistor), MISFET(Metal-Insulator-Semiconductor FET), MESFET(Metal-Semiconductor FET)등과 같은 3전극을 갖는 반도체 고체소자에 관한 것으로, 특히 전자구속을 위한 채널(channel)이 동일한 전자분포를 이루도록 전도대 포텐셜(potential)을 그레이디드(graded)하게 한 전계효과 트랜지스터에 관한 것이다.The present invention relates to a semiconductor solid-state device having three electrodes, such as a modulation-doped field deefect transistor (MODFET), a metal-insulator-semiconductor FET (MISFET), a metal-semiconductor FET (MESFET), and the like, and particularly, a channel for electron confinement. It relates to a field effect transistor in which the conduction band potential is graded so that the channels have the same electron distribution.
종래의 이중구조(Hetero-Structure) FET(Field Effect Transistor)는 제 1 도에 도시된 바와같은 구조를 갖는다. 즉 GaAs기판(11)상에 AlGaAs버퍼층이나 스페이서/전자공급층(Electron supplying layer)/배리어의 적층막중의 어느 하나(10)가 형성되고, 그위에 InGaAs 채널(8), AlGaAs스페이서(7), AlGaAs 전자공급층(6), AlGaAs배리어(5)가 차례로 형성되며, 이위의 소정부분에 GaAs캡층(4)이 형성되고, 그 상부의 소정영역에 소오스(1), 드레인(2) 및 게이트(3)가 각각 형성된 구조로 되어 있다.A conventional hetero-structure field effect transistor (FET) has a structure as shown in FIG. That is, any one of the AlGaAs buffer layer, the spacer / electron supplying layer / barrier lamination film 10 is formed on the GaAs substrate 11, and the InGaAs channel 8, the AlGaAs spacer 7, An AlGaAs electron supply layer 6 and an AlGaAs barrier 5 are formed in turn, and a GaAs cap layer 4 is formed on a predetermined portion thereon, and a source 1, a drain 2, and a gate () on a predetermined region thereon. 3) is formed respectively.
상기 구조의 FET소자는 AlGaAs/InGaAs층이 이종접촉면(Hetero-interface)에서 발생하는 전도대의 밴드갭 차이(△Ec)에 의해서 전자 가스(Electron gas)가 InGaAs 채널(8)에서 구속되게 된다.In the FET device having the above structure, the electron gas is constrained in the InGaAs channel 8 by the band gap difference ΔEc of the conduction band generated at the hetero-interface of the AlGaAs / InGaAs layer.
이때, 소오스(1)에서 드레인(2)쪽으로의 전류의 흐름은 게이트(3) 전압에 의해 변조되어진다.At this time, the flow of current from the source 1 toward the drain 2 is modulated by the gate 3 voltage.
그러나 상기 구조에서는 양자우물내에서의 전자가 이종접합면 부근에 집중되어 분포하기 때문에 고주파나 고출력 영역에서 제한 받게 된다. 즉, 채널내에서 전자가스가 이종접합면에 국부적을 분포되는 것은 결함이나 산란의 원인이 된다.However, in the above structure, electrons in the quantum well are concentrated and distributed near the heterojunction surface, thereby being restricted in the high frequency or high power region. That is, the distribution of electron gas locally on the heterojunction surface in the channel causes defects and scattering.
종래 FET소자의 동작특성을 밴드다이어그램으로 살펴보면 제 2 도와 같다.The operation characteristics of the conventional FET device are as shown in the second diagram.
제 2 도(a)는 단일 모듈레이션 도우프드(single modulation-doped) FET의 경우이고, (b)는 이중 모듈레이션 도우프드(Double modulation-doped) FET의 경우로서, 각각 AlGaAs 전자 공급층(14, 22)으로부터 나온 전자(15, 25)는 AlGaAs/InGaAs층의 밴드갭 차이에 의해 도시된 바와같이 삼각형의 양자우물안에 구속되어 이종접합면에 국부적으로 분포하게 되므로 접합면특성에 민감해진다.Figure 2 (a) is for a single modulation doped FET, (b) is for a double modulation-doped FET, each of the AlGaAs electron supply layers 14, 22 The electrons 15 and 25 from) are constrained in the junction surface properties because they are constrained in the triangular quantum wells as shown by the band gap difference between the AlGaAs / InGaAs layers and are locally distributed in the heterojunction.
이와 같은 소자에서는 상기와 같은 국부화에 의해서 전자의 이동도가 낮아지고 항복전압도 낮아지게 되며, 고출력 응용을 위해 전자가스(18, 25)를 증가시킬수록 이와 같은 국부화는 더 심각해지며, 동시에 이종접합에 가까와지게 된다. 따라서 이와같은 형태의 MODFET등은 고속 및 고출력 동작이 불안해지게 된다.In such a device, the mobility of electrons and the breakdown voltage are lowered by the localization as described above, and as the electron gas 18 and 25 are increased for high power application, such localization becomes more serious. You will get close to a heterojunction. Therefore, the high speed and high output operation of this type of MODFET becomes unstable.
이와 같은 문제점을 해결하기 위하여 아카자키(Akazaki)등은 "IEEE Electron Device Letters : Vol 3, June, 1992"에 이종접합으로부터 떨어져서 전자가스 밀도의 최대치를 유지하도록 하기 위해 낮은 밴드갭을 갖는 매우 얇은 InAs층을 채널에 삽입하는 방법을 제안하였다.To solve this problem, Akazaki et al. Described in "IEEE Electron Device Letters: Vol 3, June, 1992" a very thin InAs with a low bandgap to keep the maximum of electron gas density away from heterojunctions. A method of inserting a layer into a channel is proposed.
전자가스가 이종접합면에 국부적으로 분포되는 것을 막기 위해 채널에 InAs층을 삽입한 상기 구조는 상술한 문제점을 해결하나, 종래 구조에서 이종접합 산란(scattering)이 문제되지 않는 대신에 다른층을 삽입함으로써 생기는 새로운 접합면에서 산란이 발생되므로 소자특성을 저하시키는 새로운 원인이 되며, 이는 종래의 문제점만큼 심각한 결함이 된다.The structure in which the InAs layer is inserted into the channel to prevent the electron gas from being locally distributed on the heterojunction surface solves the above-mentioned problems, but in the conventional structure, the heterojunction scattering is not a problem. Scattering occurs at the new junction surface, which is a new cause of deterioration of device characteristics, which is as serious as a conventional problem.
본 발명은 상술한 문제점들을 해결하기 위하여 GaAs기판위에 AlGaAs배리어에 의해 형성된 InGaAs채널 또는 InP 기판위에 AlInAs/InGaAs 조합과 같은 Ⅲ-Ⅴ족 화합물로 된 그레이디드(graded)채널을 갖는 구조의 FET를 제공한다.The present invention provides a FET having a structure having a graded channel of a group III-V compound such as an InGaAs channel formed by an AlGaAs barrier on a GaAs substrate or an AlInAs / InGaAs combination on an InP substrate to solve the above problems. do.
이를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.This will be described in detail with reference to the accompanying drawings.
제 3 도에 본 발명의 FET 구조를 밴드다이어그램으로 나타내었다.In FIG. 3, the FET structure of the present invention is shown by a band diagram.
(a)는 그레이디드 스트레인드 싱글도우프도(graded-straind single-doped)MODFET인 경우이고, (b)는 그레이디드 스트레인드 더블 도우프드(graded-strained double-doped)MODFET인 경우이다.(a) is a case of a graded strained single-doped MODFET, and (b) is a case of a graded strained double-doped MODFET.
(a)의 구조에서 게이트(26)아래의 배리어(27)는 0.15∼0.45의 FET몰량(molefraction)을 갖는 언도우프드 AlGaAs로 형성되며 그 두께는 100∼500Å 정도이다. 전자공급층(28)은 XA1이 0.0∼0.45인 n-도우프드 AlGaAs로 형성되며 그 두께가 0.0∼200Å 정도이며, 스페이서층(29)은 XA1이 0.0∼0.45Å인 두께 0.0∼200Å 정도인 언더우프도 AlGaAs로 형성된다.In the structure of (a), the barrier 27 under the gate 26 is formed of undoped AlGaAs having a molefraction of 0.15 to 0.45 and the thickness thereof is about 100 to 500 mW. Electron supply layer 28 is about the thickness of 0.0~200Å formed in the n- dough peudeu X A1 is 0.0~0.45 AlGaAs, the spacer layer 29 is approximately the thickness of the X A1 0.0~0.45Å 0.0~200Å Phosphorus underwoofer is also formed of AlGaAs.
양자우물채널(30)은 X=0.0∼0.34인 그레이디드(graded)In 조성을 갖는 InxGa1-xAs로 형성되며 In의 몰량(mole fraction)에 따라 50∼500Å의 범위에서 그 두께가 조절된다.The quantum well channel 30 is formed of In x Ga 1-x As having a graded In composition in which X = 0.0 to 0.34, and its thickness is controlled in the range of 50 to 500 microns according to the mole fraction of In. do.
이와 같이 그레이디드 스트레인드 포텐셜 형태(graded-strained potential shape)는 0.0∼0.35의 In그레이딩(grading)조성에 따라 사각형, 포물선, 또는 V형태가 된다.Thus, the graded strained potential shape becomes square, parabolic, or V-shaped depending on the composition of In Grading of 0.0 to 0.35.
이중 모듈레이션 도우프디(double modulation-doped) FET의 경우를 도시한 제 3 도(b)는 2개의 전자공즉층(36)과 스페이서층(37) 및 배리어(35)를 가지며 (a)와 동일한 조성의 채널을 갖는다.FIG. 3 (b) shows a case of a double modulation-doped FET, which has two electron-immune layers 36, a spacer layer 37 and a barrier 35, of the same composition as (a). Has a channel.
본 발명의 FET는 InGaAs채널과 AlGaAs스페이서/배리어사이의 전도대의 차이가 전자구속을 위한 전위장벽을 만들 수 있도록 형성하게 되는데 이때 InGaAs의 밴드갭은 다음과 같이 In조성물의 함수로써 나타낼 수 있다.The FET of the present invention is formed so that the difference in conduction band between the InGaAs channel and the AlGaAs spacer / barrier can create a potential barrier for electron confinement. The band gap of InGaAs can be expressed as a function of In composition as follows.
Eg(InxGa1-xAs)=1.424-1.337x+0.27x2 E x (In x Ga 1-x As) = 1.424-1.337x + 0.27x 2
채널내의 전도대 프로파일은 In 조성비를 조절함으로써 조절이 가능하다.The conduction band profile in the channel can be adjusted by adjusting the In composition ratio.
본 발명의 포텐셜 프로파일에서, 전자는 채널 중심부에 몰려 분포하게 되며 종래와 같이 이종접합의 산란등에 민감하게 반응하지 않게 된다.In the potential profile of the present invention, the electrons are concentrated in the center of the channel and are not sensitive to scattering of heterojunctions as in the prior art.
이와 같이 그레이디드 조성(graede composition)특성을 갖춘 스트레인드층(strained-layer)채널을 채용함으로써 이종접합으로부터 떨어지게 하여 양자우물을 중간에 전자가스를 집중하여 구속함으로써 이동도의 감소없이 전자 전송되도록 하는 소자를 얻는다.As such, a strained-layer channel having a graded composition characteristic is employed to separate it from heterojunctions, thereby concentrating and restraining quantum wells in the middle so that electrons can be transmitted without reducing mobility. Get
또한, 채널에서 전자분포가 넓어짐에 따라 항복전압도 증가하게 된다. 따라서 결국 본 발명의 소자는 접합산란에 기인한 이동도의 감소와 전자의 국부화에 의한 항복전압의 감소를 동시에 해결할 수 있게 된다.In addition, as the electron distribution in the channel widens, the breakdown voltage also increases. Therefore, the device of the present invention can simultaneously solve the decrease in mobility due to junction scattering and the breakdown voltage due to localization of electrons.
즉, 종래구조의 접합산란등에 민감한 채널구조를 개선하고 전자분포를 균일하게 함으로써, 고속, 고출력 소자를 구현할 수 있게 된다.That is, by improving the channel structure sensitive to the junction scattering and the like of the conventional structure and uniform electron distribution, it is possible to implement a high speed, high output device.
상기 그레이디드 채널을 형성하는 Ⅲ-Ⅴ족 화합물은 에피성장에 의해서 형성되며, 상기한 AlGaAs/InGaAs 외에도 AlGaAs/InGaAs, GaInP/InGaAs, AlGaAs/GaInP/InGaAs AlGaAs/GaInP/InGaAs, InP/GaAsP 등을 사용할 수 있다.Group III-V compounds forming the graded channel are formed by epitaxial growth, and in addition to AlGaAs / InGaAs, AlGaAs / InGaAs, GaInP / InGaAs, AlGaAs / GaInP / InGaAs AlGaAs / GaInP / InGaAs, InP / GaAsP, etc. Can be used.
다음에 본 발명의 실시예들로서, 본 발명의 그레이디드 스트레인드(graded-strainde)채널을 제 1 도(a)의 단일 모듈레이션 도우프드(single modulation-doped) FET에 적용할 수 있고, 또한 제 4 도(a)에 도시한 바와 같이 이중모듈레이션 도우프드(double modulation-doped) FET에 적용할 수 있다.Next, as embodiments of the present invention, the graded-strainde channel of the present invention may be applied to the single modulation-doped FET of FIG. As shown in FIG. (A), the present invention can be applied to a double modulation-doped FET.
또한, 제 4 도(b)에 도시한 게이트와 채널사이에 AlGaAs 같은 절연층이나 배리어를 갖는 도우프드 InGaAs 그레이디드 스트레인드 채널(doped InGaAs graded-strained channel)이나 제 4 도(c)에 도시한 배리어가 없는 도우프드 InGaAs 스트레인드(doped InGaAs graded-strained)채널을 갖는 소자등에 적용될 수 있다.In addition, a doped InGaAs graded-strained channel having an insulating layer or barrier such as AlGaAs between the gate and the channel shown in FIG. 4 (b) or the channel shown in FIG. The present invention can be applied to devices having barrier-free doped InGaAs graded-strained channels.
이상 상술한 바와같이 본 발명에 의하면, 채널의 전류밀도(sheet carrier)를 증가시켜도 전자이동도가 감소되지 않는 고속전자 트랜지스터구조가 실현되므로 고출력, 고속동작이 가능한 트랜지스터를 구현할 수 있게 된다.As described above, according to the present invention, a high-speed electronic transistor structure in which the electron mobility is not reduced even if the current density (sheet carrier) of the channel is increased is realized, thereby enabling a transistor capable of high output and high speed operation.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930013819A KR960015324B1 (en) | 1993-07-21 | 1993-07-21 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930013819A KR960015324B1 (en) | 1993-07-21 | 1993-07-21 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950004591A KR950004591A (en) | 1995-02-18 |
| KR960015324B1 true KR960015324B1 (en) | 1996-11-07 |
Family
ID=19359723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930013819A KR960015324B1 (en) | 1993-07-21 | 1993-07-21 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960015324B1 (en) |
-
1993
- 1993-07-21 KR KR1019930013819A patent/KR960015324B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950004591A (en) | 1995-02-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5285087A (en) | Heterojunction field effect transistor | |
| US5705827A (en) | Tunnel transistor and method of manufacturing same | |
| US6992319B2 (en) | Ultra-linear multi-channel field effect transistor | |
| US5495115A (en) | Semiconductor crystalline laminate structure, forming method of the same, and semiconductor device employing the same | |
| US5811844A (en) | Low noise, high power pseudomorphic HEMT | |
| US5081511A (en) | Heterojunction field effect transistor with monolayers in channel region | |
| US4916498A (en) | High electron mobility power transistor | |
| US5023674A (en) | Field effect transistor | |
| US4558337A (en) | Multiple high electron mobility transistor structures without inverted heterojunctions | |
| EP0051271B1 (en) | Heterojunction semiconductor device | |
| US5105241A (en) | Field effect transistor | |
| JPH04230042A (en) | Field-effect transistor | |
| US5907164A (en) | InAlAs/InGaAs heterojunction field effect type semiconductor device | |
| US4807001A (en) | Heterojunction field-effect device | |
| JP2611735B2 (en) | Heterojunction FET | |
| US4600932A (en) | Enhanced mobility buried channel transistor structure | |
| US4903091A (en) | Heterojunction transistor having bipolar characteristics | |
| US5751029A (en) | Field-effect semiconductor device having heterojunction | |
| US6121641A (en) | Compound semiconductor field-effect transistor with improved current flow characteristic | |
| KR960015324B1 (en) | Field effect transistor | |
| US5206528A (en) | Compound semiconductor field effect transistor having a gate insulator formed of insulative superlattice layer | |
| JPS6214105B2 (en) | ||
| JP3158467B2 (en) | InAlAs / InGaAs heterojunction structure field effect transistor | |
| US5583353A (en) | Heterojunction field effect transistor | |
| JPH09237889A (en) | Semiconductor crystal laminate and semiconductor device using the laminate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20010926 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |