JPS62245681A - Negative differential resistance field-effect tran-sistor - Google Patents
Negative differential resistance field-effect tran-sistorInfo
- Publication number
- JPS62245681A JPS62245681A JP8931086A JP8931086A JPS62245681A JP S62245681 A JPS62245681 A JP S62245681A JP 8931086 A JP8931086 A JP 8931086A JP 8931086 A JP8931086 A JP 8931086A JP S62245681 A JPS62245681 A JP S62245681A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- electrons
- differential resistance
- negative differential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 3
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- 239000000654 additive Substances 0.000 abstract 4
- 230000000996 additive effect Effects 0.000 abstract 4
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000005868 electrolysis reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7727—Velocity modulation transistors, i.e. VMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、高速の電子移動度を有し、かつ負性微分抵抗
の機能をも有する電解効果トランジスタに関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a field effect transistor that has high-speed electron mobility and also has a negative differential resistance function.
（従来の技術）
従来、電解効果型のトランジスタにおいて負性微分抵抗
を発現させる技術として、アイ、イー、イー・イー・エ
レクトロン・デバイス・レターズ（ＩＥＥＥ。(Prior Art) Conventionally, a technique for developing negative differential resistance in a field effect transistor has been proposed by the International Electron Device Letters (IEEE).
Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｌｅｔｔｅｒｓ）誌
１９８３年ＥＤＬ４巻３３４頁に記載されているような
技術が知られている。これは第３図に示す素子構造にお
いてソース電極３１とドレイン電極３２間の電子走行チ
ャンネル３３内の電子パを加速さ゛せて電子温度を」二
昇させ、これによって電子を電子走行チャンネル３３か
ら熱的に溢れさせ、半導体層３４を通して半導体層３５
へ熱的に拡散させ、ソース電極３１とドレイン電極３２
間で電流に寄与する電子数を少なくせしめ、この結果、
負性微分抵抗を得んとするものである。A technique described in Electron Device Letters, 1983, EDL, Vol. 4, p. 334 is known. This accelerates the electron particles in the electron transit channel 33 between the source electrode 31 and drain electrode 32 in the device structure shown in FIG. to overflow the semiconductor layer 35 through the semiconductor layer 34.
The source electrode 31 and the drain electrode 32 are thermally diffused into
This reduces the number of electrons that contribute to the current between
The purpose is to obtain negative differential resistance.
（発明が解決しようとする問題点）
しかしながら、上記記載の技術による良性微分抵抗を示
す電解効果トランジスタは、電解によって加速された電
子（ホットエレクトロン）の熱的拡散過程を利用するた
め、応答速度が低いという欠点を有する。本発明の目的
は、高速の電子移動度を有する電解効果トランジスタに
おいて、負性微分抵抗の機能も有する素子構造を提供す
ることにある。(Problems to be Solved by the Invention) However, the field effect transistor exhibiting benign differential resistance based on the above-mentioned technology uses a thermal diffusion process of electrons (hot electrons) accelerated by electrolysis, so the response speed is low. It has the disadvantage of being low. An object of the present invention is to provide an element structure that also has a negative differential resistance function in a field effect transistor having high-speed electron mobility.
（問題を解決するための手段）
本発明は、第１の半導体層に順次積層された第２、第３
、第４、第５の半導体層を少なくとも含む半導体積層構
造と、その上部に設置されたソース、ドレイン、ゲート
の各金属電極を備え、第５の半導体層がｎ型にドープさ
れ、第４の半導体層は不純物をドープされず、かつ層厚
が電子の平均自由行程程度であり、第３の半導体層は第
４の半導体層よりも狭い禁制帯幅を有しがっ層厚が電子
の平均自由行程程度であり、第１の半導体層は、第２の
半導体層より狭く第３の半導体層よりも広い禁制帯幅を
有し、かつ層厚が電子の平均自由行程程度であり、かつ
第３の半導体層よりも厚く、かつ不純物がドープされ、
半導体層面にそって電流を流せしめる手段を有する負性
微分抵抗電解効果トランジスタである。(Means for Solving the Problems) The present invention provides a second and third
, a semiconductor stacked structure including at least fourth and fifth semiconductor layers, and source, drain, and gate metal electrodes placed on top of the semiconductor layer structure, wherein the fifth semiconductor layer is n-doped and the fourth semiconductor layer is doped with n-type. The semiconductor layer is not doped with impurities and has a layer thickness approximately equal to the mean free path of electrons, and the third semiconductor layer has a narrower forbidden band width than the fourth semiconductor layer and has a layer thickness approximately equal to the average free path of electrons. The first semiconductor layer has a forbidden band narrower than the second semiconductor layer and wider than the third semiconductor layer, and the layer thickness is about the mean free path of electrons, and thicker than the semiconductor layer of No. 3 and doped with impurities,
This is a negative differential resistance field effect transistor having means for causing current to flow along the surface of a semiconductor layer.
（作用）
以下、図面を用いて本発明による負性微分抵抗電解効果
トランジスタの作用を説明する。まず本発明による負性
微分抵抗電解効果トランジスタのゲート電極付近のエネ
ルギーバンド構造を、ゲート電極に電位が加えられてい
ない場合について第２図（ａ）に示す。ここで横軸方向
は積層方向であり、縦軸はエネルギーである。第２図の
２２の領域の２６（■）は、電子を半導体層２３に供給
して正に帯電した不純物を表わす。半導体層２３．２５
は層厚が電子の平均自由行程程度（数１０人〜数１ｏｏ
Ａ）であるため、これは量子井戸であり、これに供給さ
れた電子はこの量子井戸の量子準位２７に蓄積され、半
導体層２３゜２５の積層面に平行な方向に拡がり、２次
元的電子気体を形成する。ゲート電極２１に電位が加え
られていないとき、半導体層２５の量子準位は半導体層
２３の量子準位よりも高エネルギー側にあるように半導
体層２５の伝導バンド端を半導体層２５の組成により設
定しであるので、電子は半導体層２５にはほとんど移動
しない。また本構造においては電子は不純物ドープをし
ていない半導体層２８によって不純物位置から隔離され
、不純物による散乱を受けないため、半導体２３の層面
には電子は半導体層２８がない場合と比べて高速の移動
度を有する。次にゲート電極２１に負電位を加えるとゲ
ート付近のエネルギーバンド構造は第２図（ｂ）のよう
になる。(Function) Hereinafter, the function of the negative differential resistance field effect transistor according to the present invention will be explained using the drawings. First, the energy band structure near the gate electrode of the negative differential resistance field effect transistor according to the present invention is shown in FIG. 2(a) when no potential is applied to the gate electrode. Here, the horizontal axis direction is the stacking direction, and the vertical axis is the energy. 26 (■) in the region 22 in FIG. 2 represents an impurity that supplies electrons to the semiconductor layer 23 and is positively charged. Semiconductor layer 23.25
The layer thickness is about the mean free path of an electron (several 10 to several 100
A) Therefore, this is a quantum well, and the electrons supplied to it are accumulated in the quantum level 27 of this quantum well, spread in a direction parallel to the laminated plane of the semiconductor layers 23° 25, and become two-dimensional. Forms an electronic gas. The conduction band edge of the semiconductor layer 25 is adjusted by the composition of the semiconductor layer 25 so that when no potential is applied to the gate electrode 21, the quantum level of the semiconductor layer 25 is on the higher energy side than the quantum level of the semiconductor layer 23. Since this is the setting, electrons hardly move to the semiconductor layer 25. In addition, in this structure, electrons are isolated from the impurity position by the semiconductor layer 28 that is not doped with impurities and are not scattered by the impurities. It has mobility. Next, when a negative potential is applied to the gate electrode 21, the energy band structure near the gate becomes as shown in FIG. 2(b).
このとき各半導体層には電解が積層方向に加わるが、電
解によって半導体層２３．２５における量子準位２７は
それぞれ低エネルギー側へ移動する。しかるに本構造で
は半導体層２５の層厚を半導体層２３の層厚よりも大き
くしているため、量子準位の低エネルギー側への移動量
は半導体層２３よりも半導体層２５の方が大きい。この
ため電解によって半導体層２５の量子準位のエネルギー
は半導体層２３の量子準位のエネルギーよりも低くなり
、電子は半導体層２４を量子力学的にトンネル効果で通
り抜けて半導体層２５の量子準位に蓄積される。半導体
層２５は不純物をドープされているため、この半導体層
内では不純物散乱により電子の移動度は低減し、これに
より半導体層面方向の電流が小さくなるため負性微分抵
抗が発現される。このように電子の走行チャンネル（半
導体層２３及び半導体層２５）を２つ設け、その間の電
子の移動を量子力学的なトンネル効果で行わせしめるこ
とが本発明の負性微分抵抗トランジスタの最も重要な点
であり、これによって、電子のホットエレクトロン化と
その熱的拡散によってソース電極とドレイン電極間のキ
ャリア密度を実効的に減少させることを利用する従来の
技術によ°る負性微分抵抗を示す電解効果トランジスタ
よりも高速のスイッチング応答速度を得ることができる
。At this time, electrolysis is applied to each semiconductor layer in the stacking direction, but the electrolysis causes the quantum levels 27 in the semiconductor layers 23 and 25 to move to the lower energy side. However, in this structure, since the thickness of the semiconductor layer 25 is made larger than that of the semiconductor layer 23, the amount of movement of the quantum level toward the lower energy side is larger in the semiconductor layer 25 than in the semiconductor layer 23. Therefore, due to electrolysis, the energy of the quantum level of the semiconductor layer 25 becomes lower than the energy of the quantum level of the semiconductor layer 23, and the electrons pass through the semiconductor layer 24 by quantum mechanical tunneling effect and reach the quantum level of the semiconductor layer 25. is accumulated in Since the semiconductor layer 25 is doped with impurities, the mobility of electrons in this semiconductor layer is reduced due to impurity scattering, and this reduces the current in the plane of the semiconductor layer, resulting in negative differential resistance. The most important aspect of the negative differential resistance transistor of the present invention is to provide two electron travel channels (semiconductor layer 23 and semiconductor layer 25) and to allow electron movement between them to be performed by quantum mechanical tunneling effect. This shows negative differential resistance according to the conventional technology that utilizes hot electronization of electrons and their thermal diffusion to effectively reduce the carrier density between the source and drain electrodes. A faster switching response speed than a field effect transistor can be obtained.
（実施例）
以下第１図の実施例により本発明による負性微分抵抗電
解効果トランジスタの構成ならびに電気的特性について
説明する。本実施例はＣｒをドープした表面が（１００
）面の半絶縁性ＧａＡｓ基板１９上に分子線エピタキシ
ー（ＭＢＥ）法と真空蒸着により作成した。(Example) The structure and electrical characteristics of a negative differential resistance field effect transistor according to the present invention will be explained below with reference to the example shown in FIG. In this example, the Cr-doped surface is (100
) was fabricated on a semi-insulating GaAs substrate 19 by molecular beam epitaxy (MBE) and vacuum evaporation.
まず上記半絶縁性ＧａＡｓ基板１９にＭＢＥ法により順
次厚さｌｐｍのノンドープＧａＡｓバッファ層１８、厚
す２００人のＣｒドープＡｌ□、ＩＧａｏ０ｇＡｓ層１
７（第１の半導体層）、厚さ５０人のノンドープＡ１０
．３ＧａＯ，７Ａｓ層１６（第２の半導体層）、厚さ１
００人のノンドープＧａＡｓ層１５（第３の半導体層）
、厚さ１００人のノンドープＡ１ｏ、３Ｇａｏ、７Ａｓ
スペーサ一層２０、厚さ５００人のＳｉドープｎ型Ａｌ
ｏ、３Ｇａ□。First, on the semi-insulating GaAs substrate 19, a non-doped GaAs buffer layer 18 with a thickness of lpm, a Cr-doped Al□ layer with a thickness of 200 nm, an IGao0gAs layer 1
7 (first semiconductor layer), non-doped A10 with a thickness of 50 people
．． 3GaO, 7As layer 16 (second semiconductor layer), thickness 1
00 non-doped GaAs layer 15 (third semiconductor layer)
, 100 thick non-doped A1o, 3Gao, 7As
Spacer layer 20, thickness 500 Si-doped n-type Al
o, 3Ga□.
７Ａｓ層１４（第４の半導体層、Ｓｉのドーピング量は
２刈０１８ｃｍ−３）及び厚さ５００人のｎ型ノンドー
プＧａＡｓ層１３を成長させたあと、その上面に真空蒸
着によりともに厚さ１１１ｍ、長さ２ｐｍ、幅３００１
１ｍのゲート電極１２、ソース電極１０及びドレイン電
極１１を設置した。ゲート電極部１２はまずＴｉを蒸着
させ（厚さ０．７ｐｍ）、次にｐｔを蒸着させて（厚さ
０．６ｐｍ）、最後にＡｕを蒸着させて（厚さ０．６ｐ
ｍ）作成した。ソース電極部１０とドレイン電極部１１
はともにまずＡｕＧｅを蒸着させ（厚さ１１１ｍ）、次
にＡｕを蒸着させて（厚さ１１１ｍ）作成した。ソース
電極１０とゲート電極１２間の距離及びドレイン電極１
１とゲート電極１２間の距離はともに２ｐｍとした。ｎ
型ノンドープＧａＡｓ層１３は電極が容易に形成される
ように設けたものである。After growing a 7As layer 14 (fourth semiconductor layer, Si doping amount is 2.018 cm-3) and a 500-layer n-type non-doped GaAs layer 13, a layer of 111 m thick was formed on the upper surface by vacuum evaporation. Length 2pm, width 3001
A gate electrode 12, a source electrode 10, and a drain electrode 11 each having a length of 1 m were installed. The gate electrode part 12 is formed by first depositing Ti (thickness: 0.7 pm), then depositing PT (thickness: 0.6 pm), and finally depositing Au (thickness: 0.6 pm).
m) Created. Source electrode section 10 and drain electrode section 11
Both were made by first depositing AuGe (111 m thick) and then depositing Au (111 m thick). Distance between source electrode 10 and gate electrode 12 and drain electrode 1
The distance between the gate electrode 1 and the gate electrode 12 was both 2 pm. n
The non-doped GaAs layer 13 is provided so that an electrode can be easily formed.
上述のプロセスにより作成した本発明による負性微分抵
抗電解効果トランジスタのドレイン電極１２とソース電
極１１の間に一定の電圧０．５Ｖを印加しておき、ゲー
ト電圧−ＶＧ［Ｖ］を印加し、ゲート電圧（ＶＧ）の変
化に対するドレイン電流（ＩＤＳ）の変化量ｇｍ＝ａＩ
ｎｓ／９Ｖａをｌｐｍゲート幅当たりで７７にのもとで
測定すると、Ｖ＝１．０Ｖ前後でｇｍが４００ｍ５から
一８００ｍ５へ急激に変化し負性微分抵抗が観測された
。このときのスイッチング時間はｌｐｓ以下と見積られ
る。ｉ范釆のＧａＡｓ−ＭＥＳＦＥＴではスイッチング
時間は最高でも数１００ｐｓであった。また上述のドレ
イン電流の急激な変化の前後でのドレイン電流の最大値
と最小値の比は約３０であった。また上述の過程におけ
る電子移動度は７７にでの測定の結果１ Ｘ １０５ｃ
ｍ２／Ｖから５ Ｘ １０３ｃｍ”／Ｖに変化している
ことがわかり、ドレイン電流に寄与する電子の濃度には
変化は見られなかった。A constant voltage of 0.5 V is applied between the drain electrode 12 and the source electrode 11 of the negative differential resistance field effect transistor according to the present invention produced by the above process, and a gate voltage -VG [V] is applied, Amount of change in drain current (IDS) with respect to change in gate voltage (VG) gm = aI
When measuring ns/9Va at 77 per lpm gate width, gm suddenly changed from 400m5 to 1800m5 around V=1.0V, and negative differential resistance was observed. The switching time at this time is estimated to be less than lps. The maximum switching time of the conventional GaAs-MESFET was several 100 ps. Further, the ratio of the maximum value to the minimum value of the drain current before and after the above-described rapid change in the drain current was about 30. Also, the electron mobility in the above process is 1 x 105c as measured at 77
It was found that the concentration changed from m2/V to 5 x 103 cm''/V, and no change was observed in the concentration of electrons contributing to the drain current.
さらにゲート電圧がＯｖから一〇、８Ｖまででは負性微
分抵抗を示さず、従来の電解効果トランジスタと同じ機
能を有するが、ｌｐｍゲート幅当たりのｇｍの値として
４００ｍ５が得られ（７７Ｋ）、これは従来のＧａＡｓ
−ＭＥＳＦＥＴの値（通常１００ｍ８前後）を凌ぐ値で
ある。このことは本発明による負性微分抵抗電解効果ト
ランジスタがトランジスタ動作の点においても従来のＧ
ａＡｓ−ＭＥＳＦＥＴに比べて高速性及び低消費電力性
に優れることを意味する。Furthermore, when the gate voltage is from Ov to 10.8V, it does not show negative differential resistance and has the same function as a conventional field effect transistor, but the value of gm per lpm gate width is 400m5 (77K). is conventional GaAs
- This value exceeds the value of MESFET (usually around 100m8). This means that the negative differential resistance field effect transistor according to the present invention is superior to the conventional G in terms of transistor operation.
This means that it is superior in high speed and low power consumption compared to aAs-MESFET.
（発明の効果）
このように本発明による負性微分抵抗電解効果トランジ
スタは、ゲート電圧の印加により高速かつ低消費電力の
電解効果トランジスタとして機能し、しかも特定のゲー
ト電圧の前後で負性微分抵抗による高速のスイッチング
素子としても機能し、高速論理素子等への応用に活用さ
れる。(Effects of the Invention) As described above, the negative differential resistance field effect transistor according to the present invention functions as a high-speed and low power consumption field effect transistor by applying a gate voltage, and has a negative differential resistance before and after a specific gate voltage. It also functions as a high-speed switching element and is used for applications such as high-speed logic elements.
第１図は本発明による負性微分抵抗電解効果トランジス
タの構造図である。第２図は本発明による負性微分抵抗
電解効果トランジスタのゲート電極付近のエネルギーバ
ンド構造をしめす図で（ａ）はゲート電極に電位が加え
られていない場合、（ｂ）はゲート電極に負電位を加え
た場合の図である。第３図は従来の電解効果トランジス
タの構造を示す図である。
第１図において
１０ソース電極（厚さｌｐｍ、長さ２１１ｍ）１１ドレ
イン電極（厚さｌｐｍ、長さ２ｐｍ）１２ゲート電極（
厚さｌｐｍ、長さ２ｐｍ）１３ｎ型ノンド一プＧａＡｓ
層（厚さ５００人）１４ Ｓｉドープｎ型Ａ１０，３Ｇ
ａＯ，７Ａｓ層（厚さ５００人）１５ノンド一プＧａＡ
ｓ層（厚さ１００人）゛１６ノジドープＡｌ００３Ｇａ
ｏ、７Ａｓ層（厚さ５０人）１７ＣｒドープＡｌ□、Ｉ
Ｇａ□、ｇＡｓ層（厚さ２００人）１８ノンド一プＧａ
Ａｓバツフア層（厚さｌｐｍ）１９半絶縁性ＧａＡｓ基
板
２０ノンドープＡＩ□、３Ｇａ□、７Ａｓスペ一サ一層
（厚さ１００人）
第２図において
２１ゲート電極
２２ｎ型半導体層（電子供給層）
２３量子井戸層
２４障壁層
２５°量子井戸層
２６イオン化した不純物
２７電子の量子準位
２８ノンド一プ半導体層
第３図において
３１ソース電極
３２ドレイン電極
３３電子走行チャンネル
３４半導体層
予 １ 図
１θ、ソース＠鍾
Ｕ、 ドレイン電茨台
１２、 ゲ°−ト電紘FIG. 1 is a structural diagram of a negative differential resistance field effect transistor according to the present invention. Figure 2 shows the energy band structure near the gate electrode of the negative differential resistance field effect transistor according to the present invention. (a) shows when no potential is applied to the gate electrode, and (b) shows when the gate electrode has a negative potential. This is a diagram when adding . FIG. 3 is a diagram showing the structure of a conventional field effect transistor. In Figure 1, 10 source electrodes (thickness lpm, length 211m), 11 drain electrodes (thickness lpm, length 2pm), 12 gate electrodes (
(thickness lpm, length 2pm) 13n type non-dipped GaAs
Layer (500 layers thick) 14 Si-doped n-type A10,3G
aO, 7As layer (500 layers thick) 15 non-doped GaA
S layer (thickness 100 layers)゛16 Nodido doped Al003Ga
o, 7As layer (thickness 50) 17Cr-doped Al□, I
Ga□, gAs layer (200 layers thick) 18 non-doped Ga
As buffer layer (thickness lpm) 19 Semi-insulating GaAs substrate 20 Non-doped AI□, 3Ga□, 7As spacer one layer (thickness 100 layers) 21 Gate electrode 22 N-type semiconductor layer (electron supply layer) 23 Quantum well layer 24 Barrier layer 25° Quantum well layer 26 Ionized impurity 27 Electron quantum level 28 Non-doped semiconductor layer 31 Source electrode 32 Drain electrode 33 Electron travel channel 34 Semiconductor layer 1 Figure 1 θ, source @Zhong U, Drain Electric Ibaradai 12, Gate Electric Hiro
Claims (1)
５の半導体層を少なくとも含む半導体積層構造と、その
上部に設置されたソース、ドレイン、ゲートの各金属電
極を備え、第５の半導体層がｎ型にドープされ、第４の
半導体層は不純物をドープされず、かつ層厚が電子の平
均自由行程程度であり、第３の半導体層は、第４、第５
の半導体層よりも狭い禁制帯幅を有し、かつ層厚が電子
の平均自由行程程度であり、第２の半導体層は、第３の
半導体層よりも広禁制帯幅を有し、かつ層厚が電子の平
均自由行程程度であり、第１の半導体層は、第２の半導
体層より狭く第３の半導体層より広い禁制帯幅を有し、
かつ層厚が電子の平均自由行程程度であり、かつ第３の
半導体層よりも厚く、かつ不純物がドープされ、半導体
層面にそって電流を流せしめる手段を有する負性微分抵
抗電解効果トランジスタ。A semiconductor stacked structure including at least second, third, fourth, and fifth semiconductor layers sequentially stacked on a first semiconductor layer, and each metal electrode of a source, a drain, and a gate installed on the semiconductor layer, The fifth semiconductor layer is n-type doped, the fourth semiconductor layer is not doped with impurities, and has a layer thickness approximately equal to the mean free path of electrons, and the third semiconductor layer is n-type doped.
The second semiconductor layer has a narrower forbidden band width than the third semiconductor layer, and the layer thickness is about the mean free path of electrons, and the second semiconductor layer has a wider forbidden band width than the third semiconductor layer, and The thickness is about the mean free path of electrons, and the first semiconductor layer has a forbidden band width that is narrower than the second semiconductor layer and wider than the third semiconductor layer,
A negative differential resistance field effect transistor having a layer thickness approximately equal to the mean free path of electrons, thicker than the third semiconductor layer, doped with an impurity, and having means for causing current to flow along the surface of the semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8931086A JPS62245681A (en) | 1986-04-17 | 1986-04-17 | Negative differential resistance field-effect tran-sistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8931086A JPS62245681A (en) | 1986-04-17 | 1986-04-17 | Negative differential resistance field-effect tran-sistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62245681A true JPS62245681A (en) | 1987-10-26 |
Family
ID=13967094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8931086A Pending JPS62245681A (en) | 1986-04-17 | 1986-04-17 | Negative differential resistance field-effect tran-sistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62245681A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0349703A2 (en) * | 1988-07-07 | 1990-01-10 | International Business Machines Corporation | Multilayer field-effect transistor |
| JPH03286540A (en) * | 1990-04-03 | 1991-12-17 | Nec Corp | Velocity-modulation type field-effect transistor |
| JP2001185559A (en) * | 1999-12-27 | 2001-07-06 | Natl Inst Of Advanced Industrial Science & Technology Meti | Negative resistance field-effect transistor |
| JPWO2007026616A1 (en) * | 2005-08-31 | 2009-03-26 | 独立行政法人科学技術振興機構 | Negative resistance field effect element and high frequency oscillation element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5851576A (en) * | 1981-09-22 | 1983-03-26 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6154670A (en) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | Semiconductor memory device |
-
1986
- 1986-04-17 JP JP8931086A patent/JPS62245681A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5851576A (en) * | 1981-09-22 | 1983-03-26 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6154670A (en) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | Semiconductor memory device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0349703A2 (en) * | 1988-07-07 | 1990-01-10 | International Business Machines Corporation | Multilayer field-effect transistor |
| JPH03286540A (en) * | 1990-04-03 | 1991-12-17 | Nec Corp | Velocity-modulation type field-effect transistor |
| JP2001185559A (en) * | 1999-12-27 | 2001-07-06 | Natl Inst Of Advanced Industrial Science & Technology Meti | Negative resistance field-effect transistor |
| JPWO2007026616A1 (en) * | 2005-08-31 | 2009-03-26 | 独立行政法人科学技術振興機構 | Negative resistance field effect element and high frequency oscillation element |
| US7652310B2 (en) | 2005-08-31 | 2010-01-26 | Japan Science And Technology Agency | Negative resistance field effect device and high-frequency oscillation device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2786327B2 (en) | Heterojunction field effect transistor | |
| US5677553A (en) | Semiconductor device strucutre having a two-dimensional electron gas and contact thereto | |
| KR890004959B1 (en) | Fet semiconductor device | |
| US4704622A (en) | Negative transconductance device | |
| JPH0821708B2 (en) | Semiconductor element | |
| JPH04112547A (en) | Velocity-modulation transistor | |
| JP2689057B2 (en) | Static induction semiconductor device | |
| JPH04118972A (en) | Semiconductor device | |
| JPS639388B2 (en) | ||
| JPS62245681A (en) | Negative differential resistance field-effect tran-sistor | |
| JPS5953714B2 (en) | semiconductor equipment | |
| JPS61147577A (en) | Complementary semiconductor device | |
| JPS59184573A (en) | Field effect transistor | |
| JPS62245680A (en) | Field-effect transistor | |
| JPH08316461A (en) | Field-effect semiconductor device | |
| JPS63161678A (en) | Field effect transistor | |
| JPH0311767A (en) | Velocity modulation type field-effect transistor | |
| JPH0230182B2 (en) | HANDOTAISOCHI | |
| JPH04277680A (en) | Tunnel transistor and manufacture of the same | |
| JPH0620142B2 (en) | Semiconductor device | |
| JPS61171179A (en) | Semiconductor coupled superconductive element | |
| JPS6196769A (en) | Field effect transistor | |
| JP2740166B2 (en) | Semiconductor laminated structure | |
| JPH06163599A (en) | Compound semiconductor heterojunction field-effect transistor | |
| JPS61248569A (en) | Hetrojunction field effect transistor |