GB2262385A

GB2262385A - Velocity modulation transistor

Info

Publication number: GB2262385A
Application number: GB9225785A
Authority: GB
Inventors: Atsushi Kurobe; Michael Pepper; Jeremy Burroughes; Jonathan E F Frost; Paul Michael Owen
Original assignee: Toshiba Cambridge Research Centre Ltd
Current assignee: Toshiba Europe Ltd
Priority date: 1991-12-13
Filing date: 1992-12-10
Publication date: 1993-06-16
Anticipated expiration: 2012-12-10
Also published as: GB9225785D0; JPH05251477A; GB2262385B; GB9126480D0

Abstract

A dual-gate velocity modulation transistor comprises an active layer 4 having first and second interfaces with a front barrier layer 5 and a back barrier layer 3, respectively situated either side of the active layer 4. The barrier layers have a conduction band energy at each interface, higher than the respective band energy of the active layer at each interface. The active layer 4 is formed so as to have a higher conduction band energy between the interfaces than at the interfaces. The transistor also includes source and drain contacts 11, 12 and front and back gates 13, 14. The structure may also be used as a back gate high electron-mobility transistor when the barrier layers abut doped layers as shown. <IMAGE>

Description

Velocity Modulation Transistor The present invention relates to a velocity modulation transistor (VMT), in which carrier mobility is controlled by externally applied voltages.

It is known that heterostructures such as GaAs/AlGaAs provide a so-called two dimensional electron gas (2DEG), in which the wavefunction perpendicular to the layers is quantised in energy and electrons are confined in the GaAs layer near the GaAs/AlGaAs hetero-interface. The electrons near the interface can move freely in a plane close and parallel to the interface and form a conduction channel.

By separating donor impurities from the electron conducting channel, i.e., by doping or the Al GaAs layer, the 2DEG exhibits a very high mobility (of the order of 106 cm2/Vs). This is utilized for making high speed field effect transistors, which are called HEMTs, (High Electron Mobility Transistors) or MODFETs (Modulation Doped Field Effect Transistors). The HEMT finds application in such areas as microwave amplifiers and high speed integrated circuits.

Figure 9 of the accompanying drawings shows the energy band diagram of an HEMT near the hetero-interface, Electrons are transferred to the interface from n-type doped AlGaAs layer and form a channel adjacent to the interface.

Electrons are quantised due to a triangular-like potential profile and occupy sub-bands. Figure 9 shows the lowest two sub-bands E1 and E2. The energy difference E21 = E2 - E1 is about 20 meV.

Therefore, when the carrier density is smaller than about 6xl01l/cm 2, only the ground-state sub-band is occupied. The carrier density is changed by the Schottky barrier formed at the surface.

The theoretical limits of operating speeds of conventional HEMTs have been analysed by H. Sakaki in (Japanese Journal of Applied Physics Vo. 21, No. 6, June 1982 p.L381). To improve on the speed of the conventional devices, this reference proposes a concept of velocity (or mobility) modulation. In ordinary field effect transistors, conductivity modulation AG is effected through the change of carrier density AN within a channel. This sets a speed limit of about 1 picosecond using high-velocity electrons (~ 2x107 cm/s) travelling over a channel distance of 0.2 Fm.

According to the velocity modulation concept, the channel conductivity G is modulated by the gate voltage mainly through a change of carrier mobility Ap, , the carrier density being maintained at a constant value.

This may be understood by considering the expression, aG=#aN+Na#L. The ordinary HEMT utilizes the first term on the right hand side, whilst the VMT utilises the second term. From this expression it is seen that in the VMT it is important to keep the large value of N and to realize large value of ap.

The VMT concept has been embodied as a dual-channel structure, as disclosed in the specification of Japanese patent TOKKAI-SHO 58-178572. This structure is also referred to as a back gate HEMT structure.

Figure 10 shows the layer structure and figure 11 the operating principle of the back gate HEMT. Two- channels A and B are respectively controlled by two back-to-back HEMT arrangements having respective gate electrodes designated Gate A and Gate B. The structure is formed on a substrate 105. A source 107 and a drain 109 are arranged at respective ends of both channels in contact therewith.

In each channel, the wavefunction perpendicular to the 2DEG plane is quantised and a single sub-band is occupied. All the carriers can be localised in the 2DEG of either channel A or channel B by positively biasing gate A and negatively biasing gate B (or vice versa).

In Figure 11, (b) shows the impurity distribution. In the remaining drawings, subscripts gA, gB etc denote the gates A and B. Thus, in (a) Vg#=Vg#=O, in (c) VgA=#V goE and in (d) V =-V =-V gB gA gB gO By the appropriate biasing of gates A and B, the carrier density can be constant between the state where all the carriers are in channel A and that where all the carriers are in channel B. The mobility of the carriers in each channel is different due to the impurity doping in the GaAs layer adjacent channel B and to the difference in surface roughness.

Therefore the mobility modulation can be achieved without changing the total carrier density, by transferring the carriers between the two channels in response to the switching potentials applied to the gate electrodes.

Since the inter-channel distance, which is typically less than 100 nm, can be smaller than the channel length, the device is able to operate at a higher speed than the conventional HEMT. It should be noted that the theory of operation of the back-gate HEMT device assumes that a single energy sub-band is occupied in each channel to enable switching between high and low mobility.

It is found in practice that with this previously proposed back-gate structure, it is not possible to achieve proper switching of the current flowing between drain and source. However, a solution to this problem of the previously proposed back-gate device has now been found, as provided by the present invention.

European Patent Specification EP-A-255 416 describes a dual channel heterostructure in which the channels are separated by an intermediate barrier layer within an active layer. The barrier layer is sufficiently thin to allow quantum tunnelling from one channel to the other.

To achieve different mobilities, in one channel the active layer is heavily doped and in the other it is undoped. Both channels are formed at interfaces having the same orientation.

The structure of the preceding paragraph is difficult to grow since during epitaxial growth, the high level of doped impurity tends to diffuse through the barrier layer into the undoped layer, reducing the mobility of the channel intended to have the high mobility.

It has now been found that a new kind of dual-channel VMT can be produced which is easier to fabricate and is not dependent on quantum tunnelling. Velocity modulation can be effected by transferring carriers between the two channels by application of appropriate front and back voltages.

Thus, a first aspect of the present invention provides a dual-gate velocity modulation transistor comprising an active layer, a front barrier layer forming a first hetero-interface with a first side of said active layer and a back barrier by forming a second hetero-interface with a second side of said active layer, said front and back barrier layers each having a conduction band energy at said first and second hetero-interfaces higher than the band energy of the active layer at said first and second hetero-interfaces, so as to form front and back conduction channels in the active layer respectively adjacent to said front and back hetero-interfaces, the active layer being so formed as to have a different conduction band energy between said first and second hetero-interfaces than adjacent to said first and second hetero-interfaces.

Whilst not wishing to be bound by any particular theory, the inventors have noted from experimental investigations on the conventional back-gate device that it behaves as if the carriers at one or other hetero-interface in the active layer occupy multiple energy sub-bands, ie with a ground-state sub-band and at least one excited sub-band.

In the known back gate HEMT structure, the conduction band edge of the active GaAs layer is flattened relative to that in an ordinary HEMT structure, since the GaAs layer is very thin, ie in the order of 100 nm.

As a result, it appears that the energy difference between the first excited sub-band and the ground sub-band is reduced and the higher bands spill into both channels, even when the carrier concentration is small.

Furthermore, it is likely that wavefunction of each channel quantum-mechanically overlaps and forms a low-lying excited state which extends over the both channels.

Figure 12 shows energy states at various bias conditions for front and back gate voltages, VA and VB, for a conventional structurally symmetric back gate HEMT. The thickness of the GaAs active layer is 100 nm and the carrier density is 3xlO11 cm 2. E and El,B are the energy levels at channel A and channel B, and Ex is the energy level of the excited energy state.

Figure 12 shows there is always an energy state extending into both channels, so that ideal mobility switching is prohibited. It should be noted that the gate voltage cannot be large, so that the field in the GaAs layer exceeds about 50kV/cm, because the leakage current between the channel and the gate increases.

It might be thought that a possible way to avoid the problems of the conventional back-gate device would be to make the GaAs layer thicker for example lpm.

However, such a device would not respond sufficiently quickly and so would be of no particular use. Another possibility could be to make the carrier density very low (less than 1x101l cm ), but that would reduce the conductance modulation, due to the relation, aG = NaCr.

Thus, it can be seen that it would not be possible to achieve a single sub-band in each channel, together with a high carrier density, by making obvious modifications to the conventional back gate HEMT structure described in JP 58-178572.

In general, in devices according to the present invention, a higher conduction band energy in the active layer between the hetero-interfaces is achieved by selection of the material from which the active layer is made and by manufacturing the device to have a certain spatial distribution of those materials.

One method is to arrange an appropriate material, for example Al, across the base material (eg GaAs) of the active layer; such the material has a distribution with a maximum between the hetero-interfaces. The material is chosen to increase the conduction band energy of the base material.

Alternatively, a material to raise the conduction band energy is arranged in one or more substantially discrete bands across the active layer, preferably with one band nearer to but spaced apart from the front hetero-interface. Preferably, a second band of such material is also arranged nearer to but spaced apart from the back hetero-interface with the barrier layer adjacent the back gate.

Alternatively or in addition to the higher conduction band layer, a quantum well layer may be situated in the active layer between and spaced apart from the hetero-interfaces. This quantum well layer comprises a material of lower band energy then the surrounding active layer.

Another alternative is to lower the conduction band energy in the active layer directly adjacent to both interfaces. If the active layer is GaAs, this could be done by incorporating In.

Typically, the active layer comprises an undoped or partially doped semiconductor. Particularly, adjacent the respective hetero-interfaces (corresponding to the two conduction channels) the active layer may be undoped or doped to have the same conductivity type.

The barrier layers may comprise a front barrier layer of n-type doped or partially n-type doped semi-conductor and a back barrier layer, formed of an undoped or an n-type doped semiconductor.

Yet again, the front barrier layer may comprise in p-type doped or partially p-type doped semiconductor and the back barrier layer may comprise an undoped or p-type doped semiconductor.

As mentioned above, the device according to EP-A-255 416 has a barrier layer in the active layer, so thin as to allow quantum tunnelling accross it. However, second aspect of the present invention provides a dual-gate velocity modulation transistor comprising an active layer having first and second interfaces with a front barrier layer and a back barrier layer, respectively situated either side of said active layer, the barrier layers having a conduction band energy at each interface, higher than the respective band energy of the active layer at each interface, so as to form a first conduction channel adjacent to said first interface and a second conduction channel adjacent to said second interface, a front gate electrode overlying said front barrier layer and a back gate electrode overlying said back barrier layer, at least one intermediate barrier or quantum well layer being provided within the active layer spaced apart from both interfaces, and if there is only one intermediate barrier or quantum well layer then it has a thickness sufficient substantially to prevent tunnelling thereacross, the at least one intermediate barrier or quantum well layer having a conduction band energy different from that of the surrounding active layer, the device being operable by transferring carriers between the first conduction channel adjacent to said first interface and a second conduction channel adjacent to said second interface by applying appropriate front and back gate voltages.

Regardless of the thickness of the intermediate barrier or quantum well layers, it is advantageous to provide at least two. Thus, a third aspect of the present invention provides a dual-gate velocity modulation transistor comprising an active layer having first and second interfaces with a front barrier layer and a back barrier layer, respectively situated either side of said active layer, the barriers layers having a conduction band energy at each interface, higher than the respective band energy of the active layer at each interface, at least two intermediate layers each independently for acting as a barrier or quantum well layer, each spaced apart from both interfaces and from each other and each having a conduction band energy different from that of the surrounding active layer.

The device according to EP-A-255 416 requires an intermediate barrier layer relatively near the mobility channel (front interface) so that the channels are close enough to permit quantum tunnelling. However, if the intermediate barrier (or quantum well) layer is thin enough, then electrons can 'tunnel" through to from a single conduction channel in the region of this layer and this layer can act as a scatterer for electrons in this single channel when appropriate gate voltages are applied. Thus, a fourth aspect of the invention provides a dual-gate velocity modulation transistor comprising an active layer having first and second interfaces with a front barrier layer and a back barrier layer nearer to a substrate than said front barrier layer, said front and back barrier layers being respectively situated either side of said active layer, the barrier layers having a conduction band energy at each interface, higher than the respective band energy at each interface, an intermediate barrier or quantum well layer being provided within the active layer, spaced apart from both interfaces and thin enough so that a single conduction channel can be formed in the region of said intermediate barrier or quantum well layer, the intermediate barrier or quantum well layer having a conduction band energy different from that of the surrounding active layer.

Preferably, in the device according to the fourth aspect of the invention, the intermediate layer is located nearer to the back barrier layer than the front barrier layer.

A fifth aspect of the invention provides a back gate HEMT structure having: an active layer, formed of an undoped or partially doped semiconductor; a front barrier layer, formed of n-type doped or partially n-type doped semiconductor, formed adjacent to one side of said active layer, having a higher conduction band edge at the first interface with said active layer compared to the conduction band edge of said active layer at said first interface, for forming the first conduction channel near said first interface;; a back barrier layer, formed of an undoped or n-type doped semiconductor, formed adjacent to the other side of said active layer, having higher conduction band edge at the second interface with said active layer compared to the conduction band edge of said active layer at said second interface, for forming the second conduction channel near said second interface, wherein said active layer contains a region, having higher conduction band edge material compared to the conduction band edge of said active layer at said first and second interface.

A sixth aspect of the invention provides a back gate HEMT structure having: an active layer, formed of an undoped or partially doped semiconductor, a front barrier layer, formed of p-type doped or partially p-type doped semiconductor, formed adjacent to one side of said active layer, having lower valence band edge at the first interface with said active layer compared to the valence band edge of said active layer at said first interface, for forming the first conduction channel near said first interface, a back barrier layer, formed of an undoped or p-type doped semiconductor, formed adjacent to the other side of said active layer, having lower valence band edge at the second interface with said active layer compared to the valence band edge of said active layer at said second interface, for forming the second conduction channel near said second interface, wherein said active layer contains a region, having higher valence band edge material compared to the valence band edge of said active layer at said first and second interface.

This invention will now be explained in more detail by the following detailed description of several preferred embodiments and with reference to the accompanying drawings, in which: Fig. 1 is a sectional view of a back gate HEMT VMT structure according to the present invention; Fig. 2 is a graph showing the Al mole fraction and the doping concentration of the active layer of the device shown in Fig. 1; Fig. 3 is a graph showing the Al mole fraction and the doping concentration of the active layer of a second back gate HEMT VMT structure according to the present invention; Fig. 4 is a graph showing the Al mole fraction and the energy band diagram of a third back gate HEMT VMT structure according to the present invention; Fig. 5 is a main part of a sectional view and the energy band diagram of a fourth back gate HEMT VMT structure according to the present invention;; Fig. 6 is a main part of a sectional view and the energy band diagram of a fifth back gate HEMT VMT structure according to the present invention; Fig. 7 a main part sectional view of a sixth back gate HEMT VMT structure according to the present invention; Fig. 8 is a main part sectional view and the energy band diagram of a seventh back gate HEMT VMT structure according to the present invention.

Fig. 9 is an energy band diagram for a conventional HEMT structure; Fig. 10 is a sectional view of the conventional back gate HEMT VMT structure described with reference to Figure 11; Fig. 11 explains the operating principle of a conventional back gate HEMT VMT structure; and Fig. 12 shows band diagrams and wavefunctions for conventional back gate HEMT VMT structures.

In the back gate structure shown in Fig. 1, an n -type GaAs buffer layer (0. 5mm thick) 2, undoped Alo 3Ga0 7As back barrier layer (100 nm thick) 3 and an AlGaAs active layer (60 nm thick) 4. On the other side of the active layer from the back barrier layer 4 is arranged a front barrier layer 5 comprising an undoped Al # 3Ga0 7As spacer layer (10 nm thick) 51 and an n-type doped (n = 8X1017 cm 3) Al 0. 3Ga0 7As layer (50 nm thick) 52. Finally, an undoped GaAs cap layer (10 nm) are successively grown on an n ±GaAs substrate 1.

The above structure is grown by MBE (Molecular Beam Epitaxy) or by MOCVD (Metal Organic Chemical Vapour Deposition) or by ALE (Atomic Layer Epitaxy). Ohmic contacts (source 11 and drain 12) are formed by deposition of GeAu and subsequent annealing.

It is important to prevent leakage current between the ohmic contacts and the back gate. Therefore, the alloying due to annealing should not penetrate down to the layer 2 and preferably stop at around the interface between layer 3 and 4. Using GeAu the annealing conditions are a temperature of 420 C and a time of 0. 8 seconds.

Back gate 14 is formed by ohmic contact to the substrate. Schottky metal such as PdAu is deposited to form the front gate 11.

Fig. 2 details the structure of the AlGaAs active layer in the structure shown in Fig. 1. The Al mole fraction increases step-wise by an amount of 0. 04 from both A and B interfaces toward the centre of the layer. The width of each step is 5 nm. This gives extra confinement for electrons at each interface and results in a single sub-band. Silicon is doped near the interface B (nsi=2xl0l7cm with a thickness of 5 nm) so that the conducting channel formed at the interface B is lower in mobility than that in the interface A. The doping also provides electrons in each channels, Fig. 3 illustrates another example for the active layer 4. The Al mole fraction is changed linearly (Fig. 3(a)) or with a parabolic profile (Fig. 3(b)).

Fig. 4 (a) shows another example for the active layer 4. Thin Alo #3Ga0 7As barrier layers 42 and 44 are located 10 nm away from the interface B and A, respectively. The thickness of the barrier layers is 3 nm.

In this example, quantum wells 41 and 45 are formed and the front and back gate allow a single sub-band, since the wavefunction is well quantised due to the barriers.

Fig. 4(b) shows the energy diagram when the front gate voltage is positive and the back gate voltage is negative. A ground sub-band wavefunction in layer 45 (100) is formed at the interface A and no state exists adjacent the interface B. Since the thickness of the barriers 42 and 44 is very thin, it is possible to transfer electrons from the layer 45 to the layer 41.

Figure 5 shows the layer structure and the band diagram for the next embodiment. An In, 1Ga0 gAs thin layers (10 nm width) 402 and 404 are located adjacent to the interfaces B and A, respectively.

Since InGaAs is lower in conduction band energy compared to GaAs, the InGaAs layers 401 and 402 form quantum wells. As a result, the carrier confinement is strong enough to allow single sub-band formation when the single channel is realised by applying appropriate gate voltages. Also, the barrier height of GaAs layer 402 and 403 is low to allow carriers to be transferred from one channel to another by under the influence of the external gate voltages.

Figure 6 shows an example in which the active layer is relatively thick and the back barrier 3 is undoped.

When the back barrier is undoped, the triangular-like potential profile for back channel electron becomes weaker. The device corresponding to Fig. 6 does not work at such high concentrations compared to the device of Figure 4, but it is easy to fabricate and works at lower carrier density.

The active layer 4 consists of an n-type doped GaAs layer 41 (n = 3xl017cm 3, 5 nm thick), an undoped AlAs thin barrier layer (0.5 nm thick) and an undoped GaAs layer (90 nm thick) 43. The GaAs layer 41 is thin enough for the wavefunction 200 have a high existence probability in the AlAs layer 42. Therefore, the AlAs layer acts as a confinement potential as well as a scatterer for electrons.

The doping concentration and the thickness of the semiconductor layers in the above embodiments can be changed if so wished. For example, an undoped AlGaAs layer 51 can be doped with n-type. The thickness of the active layer can be thinner so that the the transfer time from one channel to another is reduced. However, in this case the active layer should be large enough so that the two ground subbands at each interface do not mix quantum-mechanically, which means in GaAs/AlGaAs material systems that the thickness should be larger than about 20 nm. The AlGaAs back layer can be doped with n-type impurity. This is shown in Figure 7, as an example.

The AlGaAs back barrier layer consists of undoped AlGaAs layers (31 and 33) and an n-type AlGaAs layer 32. The thickness of undoped layers is 15 nm, and that of doped layer is 60 nm. The doping concentration for the layer 32 is 7.5x1011cm-2 .Alternatively, the width of layer 33 can be reduced to zero.

Figure 8 shows a quantum well layer 62 of lower band gap energy than the surrounding active layer 6 is placed in said active layer 6. This embodiment also suppresses a low energy extended state, as is the case of the embodiment shown in Fig. 6. When electrons are forced to populate the region adjacent the back barrier 3 by appropriately biasing front and back gate voltages, the electron wavefunction extends over this quantum well.

Since the quantum well layer consists of undoped InGaAs alloy, the mobility for this channel is reduced due to the allow scattering.

In case of the thin barrier inserted active layer in Fig. 6, it is difficult to design the structure so that the peak of the wave function is aligned with the thin barrier. On the other hand, with the structure shown in Figure 8, the peak of the wavefunction is easily arranged to locate in the quantum well, so that the scattering effect is maximised.

The width and the depth of the quantum well have to be arranged so that the electrons are weakly trapped and the bound state is easily forced to be unoccupied by the application of the external voltages. An example of the detailed design of the active layer 6 is as follows: undoped GaAs layer 61 (5nm), undoped In0 05Ga0 95AS quantum well 62 (5nm), and undoped GaAs layer (90nm).

It is possible to dope Si in the layer 62 or 61 to increase the scattering by the ionised impurities. In Figure 8, back barrier layer 32 is shown as n-type doped but in a modification of this embodiment, it can be undoped.

The explanation given above assumes that the carriers are electrons. However, the carriers could equally be holes. In that case, the n-type doping in the structure would be changed to p-type doping.

The present invention is not limited to the above embodiments. In addition to the GaAs/AlGaAs based materials, the present invention is effective for any suitable heterostructures capable of providing the appropriate conduction and valence band levels.

Examples are InxGa1- xAs/InxGa1-xAsyP1-y on an InP-substrate, InxGa1-xAs/InyAl1-y As on a GaAsor InP-substrate, InxGa1-xP/InxGa1-x)yAl1-y P on a GaAs-substrate, SixGe1-x /Si on an Si-substrate.

Furthermore, in the preferred embodiments hereinbefore described, the back gate is formed at the substrate-side surface. However, it is also possible to form the back gate at the top surface, ie, on the same side as the front gate. This can be done by making electricl isolation from layers 3 to 6, using such methods as etching and ion implantation, and by making ohmic contact to layer 2 from the top side surface.

Claims

1. A dual-gate velocity modulation transistor comprising an active layer, a front barrier layer forming a first hetero-interface with a first side of said active layer and a back barrier by forming a second hetero-interface with a second side of said active layer, said front and back barrier layers each having a conduction band energy at said first and second hetero-interfaces higher than the band energy of the active layer at said first and second hetero-interfaces, so as to form front and back conduction channels in the active layer respectively adjacent to said front and back hetero-interfaces, the active layer being so formed as to have a different conduction band energy between said first and second hetero-interfaces than adjacent to said first and second hetero-interfaces.

2. A transistor according to claim 1, wherein a conduction band energy enhancing material is distributed across the active layer so as to provide a conduction band energy maximum between the hetero-interfaces.

3. A transistor according to any preceding claim, wherein at least one discrete layer of conduction band energy enhancing material is arranged in the active layer, between and spaced apart from said first and second hetero-interfaces to form at least one intermediate barrier layer therein.

4. A transistor according to claim 3, wherein a second discrete layer of conduction band energy enhancing material is arranged closer to said second hetero-interface to form a second intermediate barrier layer therein.

5. A transistor according to any of claims 1 to 4, wherein at least one discrete layer of conduction band energy lowering material is arranged in the active layer, between and spaced apart from said first and second hetero-interfaces to form at least one intermediate quantum well layer therein.

6. A transistor according to claim 1 or claim 2, wherein a material to lower the conduction band energy of the active layer is arranged in the active layer directly adjacent to at least one of the first and second hetero-interfaces.

7. A transistor according to any preceding claim, wherein the regions of the active layer corresponding to said front and back conduction channels are both undoped.

8. A transistor according to any of claims 1-6, wherein the regions of the active layer corresponding to said front and back conduction channels respectively are both doped to have the same conductivity type.

9. A transistor according to any of claims 1-6 and 8, wherein at least one of the front and back barrier layers comprises a doped layer and an undoped spacer layer between the doped layer and the active layer.

10. A dual-gate velocity modulation transistor comprising an active layer having first and second interfaces with a front barrier layer and a back barrier layer, respectively situated either side of said active layer, the barrier layers having a conduction band energy at each interface, higher than the respective band energy of the active layer at each interface, so as to form a first conduction channel adjacent to said first interface and a second conduction channel adjacent to said second interface, a front gate electrode overlying said front barrier layer and a back gate electrode overlying said back barrier layer, at least one intermediate barrier or quantum well layer being provided within the active layer spaced apart from both interfaces, and if there is only one intermediate barrier or quantum well layer then it has a thickness sufficient substantially to prevent tunnelling thereacross, the at least one intermediate barrier or quantum well layer having a conduction band energy different from that of the surrounding active layer, the device being operable by transferring carriers between the first conduction channel adjacent to said first interface and a second conduction channel adjacent to said second interface by applying appropriate front and back gate voltages.

11. A dual-gate velocity modulation transistor comprising an active layer having first and second interfaces with a front barrier layer and a back barrier layer, respectively situated either side of said active layer, the barriers layers having a conduction band energy at each interface, higher than the respective band energy of the active layer at each interface, at least two intermediate layers each independently for acting as a barrier or quantum well layer, each spaced apart from both interfaces and from each other and each having a conduction band energy different from that of the surrounding active layer.

12. A dual-gate velocity modulation transistor comprising an active layer having first and second interfaces with a front barrier layer and a back barrier layer nearer to a substrate than said front barrier layer, said front and back barrier layers being respectively situated either side of said active layer, the barrier layers having a conduction band energy at each interface, higher than the respective band energy at each interface, an intermediate barrier or quantum well layer being provided within the active layer, spaced apart from both interfaces and thin enough so that a single conduction channel can be formed in the region of said intermmediate barrier or quantum well layer, the intermediate barrier or quantum well layer having a conduction band energy different from that of the surrounding active layer.

13. A transistor according to claim 12, wherein the intermediate barrier or quantum well layer is located nearer to said back barrier layer than to said front barrier layer.

14. A back gate HEMT structure having: an active layer (4), formed of an undoped or partially doped semiconductor; a front barrier layer (5), formed of n-type doped or partially n-type doped semiconductor, formed adjacent to one side of said active layer (4), having a higher conduction band edge at the first interface (A) with said active layer (4) compared to the conduction band edge of said active layer at said first interface (A), for forming the first conduction channel near said first interface (A);; a back barrier layer (3), formed of an undoped or n-type doped semiconductor, formed adjacent to the other side of said active layer (4), having higher conduction band edge at the second interface (B) with said active layer (4) compared to the conduction band edge of said active layer at said second interface (B), for forming the second conduction channel near said second interface (B), characterised in that said active layer contains a region, having higher conduction band edge material compared to the conduction band edge of said active layer at said first and second interface.

15. A back gate HEMT structure having: an active layer, formed of an undoped or partially doped semiconductor, a front barrier layer, formed of p-type doped or partially p-type doped semiconductor, formed adjacent to one side of said active layer, having lower valence band edge at the first interface with said active layer compared to the valence band edge of said active layer at said first interface, for forming the first conduction channel near said first interface, a back barrier layer, formed of an undoped or p-type doped semiconductor, formed adjacent to the other side of said active layer, having lower valence band edge at the second interface with said active layer compared to the valence band edge of said active layer at said second interface, for forming the second conduction channel near said second interface, characterised in that said active layer contains a region, having higher valence band edge material compared to the valence band edge of said active layer at said first and second interface.

16. A dual-gate velocity modulation transistor substantially as hereinbefore described in with reference to Figures 1-8 of the accompanying drawings.