GB2279806A - Ohmic contacts for semiconductor devices - Google Patents
Ohmic contacts for semiconductor devices Download PDFInfo
- Publication number
- GB2279806A GB2279806A GB9313876A GB9313876A GB2279806A GB 2279806 A GB2279806 A GB 2279806A GB 9313876 A GB9313876 A GB 9313876A GB 9313876 A GB9313876 A GB 9313876A GB 2279806 A GB2279806 A GB 2279806A
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- United Kingdom
- Prior art keywords
- buried layer
- interface
- layer
- heterostructure
- contact
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 13
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000037230 mobility Effects 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000013590 bulk material Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005283 ground state Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 230000005428 wave function Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
In a method for forming a shallow ohmic contact to a buried layer 3 of a semiconductor device, an opening is etched down to the interface 11 of the heterostructure 3, 5 and is overlaid with a contact material 33 which is diffused 37 into the structure to make contact with a 2-dimensional electron gas 15. The diffusion takes place during annealing and the device may be a HEMT. <IMAGE>
Description
SEMICONDUCTOR DEVICE AND METHOD OF MARING SAME
The present invention is concerned with a method of making an ohmic contact to a heterojunction-type semiconductor device and the device resulting from such method.
A typical heterojunction device is a high electron mobility effect transistor (HEMT). This uses a heterostructure such as GaAs/AlGaAs to create a so-called two dimensional electron gas (2DEG), in which the wavefunction perpendicular to the layers is quantised in energy and electrons are confined in the
GaAs layer near the GaAs/AlGaAs hetero-interface but can move freely in a plane close and parallel to the interface.
By separating donor impurities from the electron conducting channel, ie., by doping the AlGaAs layer, the 2DEG may exhibit very high mobilities (of the order of 106 cm2/Vs). This is utilized in HEMTs, MODFETs (Modulation Doped Field Effect Transistors) and the like. The HEMT finds application in such areas as microwave amplifiers and high speed integrated circuits.
In ordinary field effect transistors, conductivity modulation aG is effected through the change of carrier density aN within a channel. This sets a speed limit of about 1 picosecond using high-velocity electrons ( 2xiO7cm/s) travelling over a channel distance of 0. 2 pm.
Figure 1 of the accompanying drawings shows a typical
HEMT structure 1. This comprises an undoped GaAs active layer 3 above which, in order, are an undoped Al GaAs spacer layer 5 (e.g. 200A thickness), an n-doped
AlGaAs barrier layer 7 (e.g. with impurity concentration around 1018 cm 3, 400A thickness) and a cap layer 9 (e.g. 100k thickness).
Figure 2 shows the energy band diagram of the HEMT according to Figure 1. Electrons are transferred to the
AlGaAs/GaAs interface 11 from the doped barrier layer 7 and form a channel 13 in the active layer, adjacent to the interface in which the 2DEG 15 is confined.
However, carriers are free to move perpendicular to the layers so that a current can flow between a source 17 and drain 19, spaced apart and contacting the 2DEG in the buried active layer (see Figure 1) as respective ohmic contact regions 21,23.
A gate electrode 25 above the cap layer switches the current flowing between source and drain, by affecting the number of carriers. Electrons are able to occupy sub-bands in the potential well of the channel but if the carrier density is sufficiently small, only the ground-state is occupied. The Schottky barrier formed at the surface changes the carrier density.
Unfortunately, the abrupt energy level change at the interface, necessary for forming the potential well to contain the 2DEG, creates a significant problem for forming ohmic contacts for the source and drain.
Due to the high concentration of localised states at the
GaAs surface, the Fermi level under all conditions except UHV cleaving of the (110) facet is pinned near the centre of the bandgap. This results in the depletion of charge carriers near the surface in doped samples, with the depletion width depending on the inverse square root of the bulk material doping concentration. The high surface state density also results in an almost work-function independent Schottky barrier height between GaAs and all metals. Thus a metal contact made to n-doped GaAs will result in a non-ohmic contact (non-linear current versus voltage behaviour), even if the work-function of the metal is of the order of the electron affinity.
Conventionally, the two main techniques to form an ohmic contact with a GaAs layer are either to diffuse dopant in underneath the contact or to form another material phase between the contact and the GaAs which results in
Fermi level pinning near the conduction band. By diffusing a high concentration of dopant such as Ge into the surface region under the contact the depletion depth is reduced to such an extent that tunnelling through the barrier becomes the dominant transport mechanism. This gives ohmic behaviour over the current range of interest. There are many contact technologies that work using this effect such as GePd, GeAg and NiGeAu etc.
However, the formation of an ohmic contact to a HEMT structure is more complicated because of the buried abrupt junction (e.g. AlGaAs/GaAs) inherent in this structure. This barrier, especially at low temperatures is very effective in inhibiting current flow between the contact and the 2DEG even if the above condition is met.
Figure 3 is an energy diagram showing the effect of merely carrying out a conventional high dopant diffusion to a HEMT structure as shown in Fig. 1 to form the ohmic contacts 21,23. Whilst the effect of the Schottky barrier arising at the metal contact is greatly mitigated, the GaAs/AlGaAs interface still present a high and sharp barrier to conduction.
Moreover, in order to achieve ohmic contact to the heterostructure using the conventional methods, one either has to use a higher than normal diffusion temperature or else a higher than usual concentration of diffused dopant, so that the buried interface is "blurred". This results in a deep contact which for some devices, prevents them from functioning as intended.
One such device is a so-called velocity modulation transistor (VMT). A VMT is a derivative of the conventional HEMT. Switching of the source-to-drain current is achieved not by changing the number of carriers but by affecting their mobilities. A VMT typically has a pair of barrier layers sandwiching the active layer, with a respective gate electrode on either side. These are normally referred to as the front gate (on top of the structure) and the back gate (on the substrate side).
Using the conventional method, with (say) GeAu contacts, results in a leaky back gate. This makes it important to prevent diffusion of the dopant beyond the inverted hetero-interface.
We have now found a method of forming a shallow ohmic contact which overcomes this problem. Thus, the present invention provides a method of forming a shallow ohmic contact to a buried layer of a heterojunction
semiconductor device in which said buried layer is part of a heterostructure and forms an interface with an adjacent layer of the heterostructure such that the interface presents an abrupt energy barrier, the method comprising the steps of:
(i)etching a region of the heterostructure to expose the buried layer;
(ii)applying a contact material to the etched region to contact the buried layer; and
(iii)annealing the device to form an ohmic contact between the contact material and the buried layer.
The present invention also provides a heterojunction semiconductor device comprising a buried layer and an adjacent layer of a heterostructure defining an interface therebetween, an opening being provided in said heterostructure down to said buried layer, and a contact material overlying the opening and forming an ohmic contact with said buried layer.
The present invention is especially useful for forming ohmic contacts in HEMT or VMT structures. In terms of a
HEMT or VMT structure, a "shallow" ohmic contact means one extending down to but not substantially beyond the active layer of interest, ie, down to the 2DEG.
The present invention allows very shallow ohmic contacts to be formed and has been demonstrated to be capable of making contact to a 2DEG without contacting another layer which is separated by only a 200A Al GaAs barrier.
The contact materials used can be any materials usable to make conventional ohmic contacts with GaAs and other semiconductor materials. For devices intended to operate at low temperatures, GePd is greatly preferred, although this is not a requirement, the usual combinations may be used for example
NiInW, GeInW, GePd, NiGeAs, GeAg, etc..
As is well known, when for example GePd is used to make an ohmic contact with (say) n± GaAs, excess Ge is used as a layer on top of a Pd layer. On annealing, these two elements intermix and excess Ge diffuses into the wafer to displace Ga from some crystal sites.
First, some of the Ga reacts with Pd leaving vacant crystal sites, then Ge reacts with Pd. Finally, the excess Ge diffuses into the crystal structure and occupies the vacant Ga sites.
GePd is especially useful as the contact material for the present invention because this diffusion will occur at relatively low temperatures with GaAs, for example from 300 to 4000C. With the present invention, the Ge or analogous material can diffuse into the structure/sides of the opening to a depth of up to (say) from 50A to 250A, typically around 100A to form the ohmic contact.
It is advantageous, although not absolutely necessary, for the etched opening to extend below the interface.
Typically, it may extend from 50A to 250A, e.g.
around 100A below. The minimum etch depth is set by the tunneling distance which typically is about 100A shallower than the 2DEG. The maximum depth for practical purposes is about double the distance of the 2DEG.
To make selective ohmic contacts to a plurality of buried layers at different depths, e.g. to manufacture stacked devices, a plurality of openings may be etched to different depths, each with its own respective contact layer.
In general, the present invention is applicable not only to AlGaAs/GaAs systems but to any structure where there is a large band discontinuity, for example InGaAs/AlInAs or InGaAs/InP.
The present invention will now be explained in more detail by the following description of a preferred embodiment and with reference to the accompanying drawings in which:
Figure 1 shows a typical HEMT structure with conventional ohmic contacts;
Figure 2 is an energy diagram for the HEMT structure shown in Figure 1;
Figure 3 shows the effect on the energy diagram of a conventional diffusion process for making an ohmic contact to the 2DEG in the structure shown in Figure 1;
Figure 4 shows a first stage in carrying out a method according to the present invention;
Figure 5 shows a second stage of a method according to the present invention;
Figure 6 is a voltage versus resistance plot demonstrating selective ohmic contact to one or two 2DEGs; and
Figure 7 shows a further embodiment for effecting selective shallow ohmic contact to a plurality of buried layers at different depths.
Figure 4 shows a first stage of forming a shallow ohmic contact in accordance with the present invention. In
Figures 4 and 5, reference numerals in common with
Figure 1 denote the same features.
A heterostructure comprising the GaAs active layer 3, Al GaAs spacer layer 5, n-Al GaAs barrier layer 7 and GaAs cap layer 9 is grown in the normal way. Then, using a mask (not shown) to effect selective etching, a via 27 is etched into the structure. The bottom 29 of the via is about 100A below the interface 11.
Then, a Pd layer followed by a Ge layer in excess to the
Pd are applied over the inside of the via, typically with a ratio of Ge: Pd of 1: 1. 5 and with a thickness of about 500A. This layer overlaps the unetched rim 31 of the cap layer and is annealed at about 350 0C to form an ohmic contact layer 33 as shown in Figure 5.
This contact layer extends from the rim 31 to the bottom 29 of the via 27.
During the annealing process, the Ge diffuses through the bottom 29 and side walls 35 of the via to an extent of about 100A as denoted by the dotted line 37.
Numeral 15 shows where the 2DEG would be during operation of the device, at a depth of about 10A from the interface 11. It can be seen that the diffused Ge is at the same depth as the 2DEG to make the ohmic contact therewith.
The gate electrode 25 can be applied subsequent to formation of the ohmic contact.
To demonstrate the feasibility of making selective contact to only one 2DEG or two 2DEG's at adjacent interfaces, the resistance versus applied gate voltage was measured for a HEMT structure of the general kind shown in Figure 1. In this device, the first 2DEG was 700A below the upper surface of the structure and the second 2DEG was 400k below the first.
The results are shown in Figure 6. The curve labelled
A700(1) was obtained using a device where the via was etched to a depth about 100A above the first 2DEG.
The curve A700(4) is for an equivalent device in which the via was etched to a depth approximately equal to that of the second 2DEG. The discontinuity in the latter curve is indicative of ohmic contact being made to the second (lower) 2DEG.
The via can thus be etched to an appropriate depth to enable contact to a 2DEG of interest. This means that a plurality of 2DEGs at different depths can be selectively contacted by means of a series of vias etched to different depths. An example of such an arrangement is shown in Figure 7.
First, second and third 2DEGs are, in that order, formed in progressivly deeper buried layers and are denoted, respectively, by reference numerals 41, 43, 45, below the surface 47. To contact these, three vias 49, 51, 53 are etched to appropriate depths. Via 49 is the deepest and via 53 is the most shallow, with via 51 having a depth between the latter two.
Each via 49, 51, 53 is provided with a respective ohmic contact layer 55, 57, 59 extending to the bottom of each via in the same manner as the contact layer 33 is formed in the embodiment shown in Figures 4 and 5. The three ohmic contact layers 53, 57, 59 in the present embodiment respectively contact the first, second and third 2DEGs denoted by numerals 41, 43, 45 by virtue of the depths of the different vias.
Such a system can be applied to making selective contact to two or more buried layers and makes possible the vertical stacking of devices. The etching in such an arrangement fulfils two purposes as the unmetallised portion also serves to deplete the conducting layer, ensuring that adjacent layers are not shorted together by the ohmic contact.
In the light of this disclosure, modifications of the described embodiment as well as other embodiments, all within the scope of the appended claims will now become apparent to persons skilled in the art.
Claims (15)
1. A method of forming a shallow ohmic contact to a buried layer of a heterojunction semiconductor device in which said buried layer is part of a heterostructure and forms an interface with an adjacent layer of the heterostructure such that the interface presents an abrupt energy barrier, the method comprising the steps of:
(i)etching a region of the heterostructure to expose the buried layer;
(ii)applying a contact material to contact the buried layer; and
(iii)annealing the device to form an ohmic contact with the buried layer.
2. A method according to claim 1, wherein the etching step is effected to etch the buried layer beyond the interface.
3. A method according to claim 1 or claim 2, wherein the buried layer comprises GaAs and forms the interface with an adjacent AlGaAs layer.
4. A method according to any preceding claim, wherein the contact material is GePd.
5. A method according to any preceding claim, wherein the heterostructure is a HEMT structure.
6. A method according to any preceding claim, wherein a plurality of regions are etched to different depths in step (i) to allow formation of ohmic contacts selectively contacting a plurality of buried layers at different depths.
7. A heterojunction semiconductor device comprising a buried layer and an adjacent layer of a heterostructure defining an interface therebetween, an opening being provided in said heterostructure down to said buried layer and a contact material overlying the opening and forming an ohmic contact with said buried layer.
8. A device according to claim 7, wherein the opening extends to below the interface.
9. A device according to claim 7 or claim 8, wherein said opening extends below the interface.
10. A device according to any of claims 7 to 9, wherein the buried layer comprises GaAs and forms the interface with an adjacent AlGaAs layer.
11. A device according to any of claims 7 to 10, wherein the contact material is GePd.
12. A device according to any of claims 7 to 11, wherein the heterostructure is a HEMT structure.
13. A device according to any of claims 7 to 12, comprising a plurality of openings of different depths permitting selective ohmic contact to a plurality of buried layers at different depths.
14. A method of forming a shallow ohmic contact to a buried layer of a heterojunction semiconductor device, the method being substantially as hereinbefore described with reference to Figures 4, 5 and 7 of the accompanying drawings.
15. A heterojunction semiconductor device substantially as hereinbefore defined with reference to Figure 5 or
Figure 7 of the accompanying drawings.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9313876A GB2279806B (en) | 1993-07-05 | 1993-07-05 | Semiconductor device and method of making same |
| JP15378494A JPH07142706A (en) | 1993-07-05 | 1994-07-05 | Heterojunction semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9313876A GB2279806B (en) | 1993-07-05 | 1993-07-05 | Semiconductor device and method of making same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9313876D0 GB9313876D0 (en) | 1993-08-18 |
| GB2279806A true GB2279806A (en) | 1995-01-11 |
| GB2279806B GB2279806B (en) | 1997-05-21 |
Family
ID=10738322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9313876A Expired - Fee Related GB2279806B (en) | 1993-07-05 | 1993-07-05 | Semiconductor device and method of making same |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH07142706A (en) |
| GB (1) | GB2279806B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7692298B2 (en) * | 2004-09-30 | 2010-04-06 | Sanken Electric Co., Ltd. | III-V nitride semiconductor device comprising a concave shottky contact and an ohmic contact |
| US8035927B2 (en) | 2008-01-28 | 2011-10-11 | Hitachi Global Storage Technologies Netherlands B.V. | EMR magnetic sensor having its active quantum well layer extending beyond an over-lying semiconductor layer end with tab and lead structure for improved electrical contact |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005129696A (en) * | 2003-10-23 | 2005-05-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2007329350A (en) * | 2006-06-08 | 2007-12-20 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP5313457B2 (en) * | 2007-03-09 | 2013-10-09 | パナソニック株式会社 | Nitride semiconductor device and manufacturing method thereof |
| JP2011228720A (en) * | 2011-05-30 | 2011-11-10 | Panasonic Corp | Semiconductor device |
| JP5364760B2 (en) * | 2011-07-25 | 2013-12-11 | パナソニック株式会社 | Semiconductor device |
| WO2023189048A1 (en) * | 2022-03-29 | 2023-10-05 | ローム株式会社 | Nitride semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0064829A2 (en) * | 1981-04-23 | 1982-11-17 | Fujitsu Limited | High electron mobility semiconductor device and process for producing the same |
| EP0163203A2 (en) * | 1984-05-30 | 1985-12-04 | Texas Instruments Incorporated | Multiple high electron mobility transistor structures without inverted heterojunctions |
| EP0191201A1 (en) * | 1985-01-28 | 1986-08-20 | Koninklijke Philips Electronics N.V. | Semiconductor device with bidimensional charge carrier gas |
-
1993
- 1993-07-05 GB GB9313876A patent/GB2279806B/en not_active Expired - Fee Related
-
1994
- 1994-07-05 JP JP15378494A patent/JPH07142706A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0064829A2 (en) * | 1981-04-23 | 1982-11-17 | Fujitsu Limited | High electron mobility semiconductor device and process for producing the same |
| EP0163203A2 (en) * | 1984-05-30 | 1985-12-04 | Texas Instruments Incorporated | Multiple high electron mobility transistor structures without inverted heterojunctions |
| EP0191201A1 (en) * | 1985-01-28 | 1986-08-20 | Koninklijke Philips Electronics N.V. | Semiconductor device with bidimensional charge carrier gas |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7692298B2 (en) * | 2004-09-30 | 2010-04-06 | Sanken Electric Co., Ltd. | III-V nitride semiconductor device comprising a concave shottky contact and an ohmic contact |
| US8035927B2 (en) | 2008-01-28 | 2011-10-11 | Hitachi Global Storage Technologies Netherlands B.V. | EMR magnetic sensor having its active quantum well layer extending beyond an over-lying semiconductor layer end with tab and lead structure for improved electrical contact |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2279806B (en) | 1997-05-21 |
| JPH07142706A (en) | 1995-06-02 |
| GB9313876D0 (en) | 1993-08-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20100705 |