JPH06120518A - Semiconductor element for high-efficiency amplification - Google Patents

Abstract

PURPOSE:To provide a semiconductor amplififying element, which has a heterojunction and is increased a carrier concentration in its junction interface to make possible a high-efficiency operation. CONSTITUTION:A non-doped GaAs layer 7 is epitaxially grown on a substrate a non-doped AlGaAs layer 6 is grown, then, a carrier layer consisting of three layers of a non-doped GaAs layer 2, an Si-doped GaAs layer 1 and a non-doped GaAs layer 2 and a carrier layer consisting of three layers of a non-doped GaAs layer 2, an Si-doped GaAs layer 1 and a non-doped GaAs layer 2 are provided holding a non-doped AlGaAs layer 3 between them to form into a multilayer and an Si-doped GaAs layer 5 is grown on the uppermost part of a laminated material.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor amplifier device having a heterojunction and increasing the carrier concentration at the junction interface to enable high efficiency operation.

[0002]

2. Description of the Related Art Conventionally, the problems to be solved by the invention
The class F operation was effective when the semiconductor amplifying element was operated with high efficiency. The semiconductor amplification element parameters that determine the efficiency in this class F operation include, for example, first the ON resistance of the semiconductor amplification element, the second high frequency Gm, and the third drain conductance.

The ON resistance of the first semiconductor amplifying element can be reduced by setting the channel width large. However, there is also a limitation that increasing the channel width increases the gate-source capacitance and the gate-drain feedback capacitance, resulting in a decrease in gain described later.

In FIGS. 3A and 3B, GaAs MES is shown.
Although the actual measurement data when using the FET is shown, it can be seen that the limit is that the ON resistance is reduced to about 2/3 even if the channel width is increased.

This is because at high frequencies, the contribution of the gate-source capacitance cannot be ignored, the input inductance approaches the short-circuit point, and it becomes difficult to achieve input matching.

Another method of reducing the on-resistance is to increase the carrier concentration in the channel. However, although increasing the carrier concentration lowers the on-resistance, it has the drawback of lowering the drain breakdown voltage.

FIG. 4 is a GaAs MES FET design chart assuming that the carrier concentration in the channel is uniform in the depth direction. The horizontal axis represents carrier concentration and the vertical axis represents channel thickness. As is clear from the figure, when Vp is applied, it is necessary to increase the carrier concentration in order to improve Ids / Wg and Gm / Wg, but there is a disadvantage that the breakdown voltage between the drain and the gate is lowered. Wg, Gm
It can be understood that / Wg has an upper limit value.

For the improvement of the second high frequency Gm, see FIG.
Although it can be understood from the chart of (1) that shortening the channel length or increasing the carrier concentration is an effective method, it has the same drawbacks as in the case of the ON resistance of the first semiconductor amplifying element.

The improvement of the third drain conductance depends more on the process than on the effect of device design. One of the causes of the deterioration of drain conductance near the pinch-off voltage is the carrier leaking out of the channel. Generally, a P layer buffer or an AlGaAs heterobuffer layer is introduced to prevent carrier leakage into the buffer layer, but there is a drawback that the parasitic capacitance increases.

On the other hand, a two-dimensional electron gas device utilizing a heterojunction has a characteristic that excellent Gm characteristics can be obtained. For example, AlGaA having a small electron affinity.
When the s layer is heavily doped, a deep trap level is easily formed, the sheet carrier concentration is saturated, and the drain-gate breakdown voltage is low.

[0011]

According to the present invention, in a high-efficiency amplifying semiconductor device forming a channel of a power field effect transistor, a highly-doped semiconductor layer having a predetermined electron affinity and the highly-doped semiconductor are provided. A pair of carrier supply layers sandwiching the layers, each having a non-doped semiconductor body layer having substantially the same electron affinity as the highly doped semiconductor layer, and an electron affinity smaller than the electron affinity, and the pair of A high efficiency characterized by having a non-doped semiconductor layer sandwiched between carrier supply layers and forming a quantum well, wherein the quantum well is formed in multiple layers to obtain a predetermined current density without increasing the channel width. A semiconductor device for amplification can be obtained.

That is, the structure of the semiconductor device for high efficiency amplification according to the present invention which solves the above-mentioned problems is such that when a channel of a power field effect transistor is formed, a highly doped semiconductor layer having a large electron affinity is used with the same electron affinity. Of non-doped semiconductor layers having a large electron mobility to form a carrier supply layer, and a pair of carrier supply layers sandwiching a non-doped semiconductor layer having a small electron affinity above and below to form a quantum well. It is characterized in that it is formed to obtain a predetermined current density without increasing the channel width.

In other words, according to the present invention, a non-doped GaAs layer having a high electron affinity, for example, a GaAs layer having a high electron affinity, such as a thin GaAs layer having a high electron affinity, is sandwiched above and below the carrier supply layer, for example, an AlGaAs having a low non-doped electron affinity. The layers are sandwiched and these are periodically stacked to form a channel layer in multiple layers. As a result, the effective power density is increased while maintaining the drain-gate breakdown voltage to reduce the on-resistance, improve Gm, and improve the drain conductance.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

First, a description will be given based on the structural cross section shown in FIG.

Highly doped GaAs layer 1 having a high electron affinity
In order to sandwich the non-doped AlGaAs layer 3 having a small electron affinity above and below and to enhance the accumulation of carriers,
The non-doped GaAs layer 2 and the GaAs layer 1 and the AlGaAs
Each inserted between layer 3 to form a heterojunction,
The band diagram shown in FIG. 1 (B) is obtained. The relationship between the threshold voltage Vth and Ids is Vth = ψm- {q ・ Nd ・ (d-d0) ² / 2ε} -ΔEc (1) Ids = (μ ・ Wg ・ ε / 2Lg ・ d) ・ (Vgs-Vth ) ² (2) is given.

Here, ΔEc is, for example, AlGaAs layer 3 having a small electron affinity and GaA having a large electron affinity, for example.
It is a conduction band gap with the s layer 1. ψm
Is the Schottky barrier between the AlGaAs layer 4 and the metal, ε is the dielectric constant of the GaAs layer 3, Nd is the donor concentration in the GaAs layer 1, and μ is the electron mobility.

Vth is different from GaAs MES FET in ψm and ΔEc.
Nd needs to be prepared. Here, it is important that the thickness d of the GaAs layer 1 can be reduced to about 5 nm. That is,
Since d is small, Nd can be large, and in combination with the increase in Ids, the on-resistance can be remarkably reduced.

Next, for example, AlGa, which has a high electron affinity,
Above and below the As layer 3, the above-mentioned doped GaAs / non-doped G
If one period of each aAs layer is provided, four carrier storage layers can be obtained, and it is possible to increase the power density per unit gate width by forming this multi-layer channel. That is, even when the number of layers is increased, the threshold voltage does not change and Ids
It is possible to increase. Furthermore, the output power can be increased without increasing the gate width.

The number of layers is given threshold voltage and I
Determined from ds and.

Further, the epi thickness related to the semiconductor device for high efficiency amplification according to the present invention shown in FIGS. 1 (A) and 1 (B) described above is changed due to the deviation under the epi growth conditions.

As shown in FIG. 1A, a non-doped GaAs layer 7 having a large electron affinity is formed as a cap layer 500.
nm is epitaxially grown on the semi-insulating GaAs substrate 8. next,
A non-doped AlGaAs layer 6 is grown to 200 nm for lattice matching.

Next, the non-doped GaAs layer 2 is formed to a thickness of 5 nm and Si.
6 × 10 17 cm -3 doped GaAs layer 1 having a thickness of 2 nm, and a non-doped GaAs layer 2 having a thickness of 5 nm epitaxially grown thereon.

The GaAs layer 3 is called a carrier supply layer, and a thin non-doped AlGaAs layer 3 having a thickness of about 10 nm is used.
The carrier supply layer is installed with the carrier sandwiched therebetween.

A multi-layered structure is formed, and a 50 nm-thick non-doped AlGaAs layer 4 is formed on the top of the multi-layered film.
The As layer 9 is grown, and the Si-doped GaAs layer 5 is formed on the top.
Is grown to 20 nm. The number of carrier supply layers is determined by the required value of Ids.

[0026]

As described above, the present invention has the following effects.

First, since Ids is increased by the number of carrier supply layers without increasing the carrier concentration, deterioration of the gate / drain breakdown voltage is extremely reduced.

Next, I is increased without increasing the channel width.
It is possible to improve ds and prevent an increase in gate-source capacitance.

Further, without doping the AlGaAs layer, the GaAs / AlGaAs quantum well structure allows GaA
Heterostructure was realized by doping s. As a result, high-concentration doping is possible and the device can be improved in performance.

[Brief description of drawings]

FIG. 1 is a schematic view showing an example of a high-efficiency amplification semiconductor element, in which (A) is a sectional view of the configuration and (B) is a band diagram thereof.

FIG. 2 is a graph showing measured values of Ids when the double hetero of the present invention is used.

[FIG. 3] Id when a GaAs MES FET is used
It is a graph which shows the measured value of s.

FIG. 4 is a design chart diagram of a GaAs MES FET.

[Explanation of symbols]

 1 non-doped GaAs layer 2 non-doped GaAs layer 3 non-doped AlGaAs layer 4 non-doped AlGaAs layer 5 Si-doped GaAs layer 6 non-doped AlGaAs layer 7 non-doped GaAs layer 8 SiGaAs substrate 9 non-doped GaAs layer

Claims (1)

[Claims] 1. A high-efficiency amplifying semiconductor element constituting a channel of a power field effect transistor, wherein a highly-doped semiconductor layer having a predetermined electron affinity and the highly-doped semiconductor layer are sandwiched between the highly-doped semiconductor layer and the highly-doped semiconductor layer. And a pair of carrier supply layers each having a non-doped semiconductor layer having substantially the same electron affinity, and an electron affinity smaller than the electron affinity, sandwiched between the pair of carrier supply layers, and a quantum well And a non-doped semiconductor layer for forming the quantum well, wherein the quantum well is formed in multiple layers to obtain a predetermined current density without increasing the channel width.