JPH06334175A - Tunnel transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a tunnel transistor which is suitable for realizing fineness, low-voltage operation, high-current density and differential negative resistance characteristics. CONSTITUTION:This tunnel transistor has the laminated structure of a first semiconductor 2 (source) of one conductivity type, a second semiconductor 3 which is not degenerated, a third semiconductor 4 (drain) having a reverse conductivity type to that of the first semiconductor 2. In addition, a fourth semiconductor 5 composed of a semiconductor having a narrower forbidden bandwidth than that of the foregoing semiconductors and an insulating layer 6 composed of a material having a wider forbidden bandwidth than that thereof and a gate electrode 7 are provided in the exposed surface of the foregoing semiconductors, and a source electrode 8 and a drain electrode 9 are respectively provided in the first semiconductor 2 and the third semiconductor 4 with the formation of ohmic junction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor capable of high integration, high speed operation, and multi-function by utilizing a tunnel phenomenon.

[0002]

2. Description of the Related Art A tunnel transistor having multiple functions has been proposed by utilizing a tunnel phenomenon at a p ⁺ -n ⁺ junction on a semiconductor surface. For this device,
For example, it is described in the specification of Japanese Patent Application No. 3-196321, "Semiconductor Device" by the present applicant. This tunnel transistor can form a functional circuit with a small number of elements and enables high integration.

FIG. 2 is a schematic sectional view of a conventional tunnel transistor. 1 is a substrate, 10 is an insulating region formed on the substrate 1, 11 is a semiconductor channel layer, 12 is a source region made of a degenerate semiconductor having one conductivity type, and 13 is a conductivity type opposite to the source region 12. A drain region made of a degenerated semiconductor, 6 an insulating layer made of a material having a wider band gap than the semiconductor channel layer 11, 7 a gate electrode on the insulating layer, 8 a source electrode forming an ohmic junction with the source region 12. , 9 are drain electrodes forming an ohmic junction with the drain region 13.

Regarding the operation of this conventional tunnel transistor, the substrate 1 is a GaAs substrate, and the insulating region 10 is an i-A.
l _0.5 Ga _0.5 As, thin i-type semiconductor channel layer 11
GaAs, the source region 12 n ⁺ -GaAs, p ⁺ -GaAs to the drain region 13, the insulating layer 6 i-Al _0.5 G
An example will be described in which a _0.5 As, Al for the gate electrode 7, and Au for the source electrode 8 and the drain electrode 9 are used. When the source electrode 8 is set to the ground potential, no voltage is applied to the gate electrode 7, and a positive voltage is applied to the drain electrode 9, the source region 12 (n ⁺ -GaAs) and the drain region 13 (p
⁺ -GaAs), a forward bias is applied via a very thin semiconductor channel layer 11 (i-GaAs).
Compared to the reverse bias, this bias direction allows a drain current to flow more easily, but if the carrier diffusion current is not significant (0.7 V or less for GaAs),
Almost no current flows. When a large positive voltage is applied to the gate electrode 7, the semiconductor channel layer 11 (i-G)
A high concentration of electrons is induced in aAs). As a result, the semiconductor channel layer 11 is in a degenerated state in which the electron concentration is very large, and becomes an equivalent n ⁺ -GaAs. For this reason, the source region 12 (n ⁺ -GaAs) and the semiconductor channel layer 11 (i-GaAs) are brought into complete conduction. On the other hand, a junction (tunnel junction) similar to an Esaki diode (tunnel diode) is formed between the semiconductor channel layer 11 (i-GaAs) and the drain region 13 (p ⁺ -GaAs). Therefore, a large tunnel current flows due to the tunnel effect between the drain and source to which the forward bias is applied, and differential negative resistance appears in the current-voltage characteristic. Since the magnitude of the tunnel current depends on the concentration of electrons induced in the semiconductor channel layer 11, this differential negative resistance characteristic is controlled by the voltage applied to the gate electrode.

[0005]

The most important factor in this device is the formation of the tunnel junction between the semiconductor channel layer and the drain region, but since these are made of different semiconductors, ion implantation and selective regrowth are performed. It has to be formed through several processes such as. For this reason, there is a problem that the generation / recombination center associated with the process is easily induced in the vicinity of the tunnel junction, and the differential negative resistance characteristic is deteriorated by a large recombination current through the center. In order to obtain high reliability as a functional element, it is necessary to suppress this generation / recombination center.

An object of the present invention is to provide a tunnel transistor capable of suppressing generation / recombination centers.

[0007]

A tunnel transistor according to the present invention comprises a first semiconductor formed on a substrate and having one conductivity type and containing a high concentration of impurities, and a low concentration semiconductor formed on the first semiconductor. A second semiconductor containing an impurity of, a third semiconductor formed on the second semiconductor and having a conductivity type opposite to that of the first semiconductor, and containing a high concentration of impurities; A fourth semiconductor formed in contact with the exposed surface of the semiconductor laminated structure and having a narrower bandgap than the first to third semiconductors, and a fourth semiconductor formed in contact with the fourth semiconductor.
An insulating layer made of a material having a wider band gap than the semiconductor of
It is characterized in that it has a gate electrode provided over the insulating layer, a source electrode provided over the first semiconductor, and a drain electrode provided over the third semiconductor.

[0008]

In the tunnel transistor of the present invention, since the tunnel junction is formed in the fourth semiconductor, this junction characteristic is hardly affected by the process, and the generation / recombination center is suppressed.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a schematic sectional view showing a first embodiment of the present invention. 1, parts having the same reference numerals as those in FIG. 2 are the same as those in FIG. 2 and perform the same functions, and 2 is a first semiconductor having one conductivity type and containing a high concentration of impurities, 3
Is a second semiconductor having a low impurity concentration, 4 has a conductivity type opposite to that of the first semiconductor 2, and a third semiconductor containing a high concentration of impurities, 5 is more prohibited than the first to third semiconductors. It is a fourth semiconductor having a narrow band width.

Next, regarding the operation of the first embodiment, the substrate 1 is a GaAs substrate, the first semiconductor 2 is n ⁺ -GaAs,
The second semiconductor 3 is i-GaAs, and the third semiconductor 4 is p ⁺
-GaAs, thin i-In _0.1 Ga on the fourth semiconductor 5
_The description will be made using _0.9 As, i-Al _0.5 Ga _0.5 As for the insulating layer 6, Al for the gate electrode 7, and Au for the source electrode 8 and the drain electrode 9.

Since the first semiconductor 4 and the fourth semiconductor 5 form a modulation doping structure, first, some of the electrons in the semiconductor 2 move to the fourth semiconductor 5. Therefore, the portion of the fourth semiconductor 5 that is in contact with the first semiconductor 2 is a degenerate semiconductor in which high-concentration electrons are accumulated. Similarly, the third semiconductor 4 and the fourth semiconductor 5 also have a modulation-doped structure, and the fourth semiconductor 5 in contact with the third semiconductor 4 is a degenerate semiconductor in which high-concentration holes are accumulated. Has become. Therefore, when a positive voltage is applied to the gate electrode 7 to induce high-concentration electrons in the fourth semiconductor 5 below the insulating layer,
This region and the fourth semiconductor 5 in contact with the first semiconductor 2 are brought into complete conduction, and a tunnel junction is formed between the fourth semiconductor 5 in contact with the third semiconductor 4. Therefore, it is possible to realize a transistor operation having a differential negative resistance characteristic like the conventional tunnel transistor. In addition,
The first semiconductor 2 and the third semiconductor 4 do not necessarily have to be degenerated, but are preferably degenerated in order to reduce the parasitic resistance between the first semiconductor 2 and the third semiconductor 4. In the tunnel transistor of the embodiment, since the tunnel junction is formed in a single semiconductor layer as described above, the generation / recombination center which is associated with the heterogeneous semiconductor junction formation process near the tunnel junction is generated. Suppressed. For this reason, the recombination current is suppressed, and a more prominent differential negative resistance characteristic than the conventional structure is obtained.

Next, regarding the manufacturing method of the first embodiment,
The same material as that used in the description of the operation will be used for description.

First, n ⁺ of 500 nm is formed on a GaAs substrate.
-GaAs (n = 1 × 10 ¹⁹ cm ⁻³ ), i of 200 nm
−GaAs, 150 nm p ⁺ −GaAs (p = 5 × 1
0 ¹⁹ cm ^-3 ) to MBE (Molecular Beam)
It is formed by the epitaxy method. Next, the drain region is left in a mesa shape by lithography and etching to expose a part of n ⁺ -GaAs. After that, the substrate is again introduced into the MBE apparatus, and 20n is formed on the surface of the formed structure.
m i-In _0.1 Ga _0.9 As and 50 nm i-Al
Re-grow _0.5 Ga _0.5 As. After taking out from the MBE device, Al is vapor-deposited, and Al and i-In _0.1 Ga are deposited.
_0.9 As / i-Al _0.5 Ga _0.5 As is etched into a gate electrode shape. Lift off Au to n ⁺ -Ga
It is formed on As and p ⁺ -GaAs to serve as a source electrode and a drain electrode.

It was found that the device having this structure has a peak-valley ratio of 5 or more in the differential negative resistance characteristic, which is an improvement over the conventional structure. Similar characteristics as a tunnel transistor were obtained when the source and drain were exchanged and a negative voltage was applied to the gate to induce high-concentration holes under the gate.

Further, n ⁺ -In _0.1 Ga is added to the fourth semiconductor.
_{When 0.9} As (n = 2 × 10 ¹⁸ cm ⁻³ ) is used,
Even when the gate voltage was not applied, the tunnel junction was formed, and the depletion type operation could be performed.

Next, a second embodiment of the present invention will be described with reference to FIG. 1 similarly to the first embodiment. However, the insulating layer 6 is a semiconductor containing impurities. Hereinafter, description will be made by using n-Al _0.3 Ga _0.7 As for the insulating layer 6 and using the same material as that of the first embodiment except the above.

The fourth semiconductor 5 in contact with the second semiconductor 3
Between the insulating layer 6 and the insulating layer 6 is i-In _0.1 Ga _0.9 As / n
-Al _0.3 Ga _0.7 As modulation-doped structure.
Therefore, the electrons of n-Al _0.3 Ga _0.7 As are i-I.
The electrons move to n _0.1 Ga _0.9 As, high-concentration electrons are accumulated in the fourth semiconductor 5 in contact with the second semiconductor 3, and this region also becomes a degenerate semiconductor. On the other hand, the third semiconductor 4
A is in contact with the region of the fourth semiconductor 5, n-Al _0.3
The hole concentration decreases due to the Ga _0.7 As insulating layer 6, but the influence can be reduced by setting the hole concentration of the third semiconductor 4 to be considerably higher than the electron concentration of the insulating layer 6. . For this reason, a tunnel junction is formed inside the fourth semiconductor 5 even if a positive gate voltage is not applied, and this element is not connected to the fourth semiconductor 5 in the first embodiment.
As with the case of using ⁺ −In _0.1 Ga _0.9 As (n = 2 × 10 ¹⁸ cm ⁻³ ), it has a large tunnel current density,
Depression type operation is possible. In addition to this, since almost no impurities exist in the tunnel barrier, a leak current such as a tunnel current does not occur through the impurity level, and a larger peak-valley ratio than that of the first embodiment can be obtained. Thus, in the second embodiment,
Further improvement of the negative resistance characteristic can be expected as compared with the first embodiment.

20 nm of i-In _0.1 is added to the fourth semiconductor 5.
Ga _0.9 As, 50 nm n-Al _0.3 as insulating layer 6
Ga _0.7 As (n = 2 × 10 ¹⁸ cm ⁻³ ) was used, and the other materials and manufacturing methods similar to those of the first embodiment were used to fabricate the tunnel transistor. -A large improvement in differential negative resistance was obtained with a valley ratio of 10 or more. Also, when p-Al _0.3 Ga _0.7 As was used for the insulating layer 6, the same characteristics were obtained by reversing the polarity of the gate voltage.

Although the structure in which the entire insulating layer is doped with impurities is shown here, only a part of the insulating layer may be doped, such as planar doping, in order to increase the gate breakdown voltage.

In the above embodiments of the present invention, only the case where the first semiconductor and the third semiconductor are the same kind of semiconductor has been shown, but it is obvious that different kinds of semiconductors may be used. Further, as semiconductor materials, GaAs, I
Only nGaAs was shown, but Ge, Si, SiG
e, SiGeC, GaP, InP, GaSb, InA
s, InSb, InAsP, InAlAs, AlGaS
It is clear that many other semiconductor combinations such as b, HgCdTe, CdTe can also be applied to the present invention. Furthermore, although only AlGaAs was shown as an insulating film,
Other wide bandgap semiconductors, SiO ₂ , Si ₃ N
₄ , SiON, Al ₂ O ₃ , TiO ₂ , PbZrTIO
₃ , it is clear that insulators such as CaF may be used.

[0022]

As described above, in the tunnel transistor of the present invention, since the tunnel junction is formed in a single semiconductor layer, the generation / recombination center is small and the differential negative resistance characteristic is remarkable. However, according to the present invention, it is possible to form a tunnel device integrated circuit of high speed, low power consumption, room temperature operation, and ultra high density.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing first and second embodiments of the present invention.

FIG. 2 is a schematic cross-sectional view of a conventional tunnel transistor.

[Explanation of symbols]

 1 substrate 2 1st semiconductor 3 2nd semiconductor 4 3rd semiconductor 5 4th semiconductor 6 insulating layer 7 gate electrode 8 source electrode 9 drain electrode 10 insulating region 11 channel layer 12 source region 13 drain region

Claims (3)

[Claims] 1. A first semiconductor formed on a substrate, having one conductivity type and containing a high concentration of impurities, and a second semiconductor formed on the first semiconductor, containing a low concentration of impurities. In contact with a third semiconductor formed on the second semiconductor, having a conductivity type opposite to that of the first semiconductor, and containing a high concentration of impurities, and an exposed surface of the laminated structure of the first to third semiconductors. A fourth semiconductor formed and made of a material having a narrower bandgap than the first to third semiconductors, and an insulating layer formed in contact with the fourth semiconductor and made of a material having a wider bandgap than the fourth semiconductor And a gate electrode provided on the insulating layer, a source electrode provided on the first semiconductor, and a drain electrode provided on the third semiconductor. 2. The tunnel transistor according to claim 1, wherein at least a part of the insulating layer contains an ionized impurity, and carriers are induced inside the fourth semiconductor in contact with the second semiconductor. 3. A first semiconductor having one conductivity type and containing a high concentration of impurities, a second semiconductor containing a low concentration of impurities, and a high conductivity type having a conductivity type opposite to that of the first semiconductor. A laminated structure made of a third semiconductor containing a high concentration of impurities is formed on the substrate by the MBE method, and then a part of the first semiconductor is partially left by leaving a drain region in a mesa shape by lithography and etching. Exposing and again stacking a fourth semiconductor made of a material having a narrower band gap than the first to third semiconductors and an insulating layer made of a material having a wider band gap than the fourth semiconductor by the MBE method. Then, Al is vapor-deposited, the laminated structure including Al, the insulating layer, and the fourth semiconductor is etched into a gate electrode shape, and Au is formed on the first semiconductor and the third semiconductor by a lift-off method. Each Method of manufacturing a tunnel transistor, characterized in that the over scan electrode and the drain electrode.