JPS62211964A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the transference of quadratic hole gas or quadratic electron gas produced on a hetero interface by a method wherein the grid constant of the second semiconductor layer laminated on the first semiconductor layer with the same grid constant as that of a semiconductor substrate is made smaller than that of the first semiconductor layer. CONSTITUTION:A P<-> type GaAs layer 2, a P-type Ga0.6In0.4P layer 3 are successively laminated on a semiinsulating GaAs substrate 1 while a gate electrode 5, a source electrode 6 and a drain electrode 7 are provided on the layer 3. Furthermore, the layer 3 is provided with smaller grid constant and wider forbidden band width than those of the layer 2 provided with the same grid constant that of the substrate 1. In such a constitution, a shrinkage stress is imposed on the layer 2 at the hetero interface between the layer 2 and the layer 3 to change the forbidden band structure, a charged electron band structure and a conductor structure. Resultantly, the quadratic hole gas and the quadratic electron gas produced on the hetero interface can be diminished to increase the transference thereof.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device that utilizes two-dimensional hole gas or two-dimensional electron gas formed at a hetero interface. It's about technology.

[Prior art]

Efforts to obtain high-speed, low-power semiconductor devices using compound semiconductors have been widely made in the past, and recently, field effect transistors (Field 1 Effect T
Ransjstor, FET), for example, Japanese Journal of Applied Physics (Jpn, J., Appl, Phys.), Vol. 19,
225 (1980). FETs that use this two-dimensional electron gas are different from conventional semiconductor devices.

Although their high mobility improved performance, the disadvantage of high power consumption could not be overcome.

In recent years, in order to eliminate such drawbacks, n-channel FETs using two-dimensional hole gas are used together with n-channel FETs using two-dimensional electron gas to form a complementary FET, which enables high-speed, low-power consumption. Attempts have been made to obtain power semiconductor devices and have already been published in Electronics Letters (Elec
tronics Letters), Volume 21, No. 11
16 (1985), basic characteristics such as ring oscillation characteristics are reported.

[Problem that the invention seeks to solve]

However, the operating speed of the complementary FET reported in the above literature is slow and has insufficient performance. This is the AlGa-A semiconductor layer that constitutes the complementary FET.
The mobility of the two-dimensional hole gas formed at the hetero interface between the s-layer and the GaAs layer is still smaller than that of the two-dimensional electron gas, and for this reason, it is difficult to develop an n-channel FET using the two-dimensional hole gas. This was due to poor performance.

The present invention has been made to solve the above problems, and its purpose is to reduce the effective mass of the two-dimensional hole gas or two-dimensional electron gas formed at the hetero interface and increase the mobility. By doing so, the object is to obtain a high-performance semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention provides a first semiconductor layer with a low impurity concentration provided on a semi-insulating substrate and having substantially the same lattice constant as the semi-insulating substrate, and a first semiconductor layer on the first semiconductor layer. Is it set up? The semiconductor device is characterized primarily by comprising a second semiconductor layer having a lattice constant smaller than that of the first semiconductor layer and a second semiconductor layer having a band gap larger than the first semiconductor layer.

In conventionally manufactured semiconductor devices such as FETs using two-dimensional hole gas or two-dimensional electron gas, a semi-insulating substrate and first and second semiconductor layers laminated thereon are used. This is fundamentally different from the previous method, which used a layered structure in which all the lattice constants were the same.

By adopting the layer structure of the present invention, compressive stress exists in the first semiconductor layer at the hetero interface between the first semiconductor layer and the second semiconductor layer, so that the forbidden band structure and the valence band structure are improved. Alternatively, the conduction band structure changes, so that the effective mass of the two-dimensional hole gas or two-dimensional electron gas formed at the hetero interface decreases, and the mobility increases. As a result, the performance of the semiconductor device of the present invention using this layered structure can be significantly improved compared to conventional devices.

Attempts have already been made to reduce the effective mass of the two-dimensional hole gas due to changes in the layer structure caused by the compressive stress.
Applied Physics Letters (Appl,,P
hys, Lett, ), Volume 46, Page 187 (19
In 1985), GaAs/InGaAs strained layer-superlattice
ed-Layer 5upper-1attice)
(a superlattice consisting of strained layers) has been reported. Although this structure certainly reduces the effective mass of the two-dimensional hole gas in InGaAs, its mobility was smaller than the conventional value. This is a first layer of InGaA with a different lattice constant from GaAs on a GciAs substrate.
This is because the InGaAs layer is grown as a semiconductor layer, and the crystallinity of the InGaAs layer is impaired due to a mismatch in lattice constants. On the other hand, in the present invention, since the semi-insulating substrate and the first semiconductor layer have the same lattice constant, the crystallinity of the first semiconductor layer and the first semiconductor layer and the second semiconductor layer are the same. The crystallinity of the heterointerface was excellent, and an increase in mobility was confirmed.

[Effect]

As described above, according to the present invention, the first semiconductor layer and the second semiconductor layer
Due to the presence of compressive stress in the first semiconductor layer at the hetero interface with the semiconductor layer, its forbidden band structure, valence band structure, or conduction band structure changes, and thus 2 The effective mass of the dimensional hole gas or the two-dimensional electron gas decreases and the mobility increases.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically explained using hair drawings.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

First, a first embodiment in which the present invention is applied to a p-channel FET will be described.

As shown in FIG. 1, the p-channel FE according to the first embodiment
In T, a p-type GaAs layer 2 with a low impurity concentration and a p-type Gaa, r, InQ, doped with a P-type impurity such as Be (beryllium) are formed on a semi-insulating GaAs substrate 1.
4 P layers 3 are sequentially laminated. This p-type Gaa6I
n. The 4P layer 3 has a smaller lattice constant and a larger forbidden band width than the P-type GaAs layer 2, and also has a larger forbidden band width than the P-type GaAs layer 2.
The aAs layer 2 has the same lattice constant as the semi-insulating GaAs substrate 1. Note that these P-type GaAs layers 2 and p
Type G, a e6In, 4P layer 3 is formed by molecular beam epitaxial method (MBE method), metal organic chemical vapor deposition method (MOCV).
D method) etc. can be used for growth. The above p-type G
Of the aAs layer 2, this p-type GaAs layer 2 and p-type (
A two-dimensional hole gas 4 is formed near the hetero interface with the ja, 6In, and 4P layer 3. Further, the p-type Ga66Tne, +P layer 3 is provided with a gate electrode 5, a source electrode 6, and a train electrode 7, respectively.

Note that the source electrode 6 and the drain? ! ! Pole 7 is P-
It extends to the top of the type GaAs layer 2 and is connected to both ends of the two-dimensional hole gas 4, respectively.

According to this first embodiment, compressive stress exists in the hetero interface portion of the p-type GaAs layer 2 with the p-type GanG:In0.4P layer 3, as described above. , the forbidden band width changes, the effective mass of the two-dimensional hole gas 4 decreases, and its mobility becomes 1.8 compared to when an AlGaAs layer is used instead of the P-type Gao6In, 4P layer 3. It has doubled. For this reason, the lance conductance, which indicates the performance of FETs, also increases significantly, and P-type Ga, GIn,
,, Compared to the case where an AlGaAs layer was used instead of the P layer 3, a transconductance 1.6 times was obtained.

Next, a second embodiment in which the present invention is applied to a p-channel FET will be described.

As shown in FIG. 2, the p-channel FE according to the second embodiment
In T, a non-doped Ga, 4, Ino, As layer 9 having the same lattice constant as the semi-insulating InP substrate 8 and this Ga, 4, In
o, Ino4As layer 1 of non-doped Al having a smaller lattice constant and larger band gap than the 53As layer 9
0 are sequentially stacked. These Alo,, In
, 4As layer 10 and Ga11.47In0.53AS layer 9, a p-type semiconductor region 11 is provided in a self-alignment line with respect to the gate electrode 5. Note that this P-type semiconductor region 11 can be formed by, for example, ion-implanting a p-type impurity such as Be using the gate electrode 5 as a mask, and then electrically activating the impurity by annealing.

In the p-channel FET according to the second embodiment, an A1.6In, 4As layer 10 below the gate electrode 5
is not doped with p-type impurities, so unlike the p-channel FET according to the first embodiment, when no voltage is applied to the gate electrode 5, Gal+, 47'Ene, 5aA
The two-dimensional hole gas 4 is not formed at the hetero interface between the S layer 9 and the A1°, , In, , As layer 10 . but,
- By applying a negative voltage to the gate electrode 5, two-dimensional hole gas 4 can be induced at the hetero interface. For the same reason as described in the first embodiment, the mobility of the two-dimensional hole gas 4 is as follows.

A.I. Instead of the 6Inl14As layer 10, Ga6.4
7In. 53 AI having the same lattice constant as the AS layer 9;
The transconductance of this FET was 2.1 times higher than when l+, 48 In, , □AsJ'l was used, and a value of 1.8 times higher was obtained.

Next, the present invention is applied to a p-channel FE provided on the same substrate.
A third embodiment applied to a complementary FET consisting of a T-channel FET and an n-channel FET will be described.

As shown in FIG. 3, the complementary F'ET according to the third embodiment
As in the second embodiment, a non-doped Ga14□Ini,5iAS layer 9 and a non-doped A1°5In114As layer 10 are sequentially laminated on a semi-insulating InP substrate 8. And these Ga647Ins, 5
aAS layer 9 and A1. ,, In, 4As layer 10, the second
An n-channel FET 12 having a configuration similar to that of the embodiment is provided. Furthermore, adjacent to this n-channel FET 12,
Gate electrode 13, n-type semiconductor region 14, source electrode 15
and a drain electrode 16 are provided, respectively, and constitute an n-channel FET 17.

Note that the n-type semiconductor region 14 is, for example, the gate electrode 1
3 as a mask, for example, N such as Si (silicon).
It can be formed by ion-implanting type impurities and then electrically activating the impurities by annealing.

In the n-channel FET 17, the gate electrode 13
When no voltage is applied to , Gao, + □ ne, 5a
As layer 9 and A1. , jn, 4 Although no two-dimensional electron gas is formed at the hetero interface with the As layer 10, the gate electrode 1
By applying a positive voltage to 8, two-dimensional electron gas 18
can be induced. Also at the hetero interface where this two-dimensional electron gas 18 exists, Ga, 4. In
, , , Since compressive stress exists in the As layer 9, the mobility of the two-dimensional electron gas 18 also changes, but it is possible to obtain a mobility comparable to or higher than when there is no compressive stress. .

The performance of the complementary riT according to the third embodiment is that the n-channel FET has a lower operating speed than the n-channel FET 17.
As described in the second embodiment, by improving the performance of the n-channel FET 12 by 1.8 times, the speed of the complementary FET can be increased by this amount. Therefore, a complementary FET with high speed and low power consumption can be obtained.

As mentioned above, the invention made by the present inventor has been specifically explained based on the above-mentioned embodiments, but the present invention is not limited to the above-mentioned first to third embodiments, and within the scope of the gist thereof, Of course, various modifications can be made.

For example, as shown in FIG. 4, a p-channel FET according to the second embodiment is constructed by using an inverter. , a non-doped Ga114□In,53As layer 19 is provided as a cap layer on the As layer 10, and this Gae,*v Ing,s
3 It is also possible to have a structure in which the gate electrode 5 is provided on the As layer 19. Further, as shown in FIG. 5, p according to the second embodiment
Gao4t Ina, s 3 that constitutes the channel FET
p-type A1°, In, 4As layer 20 and p-type Gaa4t instead of As layer 9 and Al116In, 4As layer 10
Ina, 5aAs layers 21 are used, and grooves 2 are formed in these.
It is also possible to provide a structure in which a groove 22 is provided and a gate electrode 5 is provided on the bottom of the groove 22.

In addition, p-type Gae, 5Ine in the first embodiment described above
, ii GaInAs P layer instead of P layer 3, GaIn
It is also possible to use an A1 P layer or a GaInAlAs P layer. Similarly, Al in the second and third embodiments
, , AlGaInAs instead of In, 4As layer 10
It is also possible to use layers.

Furthermore, the present invention is applicable not only to a single n-channel FET using two-dimensional electron gas but also to various semiconductor devices other than FETs.

〔Effect of the invention〕

As explained above, according to the present invention, compressive stress existing at the hetero interface between the first semiconductor layer and the second semiconductor layer causes the two-dimensional hole gas or The mobility of two-dimensional electron gas can be increased, and therefore a high-performance semiconductor device can be obtained.

[Brief explanation of drawings]

FIG. 1 shows a p-channel FET according to a first embodiment of the present invention.
Cross-sectional view.゛ FIG. 2 shows a p-channel F according to a second embodiment of the present invention.
A cross-sectional view of ET. FIG. 3 is a sectional view of a complementary FET according to a third embodiment of the invention, FIG. 4 is a sectional view of a p-channel FET according to a modification of the invention, and FIG. 5 is another modification of the invention. p-channel FET by
FIG. In the figure, 1... semi-insulating GaAs substrate, 2... p-type GaAs layer, sp-p type Ga, Inf14P layer, 4
...Two-dimensional hole gas, 5.13...Gate electrode, 6,
15... Source electrode, 7.16... Drain electrode, 8
...Semi-insulating InP substrate, 9.19"'Gao4t
Ina, 53 AS layer, 12- p-channel FET, 10
-A1. ,,,In, 4As layer, 17-n channel F
ET, 18-2-dimensional electron gas, 20- p-type Al, 6I
n, 4As layer, 21- p-type Ga6,47Inn, 53
This is the AS layer.

Claims (5)

[Claims] (1) a semi-insulating substrate; a first semiconductor layer with a low impurity concentration provided on the semi-insulating substrate and having substantially the same lattice constant as the semi-insulating substrate; A semiconductor comprising a second semiconductor layer provided on a semiconductor layer and having a lattice constant smaller than that of the first semiconductor layer and a band gap larger than the first semiconductor layer. Device. (2) The semi-insulating substrate is a GaAs substrate, the first semiconductor layer is a GaAs layer, and the second semiconductor layer is a GaInP layer, a GaInAsP layer, a GaInAlP layer, or a GaInAlAsP layer. A semiconductor device according to claim 1. (3) the semi-insulating substrate is an InP substrate;
The semiconductor layer of Ga_0_. _4_7In_0_. ＿５＿
2. The semiconductor device according to claim 1, wherein the second semiconductor layer is an AlInAs layer or an AlGaInAs layer. (4) The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is a p-channel or n-channel field effect transistor. (5) Any one of claims 1 to 3, wherein the semiconductor device is a complementary field effect transistor consisting of a p-channel field effect transistor and an n-channel field effect transistor. 1. The semiconductor device according to item 1.