JPH0261150B2 - - Google Patents
Info
- Publication number
- JPH0261150B2 JPH0261150B2 JP11287683A JP11287683A JPH0261150B2 JP H0261150 B2 JPH0261150 B2 JP H0261150B2 JP 11287683 A JP11287683 A JP 11287683A JP 11287683 A JP11287683 A JP 11287683A JP H0261150 B2 JPH0261150 B2 JP H0261150B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inas
- gasb
- alsb
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 15
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 15
- 229910017115 AlSb Inorganic materials 0.000 claims description 13
- 229910005542 GaSb Inorganic materials 0.000 claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims 9
- 239000002356 single layer Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910001295 No alloy Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
Description
【発明の詳細な説明】
（技術分野）
本発明は、高速動作をする化合物半導体デバイ
スに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a compound semiconductor device that operates at high speed.
（従来技術とその問題点）
GaAsを用いたデバイスはその電子移動度が大
きいこと、半絶縁性GaAs基板が得られることに
より、Siを用いたデバイスに比べ、高速動作が得
られている。GaAsよりさらに高電子移動度を得
るためにInxGa1−xAs（ｘ＝0.53）を用いたデバ
イスが報告されているが、あまり大きな電子移動
度は得られていない。これはInxGa1−xAs混晶
中での合金散乱のためだと考えられる。(Prior art and its problems) Devices using GaAs have high electron mobility and can operate at higher speeds than devices using Si due to the availability of semi-insulating GaAs substrates. Devices using InxGa 1 -xAs (x=0.53) have been reported in order to obtain even higher electron mobility than GaAs, but very high electron mobility has not been obtained. This is thought to be due to alloy scattering in the InxGa 1 -xAs mixed crystal.
また、２元化合物半導体のInAsは、合金散乱
がなく、高電子移動度が期待できるが、この
InAsに格子整合した良質の半絶縁性基板が得ら
れないのが実状である。 InAs, a binary compound semiconductor, has no alloy scattering and can be expected to have high electron mobility;
The reality is that it is not possible to obtain a high-quality semi-insulating substrate that is lattice-matched to InAs.
（発明の構成）
本発明は、これらの問題点を解決するためにな
されたものであり、半絶縁性GaAs基板を用い合
金散乱がなく、電子移動度が大きいInAsを動作
層として用いた半導体デバイスの製造方法を与え
るものである。(Structure of the Invention) The present invention was made to solve these problems, and provides a semiconductor device using a semi-insulating GaAs substrate, no alloy scattering, and using InAs, which has high electron mobility, as an active layer. The present invention provides a method for manufacturing.
以下、実施例により、詳細に説明する。 Hereinafter, it will be explained in detail using examples.
まず第１図ａに示すように半絶縁性GaAs基板
１上にGaSb２を分子線エピタキシヤル法で2μｍ
以上成長させる。 First, as shown in FIG.
grow more than that.
次にこのGaSb２上にAlSb層３を0.5μｍ、不純
物ドープしていないInAs層４を1μｍ、AlSb層５
を0.1μｍ、Al膜６を0.4μｍ成長させる（第１図
ｂ）。つぎに第１図ｃに示すように一つの領域７
を除きAl膜６をフオトエツチングで除去し、ゲ
ート電極７を形成する。次にゲート電極７に関し
て互いに反対側にある２領域をInAs層４に到達
するまでエツチングし（第１図ｄ）、最後にこの
２領域にAuのオーミツク電極８，９を形成する
（第１図ｅ）。 Next, on this GaSb2, an AlSb layer 3 with a thickness of 0.5 μm, a non-doped InAs layer 4 with a thickness of 1 μm, and an AlSb layer 5 with a thickness of 1 μm are formed.
The Al film 6 is grown to a thickness of 0.1 μm and an Al film 6 of 0.4 μm (FIG. 1b). Next, as shown in Figure 1c, one area 7
The Al film 6 is removed by photo-etching except for the gate electrode 7. Next, two regions on opposite sides of the gate electrode 7 are etched until reaching the InAs layer 4 (FIG. 1d), and finally Au ohmic electrodes 8 and 9 are formed in these two regions (FIG. 1). e).
このようにして目的の高速半導体デバイスが得
られる。 In this way, the desired high-speed semiconductor device is obtained.
第１図ａにおいて、GaSb層２は2μ以上にして
ある。GaSbとGaAsとは約7.9％の格子不整があ
るにもかかわらず、2μｍ以上成長させることに
より良好な結晶が得られることを発明者等は見い
出している。第２図はGaSbの膜厚に対する移動
度の相対値を示しているが、膜厚が2μｍ以上で
は移動度は飽和しており、良好な結晶が得られて
いる。 In FIG. 1a, the GaSb layer 2 has a thickness of 2μ or more. The inventors have discovered that although GaSb and GaAs have a lattice mismatch of about 7.9%, good crystals can be obtained by growing them to a thickness of 2 μm or more. FIG. 2 shows the relative value of the mobility with respect to the film thickness of GaSb, and when the film thickness is 2 μm or more, the mobility is saturated and a good crystal is obtained.
第１図ｂにおいて、超高真空チエインバ内で、
AlSb層に引き続きAl膜６を成長させているのは、
AlSb膜が非常に酸化し易く、大気中ではすぐに
表面に酸化膜が形成されてしまうためである。 In FIG. 1b, in an ultra-high vacuum chamber,
The reason why the Al film 6 is grown following the AlSb layer is as follows.
This is because the AlSb film is very easily oxidized, and an oxide film is quickly formed on the surface in the atmosphere.
次に、本発明で製造した電界効果トランジスタ
高速動作性について説明する。 Next, high-speed operation of the field effect transistor manufactured according to the present invention will be explained.
第３図は、AlSbとInAsとのヘテロ界面でのエ
ネルギー・バンド図であり、ａは外部電界がない
とき、ｂはAlSb側に正電圧を印加したとき、ｃ
はAlSb側に負電圧を印加したときのそれぞれの
エネルギー・バンド図である。 Figure 3 is an energy band diagram at the hetero interface between AlSb and InAs, where a is when there is no external electric field, b is when a positive voltage is applied to the AlSb side, and c is when a positive voltage is applied to the AlSb side.
are the respective energy band diagrams when a negative voltage is applied to the AlSb side.
本実施例による電界効果トランジスタでは、
AlSbとInAsとのバンド構造の相違から第３図ａ
に示すようにInAsとGaSbとの界面のInAs側に電
子が蓄積し、これが電気伝導に寄与している。そ
してゲート電極７に電圧を加えることにより、バ
ンド図は第３図ｂ，ｃに示すように変わり、オー
ミツク電極８，９間に流れる電流が変調される。
このようにして、InAsの電子移動度は大きいの
で高速動作が得られる。 In the field effect transistor according to this example,
Figure 3a shows the difference in band structure between AlSb and InAs.
As shown in , electrons accumulate on the InAs side of the interface between InAs and GaSb, and this contributes to electrical conduction. By applying a voltage to the gate electrode 7, the band diagram changes as shown in FIGS. 3b and 3c, and the current flowing between the ohmic electrodes 8 and 9 is modulated.
In this way, high-speed operation can be achieved due to the high electron mobility of InAs.
（産業上の利用可能性）
以上述べた如く本発明は、従来用いられてきた
半導体デバイスより動作速度の速い化合物半導体
デバイスの製造方法を与えるものである。(Industrial Applicability) As described above, the present invention provides a method for manufacturing a compound semiconductor device that operates at a higher operating speed than conventionally used semiconductor devices.
現在トランジスタ、ICが用いられているあら
ゆる分野に用いることができ、その産業上の利用
分野は極めて大きく、特に高速処理が必要な分
野、例えば計算機のCPU、メモリ画像処理等で
の利用が期待できる。 It can be used in all fields where transistors and ICs are currently used, and its industrial applications are extremely wide.It is expected to be used in fields that require high-speed processing, such as computer CPUs, memory image processing, etc. .
本発明は、本実施例の構造の素子に限るもので
はなく、GaSbと格子定数のほぼ等しい材料の組
み合わせを用いたデバイスにはすべて適用でき、
半絶縁性GaAs基板を用いたこれらの素子が実現
できる。 The present invention is not limited to the device having the structure of this example, but can be applied to any device using a combination of GaSb and a material having approximately the same lattice constant.
These devices can be realized using semi-insulating GaAs substrates.
第１図は、本発明の一実施例である電界効果ト
ランジスタの製造方法の説明図であり、プロセス
の各段階での素子の断面構造を示すものである。
第２図は、GaAs基板上に結晶成長させたGaSb
の相対移動度の層厚依存性を示す図である。第３
図は、AlSbとInAsとのヘテロ界面でのエネルギ
ー・バンド図であり、ａは外部電界がないとき、
ｂは正電圧（AlSb側が正）印加したとき、ｃは
負電圧を印加したときのそれぞれのエネルギー・
バンド図である。
１は半絶縁性GaAs基板、２はGaSb層、３，
５はAlSb層、４はInAs層、６はAl膜、７はゲー
ト電極、８，９はオーミツク電極である。
FIG. 1 is an explanatory diagram of a method for manufacturing a field effect transistor, which is an embodiment of the present invention, and shows the cross-sectional structure of the device at each stage of the process.
Figure 2 shows GaSb crystal grown on a GaAs substrate.
FIG. 3 is a diagram showing the layer thickness dependence of the relative mobility of . Third
The figure is an energy band diagram at the heterointerface between AlSb and InAs, where a is when there is no external electric field.
b is the energy when a positive voltage (positive on the AlSb side) is applied, and c is the energy when a negative voltage is applied.
It is a band diagram. 1 is a semi-insulating GaAs substrate, 2 is a GaSb layer, 3,
5 is an AlSb layer, 4 is an InAs layer, 6 is an Al film, 7 is a gate electrode, and 8 and 9 are ohmic electrodes.
Claims (1)
晶成長させる工程と、該GaSb層上にGaSbとほぼ
格子定数の等しい単層または多層の結晶を成長さ
せる工程とを含む高速半導体デバイスの製造方
法。 ２ 2μｍ以上の前記GaSb層上に順次、Al、Sb
層、InAs層、AlSb層を積層し、次いでAl膜を積
層し、この後、該Al膜の一部をゲート電極とし
て残し、該ゲート電極の外側の領域を前記InAs
層の一部まで除去し、最後に除去後残つたInAs
層上にオーミツク電極を設けることを特徴とする
特許請求の範囲第１項に記載の高速半導体デバイ
スの製造方法。[Claims] 1. A high-speed method comprising the steps of growing a crystal of GaSb to a thickness of 2 μm or more on a semi-insulating GaAs substrate, and growing a single-layer or multi-layer crystal having a lattice constant approximately equal to that of GaSb on the GaSb layer. A method for manufacturing semiconductor devices. 2 Al and Sb are sequentially deposited on the GaSb layer with a thickness of 2 μm or more.
A layer, an InAs layer, and an AlSb layer are stacked, and then an Al film is stacked, and then a part of the Al film is left as a gate electrode, and a region outside the gate electrode is covered with the InAs layer.
Part of the layer was removed, and the remaining InAs was removed at the end.
A method of manufacturing a high-speed semiconductor device according to claim 1, characterized in that an ohmic electrode is provided on the layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11287683A JPS605572A (en) | 1983-06-24 | 1983-06-24 | Manufacture of high speed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11287683A JPS605572A (en) | 1983-06-24 | 1983-06-24 | Manufacture of high speed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS605572A JPS605572A (en) | 1985-01-12 |
| JPH0261150B2 true JPH0261150B2 (en) | 1990-12-19 |
Family
ID=14597740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11287683A Granted JPS605572A (en) | 1983-06-24 | 1983-06-24 | Manufacture of high speed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS605572A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2796113B2 (en) * | 1989-03-20 | 1998-09-10 | 富士通株式会社 | Semiconductor device |
| DE69223706T2 (en) * | 1991-03-28 | 1998-08-20 | Asahi Chemical Ind | FIELD EFFECT TRANSISTOR |
-
1983
- 1983-06-24 JP JP11287683A patent/JPS605572A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS605572A (en) | 1985-01-12 |
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