JPH07263664A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE:To reduce not only parasitic resistances between a channel layer and a contact layer and between a contact layer and a gate electrode but source resistance in a semiconductor device that is provided with a heterojunction field effect transistor having a gate electrode on a heterobarrier layer. CONSTITUTION:The title device has such a structure that a heterobarrier layer 4 covers the respective side faces of a pair of contact layers 3 on a channel layer 2 and the upper face of the layer 2 between the layers 3 while the channel layer and contact layer are kept in contact with each other directly and the layer 3 and electrode 5 are not brought into direct contact with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a heterojunction field effect transistor, and more particularly to a structure suitable for a heterojunction field effect transistor using a III-V compound semiconductor.

[0002]

2. Description of the Related Art Heterojunction field effect transistors using III-V group compound semiconductors have the characteristics of ultra-high speed and low noise, and are widely used in the fields of satellite communication and mobile radio. It is expected that these microwave communications will be developed in the millimeter wave band of higher frequency in the future, and it is necessary to further increase the speed of the heterojunction field effect transistor.

In order to increase the speed of the heterojunction field effect transistor, it is necessary to improve the mutual conductance.
For that purpose, measures such as thinning the active layer, shortening the gate length, and reducing the source resistance are effective. In the present invention, attention is paid to the reduction of source resistance.

IEE TRANSACTION
On Electron Devices (IEEE Trans. Electro
n Devices) vol. 33, pp. 934, 1986, a heterojunction field effect transistor according to the prior art is shown in FIG. In this example, undoped GaAs2 is used as the channel layer.
(Thickness 1000 nm), n-type GaAs3 (thickness 100
nm, Al composition ratio 0.25, impurity concentration 2x10 ¹⁸ / cm ³ ), n-type AlGaAs 4 as a heterobarrier layer (thickness 60 nm, impurity concentration 6x10 ¹⁷ / cm ³
cm ³ ), gate length 0.7 μm, source resistance 100 mΩcm
A transconductance of 2.3 S / cm is obtained.

Undoped GaAs / n-type A according to the above conventional technique
In the lGaAs heterojunction field effect transistor, a structure in which a hetero barrier layer 4 is provided on the channel layer 2 and a pair of contact layers 3 and a gate electrode 5 are arranged on the hetero barrier layer 4 is used. The same structure is used for an n-type GaAs / undoped AlGaAs heterojunction field effect transistor, an undoped InGaAs / n-type AlGaAs heterojunction field effect transistor, and an undoped InGaAs / n-type InAlAs heterojunction field effect transistor.

In the structure of the prior art, the hetero barrier layer 4 is sandwiched at the junction between the channel layer 2 and the contact layer 3. A drain current will flow through this junction, but there is a double potential barrier due to band discontinuity in the energy band structure of this junction (Fig. 3). For this reason, IEE Trans-Action on Electron Devices (IEEE Trans. Ele
Ctron Devices) vol. 36, pp. 1036, 1989, in the conventional heterojunction field effect transistor, the junction resistance between the channel layer 2 and the contact layer 3 is large.

In the structure of the prior art, the side surface of the contact layer 3 and the side surface of the gate electrode 5 directly face each other. When the contact layer 3 and the gate electrode 5 are in contact with each other, the gate breakdown voltage is lowered, so these must be separated by about 0.1 μm. However, in the space between the contact layer 3 and the gate electrode 5, the channel layer 2 is depleted due to the surface level.
Becomes high resistance (Fig. 4). For this reason, IEICE Technical Report, ED
As described in 89-133, in the conventional heterojunction field effect transistor, the parasitic resistance in the space between the contact layer 3 and the gate electrode 5 is large.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the parasitic resistance of the junction between the channel layer and the contact layer and the parasitic resistance of the space between the contact layer and the gate electrode, thereby reducing the hetero-junction of low source resistance. It is to provide a semiconductor device having a field effect transistor and a manufacturing method thereof.

[0009]

An object of the present invention is to provide a first semiconductor layer, a pair of second semiconductor layers on the first semiconductor layer, and a first semiconductor layer between the second semiconductor layers. This can be achieved by using a field effect transistor having a structure having a third semiconductor layer covering the upper surface and side surfaces of the second semiconductor layer facing each other, and a gate electrode on the third semiconductor layer. Here, when the second semiconductor layer is n-type, one having an electron affinity smaller than that of the first and second semiconductor layers is used as the third semiconductor layer. When the second semiconductor layer is p-type, a semiconductor layer having a sum of electron affinity and bandgap larger than the sum of electron affinity and bandgap of the first and second semiconductor layers is used as the third semiconductor layer.

Further, a fourth semiconductor layer may be inserted between the first and second semiconductor layers and the third semiconductor layer having the above structure. Here, when the second semiconductor layer is n-type, it is used that the electron affinity of the fourth semiconductor layer is larger than that of the third semiconductor layer. In addition, the second semiconductor layer is p
In the case of the mold, the fourth semiconductor layer having a sum of electron affinity and band gap smaller than the sum of electron affinity and band gap of the third semiconductor layer is used.

Another object of the present invention is to selectively grow a semiconductor layer which is a base material of the second semiconductor layer by using a first mask which covers a desired region of the first semiconductor layer. Second semiconductor layer by etching a part of the semiconductor layer that is the base material of the second semiconductor layer using a second mask that covers a desired region of the semiconductor layer that is the base material of the second semiconductor layer A step of selectively growing a third semiconductor layer using the second mask, a step of depositing a gate metal with the second mask left, and a step of forming a desired region of the gate metal And a step of forming a gate electrode by etching a part of the gate metal with a third mask covering the gate electrode.

Further, a step of etching a part of a semiconductor layer which is a base material of the second semiconductor layer to form the second semiconductor layer, and the third semiconductor using the second mask. Between the step of selectively growing the layer, the fourth semiconductor layer may be selectively grown using the second mask.

[0013]

In the field effect transistor of the present invention, the first semiconductor layer is the channel layer, the second semiconductor layer is the contact layer,
The third semiconductor layer functions as a hetero barrier layer. In the field effect transistor having the structure in which the fourth semiconductor layer is inserted, the fourth semiconductor layer functions as a channel layer instead of the first semiconductor layer.

In the present invention, since the channel layer and the contact layer are in direct contact with each other without the hetero barrier layer, the potential barrier between the channel layer and the contact layer can be greatly reduced. As a result, the parasitic resistance between the channel layer and the contact layer can be reduced.

Further, in the field effect transistor of the present invention, since the hetero barrier layer is interposed between the side surface of the contact layer and the side surface of the gate electrode, the contact layer and the gate electrode do not come into direct contact with each other. Therefore, they can be brought close to the thickness of the hetero barrier layer. As a result, the parasitic resistance between the contact layer and the gate electrode can be significantly reduced.

As described above, the parasitic resistance between the channel layer and the contact layer and the parasitic resistance between the contact layer and the gate electrode can be reduced, and a low source resistance heterojunction field effect transistor can be realized.

Further, in the manufacturing method of the present invention, as an etching mask for forming a contact layer, a mask for selectively growing a hetero barrier layer, and a mask for selectively depositing a gate metal on a gate electrode forming portion, Since the gate electrode is formed in the contact layer in a self-aligned manner using the same mask, the distance between the contact layer and the gate electrode can be made smaller than the alignment accuracy of lithography.

[0018]

【Example】

Example 1 This example is an application example to the undoped GaAs / n-type AlGaAs heterojunction field effect transistor of the present invention. The cross-sectional structure of the heterojunction field effect transistor of this example is shown in FIG. In the heterojunction field effect transistor of this embodiment, the undoped GaAs 2 (thickness 500
nm), n-type GaAs3 (thickness 150 nm, impurity concentration 5 × 10 ¹⁸ / cm ³ ) as a contact layer, and n-type AlGaAs as a hetero barrier layer.
4 (thickness 25 nm, Al composition ratio 0.3, impurity concentration 3.5x10 ¹⁸ / cm ³ )
Was used. The gate length is 0.2 μm.

The heterojunction field effect transistor of this example was manufactured by the following method (FIG. 5). First, undoped GaAs 2 is epitaxially grown on the semi-insulating GaAs substrate 1 by the MBE method. Plasma CV on undoped GaAs2
SiO ₂ 11 (thickness 100 nm) is deposited by the D method. The SiO ₂ 11 is patterned by photolithography, and the remaining SiO _{2 is}
Using 11 as a mask, n-type GaAs 3 is selectively epitaxially grown on the undoped GaAs 2 by MOCVD (FIG. 5).
(a)). Here, in order to reduce the interface state density of the undoped GaAs2 / n-type GaAs3 interface, the surface of the undoped GaAs2 was cleaned with HCl gas in the growth chamber of the MOCVD apparatus immediately before the selective epitaxial growth of the n-type GaAs3. Next, with the SiO ₂ 11 remaining, SiO ₂ 12 (thickness 100 nm) is deposited on the entire surface of the wafer by the plasma CVD method. The SiO ₂ 12 was patterned by photolithography and left
Using SiO ₂ 11 and 12 as a mask, n-type G
The aAs3 is etched (FIG. 5 (b)). Then, using SiO ₂ 11 and 12 as a mask, undoped GaAs 2 and n-type
Selectively epitaxially grow n-type AlGaAs 4 on GaAs 3 by MOCVD method (FIG. 5C). Here, undoped GaAs
In order to reduce the interface state density of the 2 / n-type AlGaAs4 interface and the n-type GaAs3 / n-type AlGaAs4 interface, H in the growth chamber of the MOCVD apparatus immediately before the selective epitaxial growth of the n-type AlGaAs4.
The surface of undoped GaAs2 and n-type GaAs3 was cleaned with Cl gas. Further, in order to enhance the selectivity of the selective epitaxial growth of n-type AlGaAs4, HCl is used as a source gas (a mixed gas of TMA, TMG, AsH ₃ , Si ₂ H ₆ , and H ₂ ) for the selective growth.
Gas was added. Next, while leaving SiO ₂ 11 and 12, WSi is deposited to a thickness of 300 nm on the entire surface of the wafer by a sputtering method. The WSi is patterned by photolithography to form the gate electrode 5 (FIG. 5D). Finally, n-type G
A source electrode 6 and a drain electrode 7 made of a AuGe / Ni / Au laminated film are formed on the aAs 3 by a lift-off method and alloyed (FIG. 5 (e)).

In the heterojunction field effect transistor of this example, the source resistance could be reduced to 22 mΩcm due to the effect of using the structure of the present invention. In addition, in this embodiment, SiO ₂
By forming the gate electrode 5 in a self-aligned manner while leaving 12 as it is, the overlap between the gate electrode 5 and the contact layer 3 is suppressed below the alignment accuracy of the lithography and the increase of the parasitic capacitance is suppressed.

Example 2 This example is an example of application to the n-type GaAs / undoped AlGaAs heterojunction field effect transistor of the present invention. The cross-sectional structure of the heterojunction field effect transistor of this example is shown in FIG. In the heterojunction field effect transistor of this embodiment, undoped GaAs 2 (thickness: 500) is used as a buffer layer.
nm), n-type GaAs3 (thickness 150 nm, impurity concentration 5 × 10 ¹⁸ / cm ³ ) as a contact layer, and n-type GaAs8 (thickness as a channel layer
12 nm, impurity concentration 5 × 10 ¹⁸ / cm ³ ) and undoped AlGaAs 9 (thickness 12 nm, Al composition ratio 0.3) was used as a hetero barrier layer. The gate length is 0.2 μm.

The heterojunction field effect transistor of this example was manufactured by the following method. First, semi-insulating GaAs
Undoped GaAs 2 is epitaxially grown on the substrate 1 by the MBE method. SiO ₂ is deposited to 100 nm on the undoped GaAs ₂ by the plasma CVD method. S by photolithography
By patterning iO _2, and using the remaining SiO ₂ as a mask, n-type GaAs 3 is selectively epitaxially grown on the undoped GaAs ₂ by MOCVD. Here, undoped GaAs2 /
To reduce the interface state density of the n-type GaAs3 interface, n-type Ga
Immediately before the selective epitaxial growth of As3, the surface of the undoped GaAs2 was cleaned with HCl gas in the growth chamber of the MOCVD apparatus. Next, with the SiO ₂ remaining, 100 nm of SiO ₂ is deposited on the entire surface of the wafer by the plasma CVD method. SiO ₂ is patterned by photolithography, the remaining Si
Using O ₂ as a mask, the n-type GaAs 3 is etched by the RIE method. Then, using SiO ₂ as a mask, undoped GaAs
N-type GaAs 8 and undoped AlGaAs 9 are successively and selectively grown on the 2 and n-type GaAs 3 successively by MOCVD. Here, undoped GaAs2 / n-type GaAs8
In order to reduce the interface state density of the interface and the n-type GaAs3 / n-type GaAs8 interface, the surface of the undoped GaAs2 and the n-type GaAs3 is cleaned with HCl gas in the growth chamber of the MOCVD device immediately before the selective epitaxial growth of the n-type GaAs8. It was Moreover, in order to improve the selectivity of the selective epitaxial growth of undoped AlGaAs 9, the source gas (TMA,
HCl gas was added to the mixed gas of TMG, AsH ₃ and H ₂ . next,
While leaving the SiO ₂ mask, WSi is deposited to 300 nm on the entire surface of the wafer by sputtering. WSi by photolithography
Is patterned to form the gate electrode 5. Finally,
A source electrode 6 and a drain electrode 7 made of a AuGe / Ni / Au laminated film are formed on the n-type GaAs 3 by a lift-off method and alloyed.

In this embodiment, a heterojunction field effect transistor having a source resistance of 21 mΩcm could be realized.

Example 3 This example is an undoped InGaAs / undoped AlG of the present invention.
This is an application example to an aAs heterojunction field effect transistor. The cross-sectional structure of the heterojunction field effect transistor of this example is shown in FIG. In the heterojunction field effect transistor of this example, undoped InGaAs was used as the channel layer.
21 (thickness 20 nm, In composition ratio 0.2), n as contact layer
Type GaAs 3 (thickness 150 nm, impurity concentration 5 × 10 ¹⁸ / cm ³ ) and undoped AlGaAs 9 (thickness 20 nm, Al composition ratio 0.7) were used as a hetero barrier layer. The gate length is 0.2 μm.

The heterojunction field effect transistor of this example was manufactured by the following method. First, semi-insulating GaAs
Undoped GaAs 2 (thickness 500 nm) and undoped InGaAs 21 are epitaxially grown on the substrate 1 by the MBE method.
SiO ₂ was deposited on the undoped InGaAs 21 by the plasma CVD method.
Deposit 100 nm. The SiO ₂ is patterned by photolithography, and the remaining SiO ₂ is used as a mask for undoped In
N-type GaAs 3 is selectively epitaxially grown on GaAs 21 by MOCVD. Here, undoped InGaAs21 / n
N-type GaAs to reduce the interface state density at the interface
Immediately before the selective epitaxial growth of 3, the surface of the undoped InGaAs 21 was cleaned with HCl gas in the growth chamber of the MOCVD apparatus. Next, with the SiO ₂ remaining, 100 nm of SiO ₂ is deposited on the entire surface of the wafer by the plasma CVD method. The SiO ₂ was patterned by photolithography and left
Using SiO ₂ as a mask, the n-type GaAs 3 is etched by the RIE method. Then, using SiO ₂ as a mask, undoped In
Undoped AlGaAs 9 is selectively epitaxially grown on the GaAs 21 and the n-type GaAs 3 by the MOCVD method. here,
In order to reduce the interface state density of the undoped InGaAs21 / undoped AlGaAs9 interface and the n-type GaAs3 / undoped AlGaAs9 interface, the surface of the undoped InGaAs21 and the n-type GaAs3 with HCl gas is immediately before the selective epitaxial growth of the undoped AlGaAs9 in the growth chamber of the MOCVD apparatus. It was cleaned. Further, in order to enhance the selectivity of the selective epitaxial growth of the undoped AlGaAs 9, HCl gas was added to the source gas for the selective growth (a mixed gas of TMA, TMG, AsH ₃ and H ₂ ). Next, while leaving the SiO ₂ mask, 300 nm of WSi is deposited on the entire surface of the wafer by the sputtering method. The WSi is patterned by photolithography to form the gate electrode 5. Finally, AuGe / N was formed on the n-type GaAs3 by the lift-off method.
Source electrode 6 and drain electrode 7 made of i / Au laminated film
Are formed and alloyed.

In this example, a heterojunction field effect transistor having a source resistance of 19 mΩcm could be realized.

Embodiment 4 This embodiment is an example of application to the undoped InGaAs / n-type InAlAs heterojunction field effect transistor of the present invention. The cross-sectional structure of the heterojunction field effect transistor of this embodiment is
(Fig. 8). In the field effect transistor of this example, undoped InGaAs 33 (thickness 50 nm,
In composition ratio 0.5), n-type InGaAs34 as contact layer (thickness 150 nm, In composition ratio 0.5, impurity concentration 2x10 ¹⁹ / cm ³ ), n-type InAlAs35 as heterobarrier layer (thickness 20 nm, In composition ratio)
0.5, impurity concentration 3.5 × 10 ¹⁸ / cm ³ ) was used. Gate length is 0.
2 μm.

The heterojunction field effect transistor of this example was manufactured by the following method. First, semi-insulating InP
Undoped InAlAs 32 (thickness 50
0 nm, In composition ratio 0.5) and undoped InGaAs 33 are epitaxially grown. Plasma on undoped InGaAs 33
SiO ₂ is deposited to 100 nm by the CVD method. SiO ₂ is patterned by photolithography, and the remaining SiO ₂ is used as a mask to form n-type InGaA on undoped InGaAs 33 by MOCVD.
s34 is selectively epitaxially grown. Here, in order to reduce the interface state density at the interface of the undoped InGaAs33 / n-type InGaAs34, the surface of the undoped InGaAs33 was cleaned with HCl gas in the growth chamber of the MOCVD apparatus immediately before the selective epitaxial growth of the n-type InGaAs34. Next, with the SiO ₂ remaining, 100 nm of SiO ₂ is deposited on the entire surface of the wafer by the plasma CVD method. S by photolithography
After patterning iO ₂ , using the remaining SiO ₂ as a mask, RIE
The n-type InGaAs 34 is etched by the method. Then Si
Undoped InGaAs 33 and n-type In using O ₂ as a mask
An n-type InAlAs 35 is selectively epitaxially grown on the GaAs 34 by the MOCVD method. Here, undoped InGaAs33
/ n-type InAlAs35 interface and n-type InGaAs34 / n-type InAlAs
In order to reduce the interface state density of the 35 interface, n-type InAlAs3
Immediately before the selective epitaxial growth of No. 5, in the growth chamber of the MOCVD apparatus, undoped InGaAs 33 and n
The surface of the type InGaAs 34 was cleaned. Also, n
In order to enhance the selective epitaxial growth of InAlAs 35, the source gases for selective growth (TMI, TMA, AsH ₃ , Si ₂ H ₆ ,
HCl gas was added to (H ₂ mixed gas). Next, while leaving the SiO ₂ mask, 300 WSi is sputtered on the entire surface of the wafer.
nm to deposit. The WSi is patterned by photolithography to form the gate electrode 5. Finally, n-type InGaAs
A source electrode 6 and a drain electrode 7 made of a Ti / Pt / Au laminated film are formed on the surface 34 by a lift-off method.

In this example, a heterojunction field effect transistor having a source resistance of 9 mΩcm could be realized.

Embodiment 5 This embodiment is an example in which an n-channel field effect transistor and a p-channel field effect transistor according to the present invention are integrated on the same substrate. The cross-sectional structure of this embodiment is
(Fig. 9). In the n-channel field effect transistor (left side of FIG. 9), undoped InGaAs21 is used as the channel layer.
(Thickness 20 nm, In composition ratio 0.2), n-type GaA as contact layer
s3 (thickness 150 nm, impurity concentration 5x10 ¹⁸ / cm ³ ), undoped AlGaAs 9 (thickness 20 nm, Al composition ratio 0.7) as a hetero barrier layer
Is used. p-channel field effect transistor (Fig. 9
On the right side, undoped InGaAs21 (20 nm thick, In composition ratio 0.2) is used as the channel layer and p-type GaAs2 is used as the contact layer
2 (thickness 150 nm, impurity concentration 2x10 ¹⁹ / cm ³ ), undoped AlGaAs as hetero barrier layer 9 (thickness 20 nm, Al composition ratio 0.7)
Is used. Both n-channel field effect transistor and p-channel field effect transistor have a gate length of 0.2 μm
Is.

This example was manufactured by the following method. First, undoped G on the semi-insulating GaAs substrate 1 by MBE method.
Epitaxially grow aAs2 (thickness 500 nm) and undoped InGaAs21. Plasma on undoped InGaAs 21
SiO ₂ is deposited to 100 nm by the CVD method. The SiO ₂ is patterned by photolithography, the remaining SiO ₂ is used as a mask, and after cleaning the surface with HCl gas, undoped I
The n-type GaAs 3 is selectively epitaxially grown on the nGaAs 21 by the MOCVD method. Next, with the SiO ₂ remaining, 100 nm of SiO ₂ is deposited on the entire surface of the wafer by the plasma CVD method. After patterning SiO ₂ by photolithography and using the remaining SiO ₂ as a mask, after cleaning the surface with HCl gas,
P-type GaAs 22 on undoped InGaAs 21 by MOCVD method
Selectively grow epitaxially. Next, with the SiO ₂ remaining, 100 nm of SiO ₂ is deposited on the entire surface of the wafer by the plasma CVD method. Except on the p-type GaAs 22, SiO ₂ is etched by 100 nm. SiO ₂ is patterned by photolithography, and the remaining SiO ₂ is used as a mask to form n-type GaAs by RIE.
3 and p-type GaAs 22 are etched simultaneously. Subsequently, after surface cleaning with HCl gas using SiO ₂ as a mask, undoped AlGaAs 9 is formed on the undoped InGaAs 21 and n-type GaAs 3 and p-type GaAs 22 by the MOCVD method.
Selectively grow epitaxially. A mixed gas of TMA, TMG, AsH ₃ , H ₂ and HCl was used as the source gas for the selective growth. Next, while leaving the SiO ₂ mask, 300 nm of WSi is deposited on the entire surface of the wafer by the sputtering method. By photolithography
The gate electrode 5 is formed by patterning WSi. Finally, the source electrode 6 and the drain electrode 7 made of the AuGe / Ni / Au laminated film are formed on the n-type GaAs 3, and the AuZn / A is formed on the p-type GaAs 22.
u Source electrode 6 and drain electrode 7 made of laminated film
Are formed and alloyed.

In this embodiment, an n-channel field effect transistor having a source resistance of 19 mΩcm and a p-channel field effect transistor having a source resistance of 42 mΩcm could be integrated on the same substrate. In addition, by applying this embodiment, complementary logic gates configured to connect the gate electrodes and the drain electrodes of the n-channel and p-channel field effect transistors by metal wiring and connect a power supply between the source electrodes. A digital integrated circuit with a basic circuit was manufactured.

Example 6 This example is an undoped InGaAs / n-type InA using the present invention.
lAs heterojunction field effect transistor and undoped InGaA
This is an example in which s / undoped InAlAs heterojunction field effect transistors are integrated on the same substrate. The cross-sectional structure of this example is shown in FIG. Undoped InGaAs / n-type InAlA
In the s heterojunction field effect transistor (left side of FIG. 10),
Undoped InGaAs 33 (thickness 50 nm, In
Composition ratio 0.5), n-type InGaAs34 (thickness 1 as contact layer
50 nm, In composition ratio 0.5, impurity concentration 2 × 10 ¹⁹ / cm ³ ), n-type InAlAs 35 as a hetero barrier layer (thickness 20 nm, Al composition ratio 0.5,
Impurity concentration 3.5x10 ¹⁸ / cm ³ ) is used. Undoped InG
aAs / Undoped InAlAs heterojunction field effect transistor
On the right side of FIG. 10, undoped InGaAs is used as the channel layer.
33 (thickness 50 nm, In composition ratio 0.5), n as contact layer
Type InGaAs34 (thickness 150nm, In composition ratio 0.5, impurity concentration 2x1
0 ¹⁹ / cm ³ ), undoped InAlAs 36 as a hetero barrier layer
(Thickness 20 nm, Al composition ratio 0.5) is used. Undoped InG
The gate length of both the aAs / n-type InAlAs heterojunction field effect transistor and the undoped InGaAs / undoped InAlAs heterojunction field effect transistor is 0.2 μm.

This example was manufactured by the following method. First, undoped on the semi-insulating InP substrate 31 by MBE method.
InAlAs32 (thickness 500nm, In composition ratio 0.5) and undoped
InGaAs 33 is epitaxially grown. Undoped InGa
SiO ₂ is deposited to 100 nm on As 33 by the plasma CVD method.
After patterning SiO ₂ by photolithography and using the remaining SiO ₂ as a mask to clean the surface with HCl gas, n-type I was formed on undoped InGaAs 33 by MOCVD.
Selectively epitaxially grow nGaAs 34. Then SiO ₂
While leaving the, SiO ₂ by a plasma CVD method over the entire surface of the wafer
Is deposited to 100 nm. The SiO ₂ is patterned by photolithography, and the n-type InGaAs 34 is etched by the RIE method using the remaining SiO ₂ as a mask. Then, using SiO ₂ as a mask, after surface cleaning with HCl gas, n-type InAlAs 35 is selectively epitaxially grown on the undoped InGaAs 33 and n-type InGaAs 34 by MOCVD.
Source gases for selective growth are TMI, TMA, AsH ₃ , Si ₂ H ₆ ,
A mixed gas of H ₂ and HCl was used. Next, while leaving the SiO ₂ mask, 300 nm of WSi is deposited on the entire surface of the wafer by the sputtering method. The WSi is patterned by photolithography to form the gate electrode 5. Next, SiO ₂ is patterned by photolithography, and the n-type InGaAs 34 is etched by the RIE method using the remaining SiO ₂ as a mask. Then, using SiO ₂ as a mask, after cleaning the surface with HCl gas, undoped InGaAs 33 and n-type InGaAs 3
An undoped InAlAs 36 is selectively epitaxially grown on the layer 4 by MOCVD. Source gases for selective growth include TMI and T
A mixed gas of MA, AsH ₃ , H ₂ and HCl was used. Next, with the SiO ₂ remaining, WSi of 300 nm is sputtered on the entire surface of the wafer.
accumulate. The WSi is patterned by photolithography to form the gate electrode 5. Finally, n-type InGaAs3
A source electrode 6 and a drain electrode 7 made of a Ti / Pt / Au laminated film are formed on the surface 4 by a lift-off method.

In this example, an undoped InGaAs / n-type InAlAs heterojunction field effect transistor having a source resistance of 9 mΩcm and an undoped InGaAs / undoped InAlAs heterojunction field effect transistor having a source resistance of 9 mΩcm could be integrated on the same substrate. Further, by applying this embodiment, a digital integrated circuit having a DCFL type logic gate as a basic circuit could be manufactured.

[0036]

According to the present invention, a low junction resistance heterojunction field effect transistor can be realized.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a field effect transistor of a first embodiment of the present invention.

FIG. 2 is a cross-sectional structural diagram of a conventional field effect transistor.

FIG. 3 is an energy band structure diagram of a junction between a channel layer and a contact layer of a conventional field effect transistor.

FIG. 4 is an energy band structure diagram of a gap between a contact layer and a gate electrode of a conventional field effect transistor.

5 (a) to 5 (e) are manufacturing process diagrams of the field effect transistor of the first embodiment of the present invention.

FIG. 6 is a sectional structural view of a field effect transistor of a second embodiment of the present invention.

FIG. 7 is a sectional structural view of a field effect transistor of a third embodiment of the present invention.

FIG. 8 is a sectional structural view of a field effect transistor of a fourth embodiment of the present invention.

FIG. 9 is a sectional structural view of a field effect transistor of a fifth embodiment of the present invention.

FIG. 10 is a sectional structural view of a field effect transistor of a sixth embodiment of the present invention.

[Explanation of symbols]

1: Semi-insulating GaAs substrate, 2: Undoped GaAs, 3: n-type GaA
s, 4: n-type AlGaAs, 5: gate electrode, 6: source electrode, 7:
Drain electrode, 8: n-type GaAs, 9: undoped AlGaAs, 1
1: SiO ₂ , 12: SiO ₂ , 21: Undoped InGaAs, 22: p-type G
aAs, 31: Semi-insulating InP substrate, 32: Undoped InAlAs, 3
3: Undoped InGaAs, 34: n-type InGaAs, 35: n-type InAlA
s, 36: Undoped InAlAs.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/095

Claims (17)

[Claims] 1. A first semiconductor layer, a pair of n-type second semiconductor layers on the first semiconductor layer, an upper surface of the first semiconductor layer between the second semiconductor layers, and the first semiconductor layer. A third semiconductor layer that covers opposite sides of the second semiconductor layer and a gate electrode on the third semiconductor layer, and the electron affinity of the third semiconductor layer is the first and second semiconductor layers. A semiconductor device having a field-effect transistor smaller than the electron affinity of the semiconductor layer. 2. The third semiconductor layer formed between the upper surface of the first semiconductor layer and the side surfaces of the second semiconductor layer facing each other between the second semiconductor layer and the third semiconductor layer. The semiconductor device according to claim 1, further comprising a fourth semiconductor layer having an electron affinity larger than that of the semiconductor layer. 3. The semiconductor device according to claim 1, wherein the first semiconductor layer contains an n-type impurity. 4. The semiconductor device according to claim 2, wherein the fourth semiconductor layer contains an n-type impurity. 5. The semiconductor device according to claim 1, wherein the third semiconductor layer contains an n-type impurity. 6. A first semiconductor layer, a pair of p-type second semiconductor layers on the first semiconductor layer, an upper surface of the first semiconductor layer between the second semiconductor layers, and the first semiconductor layer. A third semiconductor layer that covers opposite sides of the second semiconductor layer and a gate electrode on the third semiconductor layer, and the sum of the electron affinity and the band gap of the third semiconductor layer is the above A semiconductor device having a field effect transistor having a larger electron affinity and bandgap of the first and second semiconductor layers. 7. The third semiconductor layer formed between the upper surface of the first semiconductor layer between the second semiconductor layers and the side surfaces of the second semiconductor layer facing each other, and the third semiconductor layer. 7. The semiconductor device according to claim 6, further comprising a fourth semiconductor layer having a smaller sum of electron affinity and band gap than the semiconductor layer of. 8. The semiconductor device according to claim 6, wherein the first semiconductor layer contains p-type impurities. 9. The semiconductor device according to claim 7, wherein the fourth semiconductor layer contains a p-type impurity. 10. The semiconductor device according to claim 6, wherein the third semiconductor layer contains a p-type impurity. 11. The semiconductor device according to claim 1, wherein the third semiconductor layer is AlGaAs. 12. The semiconductor device according to claim 1, wherein the third semiconductor layer is InAlAs. 13. A step of selectively growing a semiconductor layer which is a base material of a second semiconductor layer by using a first mask which covers a desired region of the first semiconductor layer, and a step of forming the second semiconductor layer. A step of forming a second semiconductor layer by etching a part of the semiconductor layer which is a base material of the second semiconductor layer using a second mask which covers a desired region of the semiconductor layer which is a base material; A step of selectively growing a third semiconductor layer using the second mask, a step of depositing a gate metal with the second mask left, and a step of covering a desired region of the gate metal. A method of manufacturing a semiconductor device, comprising a step of etching a part of the gate metal using a third mask to form a gate electrode. 14. A step of selectively growing a fourth semiconductor layer using the second mask between the step of forming the second semiconductor layer and the step of selectively growing the third semiconductor layer. 14. The method for manufacturing a semiconductor device according to claim 13, which comprises. 15. A first field effect transistor according to any one of claims 1 to 5, and a second field effect transistor according to any one of claims 6 to 10,
The gate electrode of the first field effect transistor and the gate electrode of the second field effect transistor are electrically connected, and the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor are connected to each other. A semiconductor device, which is electrically connected. 16. A step of selectively growing a semiconductor layer, which is a base material of a second semiconductor layer, using a first mask which covers a desired region of the first semiconductor layer, and a step of forming a desired semiconductor layer of the first semiconductor layer. A step of selectively growing a semiconductor layer as a base material of the third semiconductor layer using a second mask covering the outside of the region, and a semiconductor layer as a base material of the second semiconductor layer and the third semiconductor Of a semiconductor layer which is a base material of the second semiconductor layer and a semiconductor layer which is a base material of the second semiconductor layer by using a third mask which covers a desired region of the semiconductor layer which is a base material of the layer Partially etching to form a second semiconductor layer and a third semiconductor layer, a step of selectively growing a fourth semiconductor layer using the third mask, and leaving the third mask The step of depositing the gate metal as it is, and the fourth mask covering the desired area of the gate metal. The method of manufacturing a semiconductor device characterized by comprising the step of forming a partially etched gate electrode of the gate metal Te. 17. A semiconductor layer which is a base material of a second semiconductor layer or a semiconductor layer which is a base material of a fourth semiconductor layer is formed using a first mask which covers a desired region of the first semiconductor layer. A step of selectively growing and a part of the semiconductor layer which is the base material of the second semiconductor layer is performed by using a second mask which covers the outside of a desired region of the semiconductor layer which is the base material of the second semiconductor layer. A step of forming a second semiconductor layer by etching, a step of selectively growing a third semiconductor layer using the second mask, and a step of depositing a gate metal while leaving the second mask. And a step of forming a gate electrode by etching a part of the gate metal using a third mask that covers a desired region of the gate metal, and a semiconductor layer serving as a base material of the fourth semiconductor layer. Using a fourth mask that covers the outside of the desired area of the semiconductor layer, which is the base material of the fourth semiconductor layer. A step of etching a part of the layer to form a fourth semiconductor layer; a step of selectively growing a fifth semiconductor layer using the fourth mask; and a gate metal with the fourth mask left. And a step of forming a gate electrode by etching a part of the gate metal with a fifth mask covering a desired region of the gate metal. Manufacturing method.