JP3178395B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device and its, in particular, satellite broadcasting, satellite communication, to a semiconductor device suitable for a mobile communication device.

[0002]

2. Description of the Related Art A semiconductor device excellent in high frequency performance, for example, a Schottky gate field effect transistor (FE) using a III-V compound semiconductor represented by GaAs.
T) is widely used in satellite broadcasting, satellite communication, mobile communication and microwave backbone communication, and its performance is required to be improved.

A conventional HJFET (heterojunction transistor) having a WSi / Ti / Au gate electrode
25 to 34 are shown in FIGS. 25 to 34 are cross-sectional views shown in the order of steps. As shown in FIG.
Undoped GaAs layer 62 is deposited on s substrate 61 at 4000
Then, an undoped InGaAs layer 63 is formed at a thickness of 150 °, followed by 2E1
N-type Al doped with an N-type impurity to about 0 ¹⁸ cm ^-3
Each of the GaAs layer 64 and the n-type GaAs layer 65 doped with an N-type impurity to about 3E10 ¹⁸ cm ⁻³ is 500
{1000} is formed.

[0004] Next, as shown in FIG.
Using a photoresist, leaving the element portion 66
By n-type GaAs as shown in FIG.
Layer 65, n-type AlGaAs layer 64, undoped InGa
Remove As layer 63 and expose undoped GaAs layer 62
Then, element isolation is performed. Next, SiO 2 is used as the insulating film 67. _Two
As shown in FIG. 28 showing a cross section taken along the line AB in FIG.
, A photoresist 68 is applied, and an i-line stepper is used.
Opening in the insulating film 67 on the n-type GaAs layer 65
A 0.4 μm × 200 μm recess pattern 69 and FIG.
6 showing the CD section of FIG.
100 μm × 100 μm gate on insulating film 67 on 62
After forming the electrode pad pattern 70, dry etch
The insulating film 67 is etched to form an opening.

Next, as shown in FIGS. 30 and 31 showing cross sections taken along the lines AB and CD in FIG. 26, after the n-type GaAs layer 65 is removed by etching, the side wall insulating film 71 (SiO ₂ ) is removed. After forming a film and forming a side wall by dry etching to reduce the opening dimension of the recessed portion to 0.2 μm, WSi / Ti /
Au metal is sputtered to form a T-type gate electrode 72.

A gate electrode pad 73 is formed on the undoped GaAs layer 62 simultaneously with the formation of the gate electrode 72. FIG. 32 shows a plan view seen from above. This FIG.
33 and 34 show cross sections AB and CD of FIG. In order to form the source electrode 74, the drain electrode 75, the source electrode pad 76, and the drain electrode pad 77, after patterning with a photoresist, the insulating film 67 is etched as shown in FIG.
A source electrode 74 and a drain electrode 75 of about 0 μm are formed on the n-type GaAs layer 65, and a gate electrode pad is formed with a source electrode pad 76 and a drain electrode pad 77 of 100 μm × 300 μm as shown in FIG. It is formed on the same undoped GaAs layer 62 as the ohmic metal layer using AuGe / Ni / Au as an ohmic metal.

In the FET thus manufactured, the leakage current flowing between the gate electrode pad and the drain electrode pad was 1 μA, and NF was deteriorated by the leakage current. In particular, since the gate electrode pad and the drain electrode pad are formed on the same buffer layer surface, leak paths are formed due to crystal defects due to contamination and damage of the buffer layer surface, and the leak current between the electrode pads increases. Further, since the leak current between the gate electrode pad and the drain electrode pad is proportional to the area of the electrode pad, it does not change even if the gate electrode, the source electrode, and the drain electrode become smaller.

Therefore, when the absolute value of NF becomes small,
The increase in NF due to the increase in leakage current between the gate electrode pad and the drain electrode pad cannot be ignored, and it has been difficult to achieve high performance.

[0009]

The purpose of the 0008] The present invention improves the drawbacks of the prior art described above, there is provided a method of manufacturing a small semiconductor device and its noise figure.

[0010]

In order to achieve the above object, the present invention basically employs the following technical configuration. That is, a first aspect of the semiconductor device according to the present invention is a semiconductor device in which three or more buffer layers are formed on a semiconductor substrate and a semiconductor element is formed on the buffer layer. The device is characterized in that the gate electrode pad of the device is formed on a buffer layer different from the other electrode pads with one or more of the buffer layers interposed therebetween.
A first undoped GaAs buffer layer on an As substrate,
A semiconductor device in which a buffer layer including an undoped AlGaAs hetero-buffer layer and a second undoped GaAs buffer layer is formed, and a semiconductor element is formed on the buffer layer, wherein the gate electrode pad of the semiconductor is formed of the first undoped GaAs Formed on the buffer layer,
Source and drain electrode pads or drain
Only the in-electrode pad is formed on the second undoped GaAs buffer layer,
As a third aspect, a buffer layer including a first undoped GaAs buffer layer, an undoped AlGaAs hetero buffer layer, and a second undoped GaAs buffer layer is formed on a GaAs substrate, and a semiconductor element is formed on the buffer layer. A semiconductor device, comprising: a source electrode pad and a drain electrode pad of the semiconductor device ;
Means that only the drain electrode pad is
A gate electrode pad is formed on the second undoped GaAs buffer layer, and the gate electrode pad is formed on the aAs buffer layer.

[0011]

A first aspect of the method of manufacturing a semiconductor device according to the present invention is directed to a buffer including a first undoped GaAs buffer layer, an undoped AlGaAs hetero buffer layer, and a second undoped GaAs buffer layer on a GaAs substrate. A method for manufacturing a semiconductor device, comprising forming a semiconductor element on the buffer layer, comprising: a first step of forming an undoped InGaAs layer on a GaAs substrate; and an n-type A doped with an n-type impurity.
a second step of forming an lGaAs layer, a third step of forming an n-type GaAs layer doped with an n-type impurity,
N-type GaAs except for the part where the semiconductor element is formed
A fourth step of mesa-etching the layer, the n-type AlGaAs layer, and the undoped InGaAs layer, a fifth step of forming an insulating film on the etched surface, and a first portion serving as a gate electrode portion of the insulating film A sixth step of etching a second portion to be a gate electrode pad portion while etching the n-type GaAs exposed on the first portion.
a seventh step of etching the s layer, and an eighth step of sequentially etching the second undoped GaAs buffer layer and the undoped AlGaAs hetero buffer layer exposed in the second portion to expose the first undoped GaAs buffer layer. A ninth step of forming a gate electrode in the first portion sandwiched between the insulating films and forming a gate electrode pad on the first undoped GaAs buffer layer exposed in the eighth step; A tenth step of etching the insulating film into a predetermined shape to form a drain electrode pad on a second undoped GaAs buffer layer. The second mode is to form a first undoped GaAs on a GaAs substrate. Buffer layer, undoped AlGa
A method for manufacturing a semiconductor device in which a buffer layer including an As hetero buffer layer and a second undoped GaAs buffer layer is formed and a semiconductor element is formed on the buffer layer, the method comprising forming an undoped InGaAs layer on a GaAs substrate. Step 1, a second step of forming an n-type AlGaAs layer doped with an n-type impurity, a third step of forming an n-type GaAs layer doped with an n-type impurity, and a portion for forming the semiconductor element N-type Ga
As layer, n-type AlGaAs layer, undoped InGaAs
A fourth step of mesa etching the layer, the second undoped GaAs buffer layer, and the undoped AlGaAs hetero buffer layer to expose the first undoped GaAs buffer layer, and a fifth step of forming an insulating film on the etched surface. A sixth step of etching a first portion of the insulating film that will be a gate electrode portion and etching a second portion of a gate electrode pad portion, and an n-type GaAs layer exposed on the first portion. And a n-type Ga exposed on the second portion.
As layer, n-type AlGaAs layer, undoped InGaAs
An eighth step of sequentially etching the layers to expose the second undoped GaAs buffer layer, and forming a gate electrode in the first portion sandwiched between the insulating films, and forming the gate electrode exposed in the eighth step. A ninth step of forming a gate electrode pad on the second undoped GaAs buffer layer and a tenth step of etching the insulating film into a predetermined shape to form a drain electrode pad on the first undoped GaAs buffer layer. Including.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device according to the present invention comprises a plurality of buffer layers formed on a semiconductor substrate and a semiconductor element formed on the buffer layer, wherein the semiconductor device has one gate electrode pad. Since the technical configuration formed on the buffer layer different from the other electrode pads with the above buffer layer interposed therebetween is adopted, it is not affected by the leak path formed on the buffer layer surface,
In addition, the increase in the tunnel resistance reduces the gate leak current, and reduces NF.

[0014]

EXAMPLES be described in detail with reference to the accompanying drawings a specific example of a method for manufacturing a semiconductor device and its according to the present invention below. 1 to 12 are diagrams showing a first specific example of the present invention,
In the figure, a plurality of buffer layers 2, 3, 4,
Is formed, and in the semiconductor device in which the semiconductor element 14 is formed on the buffer layers 2, 3, and 4, the gate electrode pad 9 of the semiconductor device has the other electrode pads 12, 13 with one or more of the buffer layers interposed therebetween. And a first undoped GaAs buffer layer 2 and an undoped A on a GaAs substrate 1.
lGaAs hetero buffer layer 3, second undoped G
a buffer layer including the aAs buffer layer 4 is formed;
A semiconductor device having a semiconductor element formed on the buffer layer, wherein a gate electrode pad of the semiconductor device is formed on the first undoped GaAs buffer layer, and a source electrode pad or a drain electrode pad is formed.
2 shows a semiconductor device in which at least one of the electrode pads is formed on the second undoped GaAs buffer layer 4.

1 to 12, a buffer layer including a first undoped GaAs buffer layer 2, an undoped AlGaAs hetero buffer layer 3, and a second undoped GaAs buffer layer 4 is formed on a GaAs substrate 1. A method for manufacturing a semiconductor device in which a semiconductor element 14 is formed on the buffer layer, comprising: a first step of forming an undoped InGaAs layer 5 on a GaAs substrate 1;
Except for a second step of forming an n-type AlGaAs layer 6 doped with an n-type impurity, a third step of forming an n-type GaAs layer 7 doped with an n-type impurity, and a portion where the semiconductor element 14 is formed. N-type GaAs layer 7, n-type A
a fourth step of mesa-etching the lGaAs layer 6 and the undoped InGaAs layer 5, a fifth step of forming an insulating film 15 on the etched surface,
A sixth step of etching a first portion P1 to be a gate electrode portion and a second portion P2 to be a gate electrode pad portion, and etching the n-type GaAs layer 7 exposed in the first portion P1. A seventh step,
Second undoped GaAs exposed in the second portion P2
The buffer layer 4 and the undoped AlGaAs heterobuffer layer 3 are sequentially etched to form a first undoped GaAs.
an eighth step of exposing the s buffer layer 2; forming a gate electrode 8 in the first portion P1 sandwiched between the insulating films 15; and forming a first undoped GaAs buffer layer exposed in the eighth step. And a tenth step of forming the drain electrode pad 12 on the second undoped GaAs buffer layer 4 by etching the insulating film 15 into a predetermined shape. 1 shows a method for manufacturing a semiconductor device.

Next, a first embodiment of the present invention will be described in more detail with reference to the drawings. 1 is an external view as viewed from above, and FIG. 2 is a cross-sectional view taken along a line AB of FIG. FIG. 3 is a cross-sectional view taken along the line CD of FIG. First undoped GaAs on GaAs substrate 1
The buffer layer (hereinafter, referred to as a first undoped GaAs layer) 2 is 4000 °, and an undoped AlGaAs hetero buffer layer (hereinafter, referred to as an undoped AlGaAs layer).
3 is 2000 °, a second undoped GaAs buffer layer (hereinafter referred to as a second undoped GaAs layer) 4 is 200
0 °, undoped InGaAs layer (channel layer) 5 is 150 °, n-type AlGaAs layer (electron supply layer) 6 doped with an n-type impurity to about 2E10 ¹⁸ cm ^-3 is 500
{The n-type GaAs layer (contact layer) 7 doped with an n-type impurity to about 3E10 ¹⁸ cm ⁻³ is formed in order of 1000 °. The gate electrode 8 is formed on the n-type AlGaAs layer 6 after removing the n-type GaAs layer 7 to form a recess, and the gate electrode pad 9 is formed on the first undoped Ga.
It is formed on the As layer 2. Also, the source electrode 10,
The drain electrode 11 is formed on the n-type GaAs layer 7, and the source electrode pad 12 and the drain electrode pad 13 are formed on the second undoped GaAs layer 4.

Next, a method of manufacturing the semiconductor device of the first specific example will be described. 4 to 12 are sectional views shown in the order of steps. As shown in FIG. 4, a first undoped GaAs layer 2 is epitaxially grown on a GaAs substrate 1 by 4000 .ANG., An undoped AlGaAs layer 3 is 2000 .ANG., And a second undoped GaAs layer 4 is 2000.
Å Be grown.

Next, the undoped InGaAs layer 5 is
An n-type AlGaAs layer 6 formed at 0 ° and subsequently doped with an N-type impurity to about 2E10 ¹⁸ cm ⁻³ ;
N-type GaAs doped with an N-type impurity to about ¹⁸ cm ^-3
The s layer 7 is formed at 500 ° and 1000 °, respectively.
Next, an FET is manufactured using this crystal.

As shown in FIG. 5, the n-type GaAs layer 7, the n-type AlGaAs layer 6, and the undoped InGaAs layer 5, as shown in FIG. After removal, the second undoped GaAs layer 4 is exposed to perform element isolation. Next, a SiO ₂ film is formed as the insulating film 15, a photoresist 16 is applied as shown in FIGS. 7 and 8 showing cross sections AB and CD in FIG. 5, and n is exposed by an i-line stepper. Opening of 0.4 μm in insulating film 15 on n-type GaAs layer 7
100 μm × 100 μm in the recess pattern 17 of 200 μm and the insulating film 15 on the second undoped GaAs layer 4.
After the formation of the gate electrode pad pattern 18 of m, the insulating film 15 is etched and opened by dry etching.

Next, as shown in FIGS. 9 and 10 showing cross sections AB and CD in FIG. 5, the n-type GaAs layer 7 is etched and removed to expose the n-type AlGaAs layer 6. Then, the first portion P1 is covered with a photoresist 19, and the second undoped GaAs layer 4 and the undoped AlGaAs layer 3 of the gate electrode pad pattern portion 18 are etched.
The undoped GaAs layer 2 is exposed.

Next, as shown in FIG. 11, a side wall insulating film 20 (SiO ₂ ) is formed on the first portion P1, and the side wall is formed by dry etching to reduce the opening dimension of the recess to 0.2 μm. , W-Si / Ti / Au metal is sputtered to form a T-type gate electrode 8. Further, the gate electrode pad 9 is provided on the first undoped GaAs 2 with the gate electrode 8.
It is produced simultaneously with the formation of

Thereafter, as shown in FIG.
In order to form the drain electrode 11, the source electrode pad 12, and the drain electrode pad 13, after patterning with a photoresist 21, the insulating film 15 is etched, and the source electrode 10 and the drain electrode 11 of about 100 μm × 50 μm are replaced with n. Formed on the type GaAs layer 7, and
The source electrode pad 12 and the drain electrode pad 13 of m × 300 μm are formed on the second undoped GaAs layer 4 using AuGe / Ni / Au as an ohmic metal. Finally, the photoresist 21 is removed to complete the process.

The FET fabricated in this manner has a leakage current flowing between the gate electrode pad 9 and the drain electrode pad 13 of 1 pA, has a reduced NF of 0.03 dB as compared with the conventional FET, and has a NF = 12 GHz band. 0.45
dB was obtained. Next, a second specific example of the present invention will be described with reference to FIGS. 13 to 2
4 has a first undoped GaAs on a GaAs substrate 31.
a semiconductor device in which a buffer layer including an s buffer layer 32, an undoped AlGaAs hetero buffer layer 33, and a second undoped GaAs buffer layer 34 is formed, and a semiconductor element 44 is formed on the buffer layer;
At least one of the source electrode pad 42 and the drain electrode pad 43 of the semiconductor device is formed on the first undoped GaAs buffer layer 32, and the gate electrode pad 39 is formed on the second undoped Ga.
The semiconductor device formed on the As buffer layer 34 is shown.

FIGS. 13 to 24 show a first undoped GaAs buffer layer 32 on a GaAs substrate 31.
Undoped AlGaAs hetero buffer layer 33, second
A buffer layer including an undoped GaAs buffer layer 34 is formed, and a semiconductor element 44 is formed on the buffer layer.
Forming a undoped InGaAs layer 35 on a GaAs substrate 31; and n-type AlGa doped with an n-type impurity.
A second step of forming an As layer 36, a third step of forming an n-type GaAs layer 37 doped with an n-type impurity, and an n-type G
aAs layer 37, n-type AlGaAs layer 36, undoped I
a fourth step of mesa etching the nGaAs layer 35, the second undoped GaAs buffer layer 34, and the undoped AlGaAs hetero buffer layer 33 to expose the first undoped GaAs buffer layer 32, and an insulating film 45 on the etched surface. A fifth step of forming
A first portion R1 serving as a gate electrode portion of the insulating film 45;
A sixth step of etching a second portion R2 serving as a gate electrode pad portion while etching the first portion;
A seventh step of etching the n-type GaAs layer 37 exposed at the portion R1, and an n-type GaAs exposed at the second portion.
Layer 37, n-type AlGaAs layer 36, undoped InGa
The As layer 35 is sequentially etched to form a second undoped Ga layer.
An eighth step of exposing the As buffer layer 34, and forming a gate electrode 38 in the first portion R1 sandwiched by the insulating film 45.
A ninth step of forming a gate electrode pad 39 on the second undoped GaAs buffer layer 34 exposed in the eighth step, and etching the insulating film 45 into a predetermined shape to form a first step. First, a drain electrode pad 43 is formed on the undoped GaAs buffer layer 32.
0 steps.

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 13 is an external view seen from above, and FIG.
FIG. 4 is a sectional view taken along line AB in FIG. FIG. 15 is a sectional view taken along line CD of FIG. On the GaAs substrate 31, the first undoped GaAs layer 32 is 2000Å, the undoped AlGaAs layer 33 is 3000Å, the second undoped GaAs layer 34 is 2000Å, and the undoped InGaAs is formed.
The layer 35 is 150Å, the n-type AlGaAs layer 36 doped with an n-type impurity to about 2E10 ¹⁸ cm ^-3 is 500Å,
N doped with an n-type impurity to about 3E10 ¹⁸ cm ^-3
Type GaAs layers 37 are sequentially formed at 1000 °.

The gate electrode 38 is formed on the n-type AlGaAs layer 36 after removing the n-type GaAs layer 37 to form a recess, and the gate electrode pad 39 is formed on the second undoped GaAs layer 34. . Further, the source electrode 40 and the drain electrode 41 are formed on the n-type GaAs layer 37, and the source electrode pad 42 and the drain pad 43 are formed on the first undoped GaAs layer 32.

The manufacturing method of the second embodiment will be described below.
explain. 16 to 24 are sectional views shown in the order of steps.
is there. As shown in FIG. 16, the first
1 undoped GaAs layer 32 is 2000Å epitaxy
Crystal growth followed by an undoped AlGaAs layer 3
3 is 3000 °, the second undoped GaAs layer 34 is 2
Grow by $ 000. Next, an undoped InGaAs layer 3
5 are formed at 150 °, followed by 2E10¹⁸cm ^-3About
An n-type AlGaAs layer 36 doped with an n-type impurity;
3E10¹⁸cm ^-3N doped with N-type impurities
Type GaAs layers 37 are formed at 500 ° and 1000 °, respectively.
Is done.

Next, an FET is manufactured using this crystal. As shown in FIG. 17, the element portion 44 and the gate electrode pad forming portion 48 are left as isolations.
As shown in FIG. 8, the n-type GaAs layer 37 and the n-type AlGaAs layer 3 are formed by mesa etching using a photoresist.
6. The undoped InGaAs layer 35, the second undoped GaAs layer 34, and the undoped AlGaAs layer 33 are removed, and the first undoped GaAs layer 32 is exposed to perform element isolation.

Next, SiO ₂ is formed as an insulating film 45, and FIGS. 19 and 20 show cross sections AB and CD in FIG.
A photoresist 46 is applied, and a 0.4 μm × 200 μm recess pattern 47 is formed on the insulating film 45 on the n-type GaAs layer 37 by exposure using an i-line stepper.
Then, after forming a gate electrode pad pattern 48 of 100 μm × 100 μm, the insulating film 45 is etched by dry etching to form openings.

Next, as shown in FIGS. 21 and 22 showing cross sections AB and CD in FIG. 17, the n-type GaAs layer 37 is removed by etching, and then the recess pattern 47 is protected by a photoresist 49. Then, the gate electrode pad pattern portion 4
8 n-type AlGaAs layer 36, undoped InGaAs
The layer 35 is etched to form the second undoped GaAs layer 3
Expose 4.

Next, as shown in FIG.
SiO ₂ film is formed, after reducing the opening size of the recessed portion to 0.2μm to form a side wall in the dry etching, a gate electrode 38 of the T-type by sputtering metal WSi / Ti / Au formed as I do. Also, the gate electrode pad 3
9 is formed on the second undoped GaAs 34 simultaneously with the formation of the gate electrode.

Thereafter, as shown in FIG.
0, the insulating film 45 is etched to form the drain electrode 41, the source electrode pad 42, and the drain electrode pad 43, and the source electrode 4 is about 100 μm × 50 μm.
0, the drain electrode 41 is formed on the n-type GaAs layer 37, and the 100 μm × 300 μm source electrode pad 42 and the drain electrode pad 43 are the first undoped GaAs.
AuGe / Ni / as ohmic metal on the s layer 32
It is formed using Au. Finally, the photoresist 51 is removed to complete the process.

The leakage current flowing between the gate electrode pad and the drain electrode pad of the FET thus manufactured is 1 pA, and the NF is 0.03 d higher than that of the conventional FET.
B was reduced, and NF = 0.45 dB was obtained in the 12 GHz band.

[0034]

The present invention is constructed as described above.
Because the gate electrode pad and other electrode pads (drain electrode pad, source electrode pad) are formed in different layers with a hetero buffer layer with a large energy gap in between, the influence of the leak path formed on the buffer layer surface is reduced. As a result, a remarkable effect of reducing gate leakage current and reducing NF due to an increase in tunnel resistance was obtained.

[Brief description of the drawings]

FIG. 1 is a plan view of a first specific example of the present invention.

FIG. 2 is a sectional view taken along a line AB in FIG. 1;

FIG. 3 is a cross-sectional view taken along a line CD in FIG. 1, showing a state where a gate electrode pad, a drain electrode pad, and a source electrode pad are formed.

FIG. 4 is a sectional view of a first specific example of the present invention.

FIG. 5 is a plan view of a first specific example of the present invention.

FIG. 6 is a diagram showing a state in which an insulating film is formed after mesa etching according to the first specific example of the present invention.

FIG. 7 is a diagram showing a state where a first portion serving as a gate portion of the insulating film is etched.

FIG. 8 is a diagram showing a state where a second portion of the insulating film which will be a gate electrode pad portion is etched.

FIG. 9 is a diagram illustrating a state in which a first portion serving as a gate portion of the insulating film is covered with a photoresist.

FIG. 10 shows a second undoped G exposed in a second portion P2.
The aAs buffer layer and the undoped AlGaAs hetero buffer layer are sequentially etched to form a first undoped Ga
It is a figure showing the state where As buffer layer was exposed.

FIG. 11 is a diagram showing a state where a gate electrode is formed.

FIG. 12 is a diagram showing a state where a drain electrode pad and a source electrode pad are formed.

FIG. 13 is a plan view of a second specific example of the present invention.

FIG. 14 is a sectional view taken along the line AB in FIG.

FIG. 15 is a cross-sectional view taken along a line CD of FIG. 13, showing a state where a gate electrode pad, a drain electrode pad, and a source electrode pad are formed.

FIG. 16 is a sectional view of a second specific example of the present invention.

FIG. 17 is a plan view of a second specific example of the present invention.

FIG. 18 is a view showing a state in which an insulating film is formed after mesa etching according to the second specific example of the present invention.

FIG. 19 is a diagram showing a state where a first portion serving as a gate portion of the insulating film is etched.

FIG. 20 is a diagram showing a state where a second portion of the insulating film which will be a gate electrode pad portion is etched.

FIG. 21 is a diagram illustrating a state where a first portion serving as a gate portion of the insulating film is covered with a photoresist.

FIG. 22 is a view showing a state in which the second portion is further etched to expose the second undoped GaAs buffer layer.

FIG. 23 is a diagram showing a state where a gate electrode is formed.

FIG. 24 is a diagram showing a state where a drain electrode pad and a source electrode pad are formed.

FIG. 25 is a sectional view of a conventional technique.

FIG. 26 is a plan view of a conventional technique.

FIG. 27 is a cross-sectional view showing a step of a conventional technique.

FIG. 28 is a cross-sectional view showing a step in the related art.

FIG. 29 is a cross-sectional view showing a step in the related art.

FIG. 30 is a cross-sectional view showing a step of a conventional technique.

FIG. 31 is a cross-sectional view showing a step in the related art.

FIG. 32 is a plan view of a conventional technique.

FIG. 33 is a sectional view taken along line AB in FIG. 32;

FIG. 34 is a sectional view taken along line CD of FIG. 32;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... GaAs substrate 2 ... 1st undoped GaAs layer 3 ... undoped AlGaAs layer 4 ... 2nd undoped GaAs layer 5 ... undoped InGaAs layer 6 ... n-type AlGaAs layer 7. ..N-type GaAs layer 8 ... gate electrode 9 ... gate electrode pad 10 ... source electrode 11 ... drain electrode 12 ... source electrode pad 13 ... drain electrode pad 14 ... element Part 15: Insulating film (SiO ₂ ) 16: Photoresist 17: Recess forming part 18: Gate electrode pad forming part 19: Photoresist 20: Side wall insulating film 21: Photoresist 31 ・ ・ ・ GaAs substrate 32 ・ ・ ・ First undoped GaAs layer 33 ・ ・ ・ Undoped AlGaAs layer 34 ・ ・ ・ Second undoped Ga s layer 35 undoped InGaAs layer 36 n-type AlGaAs layer 37 n-type GaAs layer 38 gate electrode 39 gate electrode pad 40 source electrode 41 drain electrode 42 ... source electrode pads 43 ... drain electrode pads 44 ... element portion 45 ... insulating film (SiO ₂₎ 46 ... photoresist 47 ... recessed portion 48 ... gate electrode pad Forming part 49 Photoresist 50 Sidewall insulating film 51 Photoresist 61 GaAs substrate 62 Undoped GaAs layer 63 Undoped InGaAs layer 64 n-type AlGaAs layer 65 ... n-type GaAs layer 66 ... element part 67 ... insulating film (SiO ₂₎ 68 ... photoresist 69 ... recessing Portion 70: Gate electrode pad forming portion 71: Side wall insulating film (SiO ₂ ) 72: Gate electrode 73: Gate electrode pad 74: Source electrode 75: Drain electrode 76: Source electrode pad 77 ・ ・ ・ Drain electrode pad

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/423 H01L 29/812

Claims (5)

(57) [Claims] 1. A semiconductor device in which three or more buffer layers are formed on a semiconductor substrate and a semiconductor element is formed on the buffer layer, wherein a gate electrode pad of the semiconductor device sandwiches one or more of the buffer layers. A semiconductor device formed on a buffer layer different from the other electrode pads. 2. A first undoped Ga on a GaAs substrate.
A semiconductor device in which a buffer layer including an As buffer layer, an undoped AlGaAs hetero buffer layer, and a second undoped GaAs buffer layer is formed, and a semiconductor element is formed on the buffer layer. 1 on the undoped GaAs buffer layer, and
And a drain electrode pad or only the drain electrode pad is formed on the second undoped GaAs buffer layer. 3. A first undoped Ga on a GaAs substrate.
A semiconductor device in which a buffer layer including an As buffer layer, an undoped AlGaAs hetero buffer layer, and a second undoped GaAs buffer layer is formed, and a semiconductor element is formed on the buffer layer. A source electrode pad and a drain of the semiconductor device Electrode pad
A semiconductor device, wherein only a pad or a drain electrode pad is formed on the first undoped GaAs buffer layer, and a gate electrode pad is formed on the second undoped GaAs buffer layer. (4)First undoped Ga on a GaAs substrate
As buffer layer, undoped AlGaAs hetero buffer
Fur layer and a second undoped GaAs buffer layer.
Buffer layer is formed, and a semiconductor layer is formed on the buffer layer.
A method of manufacturing a semiconductor device having a body element formed therein, Forming undoped InGaAs layer on GaAs substrate
A first step; Form n-type AlGaAs layer doped with n-type impurity
A second step of Form an n-type GaAs layer doped with an n-type impurity
A third step; N-type GaAs except for the part where the semiconductor element is formed
Layer, n-type AlGaAs layer and undoped InGaAs layer
A fourth step of mesa etching; Fifth step of forming an insulating film on the etched surface
About Etching a first portion of the insulating film which is to be a gate electrode portion;
2nd part which becomes the gate electrode pad part while
A sixth step of etching Etching the n-type GaAs layer exposed in the first portion;
A seventh step, A second undoped GaAs buffer exposed in the second portion;
Fur layer, undoped AlGaAs hetero buffer layer
Are sequentially etched to form a first undoped GaAs buffer.
An eighth step of exposing the metal layer, Forming a gate electrode in the first portion sandwiched between the insulating films;
And the first undoped portion exposed in the eighth step.
Forming a gate electrode pad on a GaAs buffer layer
A ninth step; The insulating film is etched into a predetermined shape and a second AND
Electrode pad on GaAs buffer layer
A semiconductor device comprising:
Production method. (5)First undoped Ga on a GaAs substrate
As buffer layer, undoped AlGaAs hetero buffer
Fur layer and a second undoped GaAs buffer layer.
Buffer layer is formed, and a semiconductor layer is formed on the buffer layer.
A method of manufacturing a semiconductor device having a body element formed therein, Forming undoped InGaAs layer on GaAs substrate
A first step; Form n-type AlGaAs layer doped with n-type impurity
A second step of Form an n-type GaAs layer doped with an n-type impurity
A third step; N-type GaAs except for the part where the semiconductor element is formed
Layer, n-type AlGaAs layer, undoped InGaAs layer,
Second undoped GaAs buffer layer, undoped A
The lGaAs heterobuffer layer is mesa-etched,
The fourth exposing the undoped GaAs buffer layer
Process and Fifth step of forming an insulating film on the etched surface
About Etching a first portion of the insulating film which is to be a gate electrode portion;
2nd part which becomes the gate electrode pad part while
A sixth step of etching Etching the n-type GaAs layer exposed in the first portion;
A seventh step, An n-type GaAs layer exposed to the second portion, an n-type AlGa
As layer and undoped InGaAs layer are etched in order
To expose the second undoped GaAs buffer layer.
An eighth step, Forming a gate electrode in the first portion sandwiched between the insulating films;
And the second undoped portion exposed in the eighth step.
Forming a gate electrode pad on a GaAs buffer layer
A ninth step; The insulating film is etched into a predetermined shape and a first AND
Electrode pad on GaAs buffer layer
A semiconductor device comprising:
Production method.