JP2003309126A - Manufacturing method of heterojunction bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when a resist for forming a conventional base electrode is applied, bubbles generate in a base electrode arrangement region, desired patterning cannot be performed, and as a result, the ledge of an emitter layer is not formed on the circumference of the base electrode to cause the deterioration of characteristics. <P>SOLUTION: An air gap 202 is created by side etching between a WSi layer 10 and an emitter cap layer 6 by masking a resist 102 forming a key hole type opening in etching for forming the base electrode arrangement region 104. As a result, when a resist 103 for base and emitter electrode formation is applied, an opening for the base electrode can be accurately formed without generating the bubbles on the base electrode arrangement region 104. Since the ledge 105 of an emitter layer 5 is formed on the circumference of the base electrode 7, the deterioration of the characteristics is not caused. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a heterojunction bipolar transistor which is widely used in high output power amplifiers for transmission.

[0002]

2. Description of the Related Art A heterojunction bipolar transistor (hereinafter referred to as "HBT") is a semiconductor device having a heterojunction at its interface by making the band gaps of semiconductors used for an emitter and a base different. Compared to field effect transistors, HBTs can have a single power source,
There are various advantages such as reduction of the number of parts and high gain and low distortion in terms of characteristics. The HBT is expected as a device used for a high output power amplifier for transmission among the components of a mobile phone.

The HBT is manufactured by sequentially forming gallium arsenide (GaAs) -based layers on a semi-insulating substrate by epitaxial growth. It is manufactured by separately forming the emitter, base and collector layers by using wet etching. As the emitter layer, it is common to use a highly reliable n-type InGaP layer, which has less deterioration due to conduction than AlGaAs. Further, electrodes formed of TiPtAu, AuGeNi, etc. are connected to the formed emitter layer, base layer, and collector layer.

FIG. 3 shows a typical HBT epitaxial growth process.
The extended epi structure is shown. N on the semi-insulating substrate 1⁺Type G
aAs sub-collector layer 2 [impurity concentration 5 × 10¹⁸cm
^-3, Film thickness of about 600 nm], n-type GaAs collector layer
3 [impurity concentration 5 × 10¹⁶cm ^-3 , Thickness of about 600nm
Degree], p-type GaAs base layer 4 [impurity concentration 4 × 10¹⁹
cm^-3 , Film thickness of about 100 nm], n-type InGaP Emi
Layer 5 [impurity concentration 3 × 10¹⁷cm^-3 , Film thickness 30n
m], n⁺Type GaAs emitter cap layer 6 [impure
Material concentration 5 × 10¹⁸cm^-3 , Film thickness of about 400 nm],
By metalorganic vapor phase epitaxy (hereinafter referred to as MOCVD), etc.
Are sequentially formed.

FIG. 4 shows, for example, Japanese Patent Laid-Open No. 2001-18931.
A sectional view of a device structure of a conventional HBT having the same preferable structure as the structure shown in Japanese Patent Publication No. 9 is shown, and FIG. 5 is a plan view of the device seen from above. FIG. 4 shows AA ′ of FIG.
It is sectional drawing along.

In this HBT, semiconductor layers (2 to 6) are laminated on a semi-insulating substrate 1 as shown in FIG. 3, and WSi is used as an electrode layer for improving reliability on the emitter cap layer 6.
A (tungsten silicide) layer 10 is formed, and an emitter electrode 8 (TiPtA) connected to a wiring is further formed thereon.
u) is formed. In addition, the collector electrode 9 (made of AuGeNi / Au) is provided on the sub-collector layer 2 in the cell 30.
Sub-collector layer 2 and collector layer 3 on the outer periphery of 1 are formed in a region formed by etching. Cell 3 here
As shown in FIG. 4, 01 is a part including up to the WSi layer 10 at both ends, and represents a part in which carriers flow from the emitter cap layer 6 to the collector layer 3. Also, the cell 30
After etching the WSi layer 10, the emitter cap layer 6, and the emitter layer 5 in the central portion of 1, the base electrode 7 (T
made of iPtAu) is formed on the base layer 4.
Here, the ledge 105 of the emitter layer 5 is formed so as to surround the base electrode 7. If the ledge 105 is not present, the surface of the base layer 4 is exposed to the outside. Then, the electrons injected from the emitter electrode 8 into the base layer 5 are diffused in the direction of the base electrode 7,
Surface recombination current occurs at the portion exposed to the outside. This current causes an extra base leakage current when the device operates, which causes a decrease in current gain.

FIG. 6 is a sectional view showing a manufacturing process of the conventional HBT device. FIG. 6 shows a manufacturing process in which a cross-section BB 'is formed in FIG. 5 which is a top view of the completed device.

After the semiconductor layers (2 to 6) are sequentially formed by epitaxial growth on the semi-insulating substrate 1 as shown in FIG. 3, the WSi layer 10 is formed on the emitter cap layer 6 as shown in FIG. 6 (a). After being deposited by sputtering, a resist 101 is applied and patterned into the shape of the cell 301 (FIG. 4), that is, the same shape as the outer peripheral shape of the WSi layer 10 of FIG. Then, reactive ion beam etching (hereinafter referred to as RIE) is performed using CF ₄ and SF ₆ gas,
Inside the chamber 13.3Pa (= 100mTorr), R
Only the WSi layer 10 is etched under the condition of F120W.

Next, as shown in FIG. 6B, first, phosphoric acid:
The emitter cap layer 6 is etched using a phosphoric acid-based etchant having a ratio of hydrogen peroxide: water = 4: 1: 45. Next, the InGaP emitter layer 5 is etched using an etchant of HCl: phosphoric acid: water = 3: 2: 2. Subsequently, the phosphoric acid-based etchant is used to etch the base layer 4 and a part of the collector layer 3. After that, the resist 101 is removed.

Next, as shown in FIG. 6C, the resist 1
After applying 02, the base electrode arrangement region 104 at the center of the cell 301 is opened.

Next, as shown in FIG. 6D, the WSi layer 10 is etched by RIE in the same manner as in (a), and then only the emitter cap layer 6 is etched with the phosphoric acid-based etchant. After that, the resist 102 is removed.

Next, as shown in FIG. 6E, the oxide film 11 is formed.
After applying 2000 Å, a resist 103 is applied. At this time, bubbles 12 are formed under the resist 103 in the base electrode arrangement region 104.

Next, as shown in FIG. 6F, a resist 103 is opened to form the base electrode 7 and the emitter electrode 8. At this time, due to the bubbles 12, the resist in the base electrode arrangement region 104 is opened larger than the desired opening width of the base electrode 7.

Next, as shown in FIG. 6G, the oxide film 11 in the resist opening is first etched with hydrofluoric acid.
At this time, the oxide film 11 on the side surface of the emitter cap layer 6 is etched because the resist 103 is not formed thereon. Then, the HCl undiluted solution is used to etch the InGaP emitter layer 5 in the base electrode arrangement region 104. After that, TiPtAu is vapor-deposited to form the base electrode 7 and the emitter electrode 8.

Next, as shown in FIG. 6 (h), the resist 103 is removed by lift-off, and a collector electrode 9 (not shown) (FIGS. 4 and 5) is formed to complete the device.

[0016]

The reason why the HBT uses the circular cell structure is that the emitter layer area can be increased with respect to the base layer area, unlike the generally used comb structure. As a result, the base area can be reduced, which has the advantage of reducing the collector-base capacitance. This point is also described in JP 2001-189319 A. However, since the inside and the outside of the WSi on the emitter cap layer are etched by the self-alignment method using WSi as a mask and the processing such as the electrode formation is advanced, there are the following problems.

As shown in FIG. 6E, since the base electrode arrangement region 104 is a minute hole having a diameter of several μm, the wettability of the resist 103 is poor and bubbles 12 are formed. Then, as shown in FIG. 6F, the resist in the base electrode arrangement region 104 is opened larger than the desired opening width of the base electrode 7 due to the bubbles 12. Then Fig. 6
(G) Oxide film 1 on the side surface of the emitter cap layer 6
No. 1 has no resist 103 on it, and is therefore etched by hydrofluoric acid. After that, the emitter layer 5 on the base electrode arrangement region 104 is entirely removed by etching the emitter layer 5 with an undiluted HCl solution, and the ledge 105 (FIGS. 4 and 5) cannot be formed (in this case, the plane viewed from above). The figure is shown in FIG. 7.).

That is, with the above-described conventional manufacturing method, it is difficult to realize the configuration shown in FIGS. 4 and 5, and the ledge 105 of the emitter layer 5 that surrounds the periphery of the base electrode 7 cannot be formed. Since the surface of the layer 4 is exposed to the outside, the above-mentioned surface recombination current is generated and the current gain is reduced.

It is an object of the present invention to provide a method for manufacturing a heterojunction bipolar transistor which can form a ledge of an emitter layer around a base electrode and prevent a decrease in current gain.

[0020]

A method of manufacturing a heterojunction bipolar transistor according to the present invention comprises:
A first step of sequentially forming semiconductor layers to be a collector layer, a base layer, an emitter layer, and an emitter cap layer, a second step of forming an island-shaped emitter electrode layer on the emitter cap layer, and an emitter electrode layer The third step of etching the emitter cap layer, the emitter layer, the base layer and the collector layer in the upper part around, and applying the first resist on the entire surface after the third step, and centering the emitter electrode layer of the first resist. A region corresponding to the region and a region that is close to a predetermined portion of the outer circumference of the emitter electrode layer from this region;
Steps, and by using the first resist as a mask, the emitter electrode layer is etched and then the emitter cap layer is etched to expose the emitter layer and to approach a predetermined portion of the outer periphery of the emitter electrode layer of the first resist. A fifth step of forming a gap between the emitter electrode layer and the emitter cap layer in the vicinity of the opening region, and after removing the first resist, applying a second resist on the entire surface to form a first resist.
Process of opening a base electrode formation region, which is a region inside the resist opening region, in the second resist, and the base of the base electrode formation region by etching the emitter layer using the second resist as a mask. It includes a seventh step of exposing the layer and an eighth step of forming a base electrode on the exposed base layer.

According to the manufacturing method of the present invention, when the emitter electrode layer and the emitter cap layer are etched to expose the emitter layer in order to form the arrangement region of the base electrode,
The emitter electrode layer of the first resist is etched by using the first resist having an opening in a region corresponding to the central portion of the emitter electrode layer and a region close to a predetermined portion of the outer periphery of the emitter electrode layer as a mask. A gap can be formed by side etching between the emitter electrode layer and the emitter cap layer near the opening region close to a predetermined portion of the outer periphery of the emitter, and when the second resist for forming the base electrode is applied, The air on the layer exits to the outside through the above-mentioned voids and can be uniformly applied without generating bubbles between the emitter layer and the second resist. Thereby, the base electrode formation region can be accurately opened in the second resist, and the other emitter layer is covered with the second resist. Therefore, the second resist is used as a mask to open the emitter layer. When the base layer is exposed by etching, the emitter layer other than the base electrode formation region is not etched, and as a result, a ledge is formed around the base electrode by the emitter layer, so that the current gain is reduced. It is possible to prevent deterioration of characteristics.

In the present invention, the sixth step is the second step.
At the same time as opening the base electrode formation region in the resist of
The emitter electrode forming region on the emitter electrode layer except for the vicinity of the opening region near the outer peripheral portion of the emitter electrode layer of the first resist is opened in the second resist, and the eighth step is
By forming the base electrode at the same time as forming the base electrode in the emitter electrode forming region with the same material as the base electrode, the emitter electrode can be formed at the same time as the base electrode, and the number of steps can be reduced.

Further, in the present invention, the opening region of the first resist in the fourth step has a keyhole shape in which a protrusion is provided in a substantially circular shape, and the island-shaped emitter electrode layer formed in the second step is , And may have a portion that is substantially circular and that is parallel to the keyhole-shaped protrusion of the first resist.

In the present invention, the semi-insulating substrate is the first
It is composed of a III-V group compound semiconductor and has a collector layer of n ⁺
-Type GaAs layer and n-type GaAs layer formed thereon, p-type GaAs layer as base layer, n-type InGaP layer as emitter layer, n-type GaAs layer as emitter cap layer, and emitter electrode It is preferable that the layer is made of a layer containing WSi as a main component, and the base electrode is formed by depositing TiPtAu.

In this case, the emitter cap layer is wet-etched with a solution containing phosphoric acid in the third and fifth steps, and the emitter layer is wet-etched with a solution containing hydrochloric acid in the third and seventh steps. It is preferable.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION The HB of the embodiments of the present invention will be described below.
A method of manufacturing T (heterojunction bipolar transistor) will be described. 1A to 1C are cross-sectional views in order of the processes, showing the manufacturing method of the present embodiment, and FIG. 2 is a plan view of the completed device as seen from above. FIG. 1 shows a process in which a cross section of BB 'in FIG. 2 is formed. Further, the cross section taken along the line AA ′ of FIG. 2 in the present embodiment after completion is the same as that of FIG. 4.

On the semi-insulating substrate 1 as shown in FIG.⁺Type G
aAs sub-collector layer 2, n-type GaAs collector layer 3,
p-type GaAs base layer 4, n-type InGaP emitter layer
5, n ⁺Type GaAs emitter cap layer 6 is sequentially formed.
Then, as shown in FIG. 1A, the emitter cap layer 6 is formed.
A WSi layer (emitter electrode layer) 10 is sputtered on the
After evaporation, the resist 101 is applied and the cell 301
The shape of (FIG. 4), that is, the outer peripheral shape of the WSi layer 10 of FIG.
Pattern the same shape as. After that, by RIE
CF_FourAnd SF₆13.3 in chamber with gas
W under the condition of Pa (= 100 mTorr) and RF120W
Only the Si layer 10 is etched.

Next, as shown in FIG. 1B, first, phosphoric acid:
The emitter cap layer 6 is etched using a phosphoric acid-based etchant having a ratio of hydrogen peroxide: water = 4: 1: 45. Next, the InGaP emitter layer 5 is etched using an etchant of HCl: phosphoric acid: water = 3: 2: 2. Subsequently, the phosphoric acid-based etchant is used to etch the base layer 4 and a part of the collector layer 3. After that, the resist 101 is removed. After the etching, the eaves 13 is generated around the WSi layer 10 due to side etching.

Next, as shown in FIG. 1C, the resist 1
After applying 02, exposing and developing the cell 301 (FIG. 4)
The base electrode arrangement region 104 at the central portion of is opened. The mask used at the time of the exposure has the wiring of the base electrode 7 on which the emitter electrode 8 is not formed, as can be seen from the shape of the base electrode arrangement region 104 (the shape on the inner peripheral side of the WSi layer 10) in FIG. It has a keyhole shape with a protrusion 201 on the pull-out side (B 'side). Therefore, the resist 102
The opening part of is a keyhole type shape.

Next, as shown in FIG. 1D, the WSi layer 10 is etched by RIE in the same manner as in (a), and then only the emitter cap layer 6 is etched with the phosphoric acid-based etchant. After that, the resist 102 is removed.

At this time, a gap 202 is generated between the WSi layer 10 and the emitter cap layer 6 on the B ′ side in FIG. This is because the opening portion of the resist 102 opened using a keyhole type mask has a keyhole type shape, and B '
The contact width between the side WSi layer 10 and the emitter cap layer 6 is smaller than that in the case of FIG. As a result, FIG. 1 (b)
In (d) and (d), when the emitter cap layer 6 is etched, such a void 202 is generated due to side etching under the WSi layer 10.

Next, as shown in FIG. 1E, the resist 1
After removing 02, the oxide film 11 is applied to 2000 Å, and then the resist 103 is applied. In the process of applying, void 2
02 exists, the air between the resist 103 and the emitter layer 5 goes out through the gap 202, and the bubbles 12 as seen in FIG. 6E are not generated. Therefore, the resist 1 is evenly distributed on the base electrode arrangement region 104.
03 is painted.

At this time, in order to improve the wettability of the resist, if a mask for extending the protrusion 201 is used so that the WSi layer 10 on the B ′ side is exactly removed, the edge of the resist 102 is not exposed at the time of exposure. It may be very difficult to match the ends of the WSi layer 10. If the mask alignment at the time of exposure does not go well, the end of the protrusion 201 will be outside the cell 301. As a result, the cell 30
The layer other than 1 will be etched, resulting in a defect. Therefore, even if the mask alignment does not go well, the end of the protrusion 201 on the side B ′ is WSi.
It is necessary to use a mask in FIG. 1 (c) that allows a space to enter the inside of the outer periphery of the layer 10 and causes the void 202 when the emitter cap layer 6 is etched.

Next, as shown in FIG. 1F, a resist 103 is opened to form the base electrode 7 and the emitter electrode 8. Since there are no bubbles 12 or the like, an opening is formed on the base electrode arrangement region 104 according to the mask design value.

Next, as shown in FIG. 1G, the oxide film 11 in the opening is removed with hydrofluoric acid, and the HCl undiluted solution is used to form the InGaP emitter layer 5 in the base electrode arrangement region 104.
To etch. After that, TiPtAu is vapor-deposited.

Then, as shown in FIG. 1H, the base electrode 7 and the emitter electrode 8 are formed by lifting off. Since the ledge 105 of the emitter layer 5 is formed so as to surround the periphery of the base electrode 7, the surface recombination current does not occur and the characteristic does not deteriorate.

Although not shown in FIG. 1, as shown in FIGS. 2 and 4, the collector layer 3 around the cell 301 is formed.
And a part of the sub-collector layer 2 is removed by etching, and AuGeNi / A is formed on the removed part of the sub-collector layer 2.
A collector electrode 9 made of u is formed. In this embodiment, the collector electrode 9 is formed between the step of FIG. 1D and the step of FIG.
It may be formed at the end after the step (h).

As described above, according to the present embodiment, the WSi layer 10 and the emitter cap layer are formed by using the resist 102 having the keyhole type opening as a mask for the etching for forming the base electrode arrangement region 104. A gap 202 can be formed between the first and second layers by side etching. As a result, when the resist 103 for forming the base and emitter electrodes is applied, the base electrode arrangement region 104 is formed.
Since air bubbles 12 (FIG. 6) are not formed on the device and can be evenly applied on the device, openings for the base electrode can be accurately formed, and the ledge 105 of the emitter layer 5 is formed around the base electrode 7.
Therefore, the surface recombination current is not generated, the decrease of the current gain can be prevented, and the characteristics are not deteriorated.

The III-V used for the semi-insulating substrate 1 is used.
Group compound semiconductors differ depending on the epilayers stacked on them,
A GaAs substrate is used in the case of the present embodiment, but an InP substrate is used when the epi layer is an InAlAs layer and an InP layer, and a Ga layer is used when the epi layer is an InGaN layer and a GaN layer.
Use the N substrate.

[0040]

According to the manufacturing method of the present invention, when the emitter electrode layer and the emitter cap layer are etched to expose the emitter layer in order to form the arrangement region of the base electrode, the central portion of the emitter electrode layer is exposed. And a predetermined portion of the outer circumference of the emitter electrode layer of the first resist is etched by etching using a first resist having an opening in a region close to the predetermined portion of the outer circumference of the emitter electrode layer. An air gap can be formed between the emitter electrode layer and the emitter cap layer near the opening region by side etching, and when the second resist for forming the base electrode is applied, the air on the emitter layer has the above air gap. Therefore, it can be applied evenly without leaving bubbles between the emitter layer and the second resist. Thereby, the base electrode formation region can be accurately opened in the second resist, and the other emitter layer is covered with the second resist. Therefore, the second resist is used as a mask to open the emitter layer. When the base layer is exposed by etching, the emitter layer other than the base electrode formation region is not etched, and as a result, a ledge is formed by the emitter layer around the base electrode.
It is possible to prevent deterioration of characteristics such as a decrease in current gain.

[Brief description of drawings]

1A to 1C are cross-sectional views in order of the processes, showing a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a plan view of a heterojunction bipolar transistor manufactured according to the embodiment of the present invention as seen from above.

FIG. 3 is a cross-sectional view of a typical epi structure used to fabricate a heterojunction bipolar transistor.

FIG. 4 is a sectional view showing a preferable configuration of a conventional heterojunction bipolar transistor.

FIG. 5 is a plan view showing a preferable configuration of a conventional heterojunction bipolar transistor.

6A to 6C are cross-sectional views in order of the processes, showing a conventional method for manufacturing a heterojunction bipolar transistor.

FIG. 7 is a plan view of a heterojunction bipolar transistor manufactured by the manufacturing method shown in FIG. 6 as seen from above.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semi-insulating substrate 2 Subcollector layer (n ⁺ type GaAs) 3 Collector layer (n type GaAs) 4 Base layer (p type GaAs) 5 Emitter layer (n type InGaP) 6 Emitter cap layer (n ⁺ type GaAs) 7 Base electrode (made of TiPtAu) 8 Emitter electrode (made of TiPtAu) 9 Collector electrode (made of AuGeNi / Au) 10 WSi layer 11 Oxide film 12 Bubbles 101, 102, 103 Resist 104 Base electrode arrangement region 105 Ledge 201 Projection 202 Void 301 Cell

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshiharu Antibo             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 4M104 AA05 AA07 BB11 BB15 BB28                       CC01 DD09 DD16 DD34 DD37                       DD65 DD68 FF03 FF13 GG06                       HH14                 5F003 AP04 BA92 BB08 BB90 BE04                       BE08 BE90 BF06 BH07 BH18                       BM02 BM03 BP94 BS04 BS08                 5F043 AA14 BB07 BB08

Claims (5)

[Claims] 1. A first step of sequentially forming semiconductor layers to be a collector layer, a base layer, an emitter layer and an emitter cap layer on a semi-insulating substrate, and an island-shaped emitter on the emitter cap layer. A second step of forming an electrode layer, the emitter cap layer around the emitter electrode layer,
A third step of etching the emitter layer, the base layer, and the collector layer of the upper portion, and applying a first resist to the entire surface after the third step, corresponding to the central portion of the emitter electrode layer of the first resist. A fourth step of opening a region and a region close to a predetermined portion of the outer periphery of the emitter electrode layer from the region; and etching the emitter electrode layer using the first resist as a mask and further etching the emitter cap layer By doing so, the emitter layer is exposed and a gap is formed between the emitter cap layer and the emitter cap layer in the vicinity of the opening region of the first resist which is close to a predetermined portion of the outer periphery of the emitter electrode layer. Fifth step, after removing the first resist, a second resist is applied to the entire surface, and an opening area of the first resist is formed. A sixth step of opening a base electrode formation region, which is an inner region, in the second resist; and etching the emitter layer using the second resist as a mask to form the base of the base electrode formation region. A seventh step of exposing the layer, and an eighth step of forming a base electrode on the exposed base layer
And a method of manufacturing a heterojunction bipolar transistor including the steps of :. 2. A sixth step is to open a base electrode formation region in the second resist, and at the same time, except for the vicinity of the opening region close to a predetermined portion of the outer periphery of the emitter electrode layer of the first resist. The emitter electrode formation region on the layer is opened in the second resist, and in the eighth step, the base electrode is formed, and at the same time, the emitter electrode is formed in the emitter electrode formation region with the same material as the base electrode. The method for manufacturing a heterojunction bipolar transistor according to claim 1. 3. The opening region of the first resist in the fourth step has a keyhole shape in which a protrusion is provided in a substantially circular shape, and the island-shaped emitter electrode layer formed in the second step is a substantially circular shape. The method for manufacturing a heterojunction bipolar transistor according to claim 1 or 2, further comprising a portion that is parallel to the keyhole-shaped protrusion of the first resist. 4. A semi-insulating substrate is composed of a III-V group compound semiconductor, a collector layer is composed of an n ⁺ type GaAs layer and an n type GaAs layer formed thereon, and a base layer is formed of p.
-Type GaAs layer, the emitter layer is an n-type InGaP layer, the emitter cap layer is an n-type GaAs layer, the emitter electrode layer is a layer containing WSi as a main component, and the base electrode is formed by depositing TiPtAu. The method for manufacturing a heterojunction bipolar transistor according to claim 1, 2, or 3, wherein 5. The emitter cap layer is wet-etched with a solution containing phosphoric acid in the third step and the fifth step, and the emitter layer is wet-etched with a solution containing hydrochloric acid in the third step and the seventh step. The method for manufacturing a heterojunction bipolar transistor according to claim 4, wherein.