JP3307371B2 - Heterojunction bipolar transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor and a method of manufacturing the same, and more particularly to a heterojunction bipolar transistor having a small level difference between an emitter, a base and a collector and easy to planarize, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A heterojunction bipolar transistor (hereinafter referred to as an HBT) using a Group 3-5 compound semiconductor has excellent high-frequency characteristics and high current driving capability, and can operate with a single positive power supply. Promising applications for high-frequency devices and high-power devices in mobile communication devices and optical communication systems,
Some are already in practical use. In these applications, in the case of miniaturization of an element or an IC, ease of flattening is important. However, the conventional HBT has a vertical structure as shown in FIG.
1. In order to form each of the collector electrodes 22, it is necessary to cut a deep mesa, and a step of about 1 μm occurs between the emitter electrode 20 and the collector electrode 22. Therefore, I
In the case of C, the flattening step becomes difficult.

[0003] In the conventional HBT shown in FIG. 7, to increase the collector breakdown voltage and the collector - to reduce the base capacitance, the collector layer is formed of 10 ¹⁶ cm ^-3 units of the low-concentration n-type GaAs You. In some cases, non-do
There is also a case of ped GaAs. Therefore, it is difficult to make direct contact with the collector layer, and a high concentration n ⁺ -GaAs layer (subcollector layer 12a) of the order of 10 ¹⁸ cm ⁻³ is inserted under the collector layer, and the collector electrode 22 is placed there. Form. For this reason, the mesa stage is deeper.

To solve this problem, Japanese Patent Laid-Open Publication No. 6-14041
Gazette and F. Alexandr et al., Journal of
Crystal Gloss, 136, 235-240 (19
1994) (Alexandre et al., Journal of Crystal Gr)
owth, 136, pp. 235-240 (1994)) has proposed a method of providing a contact layer on a subcollector layer. FIG. 8 shows an example of this, in which n ⁺ -G
Contact layer 12 made of aAs and n ⁺ -InGaAs
b is formed by selective growth using CBE (Chemical Beam Epitaxy) to achieve flattening.

[0005]

The conventional HBT described above.
In the structure (1), a mesa step of 1 μm or more is formed, and planarization is difficult. Although the structure of the HBT shown in FIG. 8 is effective for eliminating the collector mesa, the subcollector layer is provided as usual, and the subcollector layer becomes a parasitic capacitance, deteriorating the device characteristics. There's a problem.

Further, since it is necessary to etch the sub-collector layer, the mesa step becomes deep, a thick selective growth layer is required, facet growth is easy, and planarization is also difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a heterojunction bipolar transistor capable of simplifying a process while facilitating planarization by using selective growth and maintaining high device characteristics, and a method of manufacturing the same.

[0008]

According to the present invention, there is provided a heterojunction bipolar transistor comprising a first conductive type collector layer, a second conductive type base layer, and a base layer formed of a Group III-V compound semiconductor thin film on a semiconductor substrate. In a heterojunction bipolar transistor in which an emitter layer of a first conductivity type having a larger forbidden band width than a layer is sequentially formed and an electrode is formed in each layer, a higher concentration than the collector layer is provided between the collector layer and the collector electrode. the first conductive type semiconductor layer of low resistance doped with an impurity is inserted into, and the first
The conductive semiconductor layer is formed of the first semiconductor layer and the second semiconductor layer.
It is characterized by comprising a laminated film .

In another heterojunction bipolar transistor according to the present invention, a first conductive type collector layer, a second conductive type base layer, and a second conductive type base layer made of a Group 3-5 compound semiconductor thin film are formed on a semiconductor substrate. In a heterojunction bipolar transistor in which an emitter layer of a first conductivity type having a large band width is sequentially formed and an electrode is formed in each layer, a part of the collector layer is removed, and a portion higher than the collector layer is formed in that part. A low-resistance first conductivity type semiconductor layer doped with impurities at a concentration and a collector electrode are sequentially formed , and the first conductivity type semiconductor layer is a first semiconductor layer.
And a laminated film of a second semiconductor layer .

Further, in the above heterojunction bipolar transistor, a low resistance semiconductor layer doped with an impurity at a higher concentration than the collector layer is formed of a semiconductor layer having a smaller forbidden band width than the collector layer. Also, this structure is characterized in that the emitter, base and collector electrodes are all formed of the same alloy.

A method of manufacturing a heterojunction bipolar transistor according to the present invention is directed to a method of manufacturing a heterojunction bipolar transistor on a semiconductor substrate, comprising a first-type collector layer, a second-type base layer, and a forbidden band width of the base layer. A heterojunction bipolar transistor including a step of sequentially epitaxially growing an emitter layer of a first conductivity type having a large resistance, wherein a low-resistance first impurity doped between the collector layer and the collector electrode with a higher concentration than the collector layer. When the conductive type semiconductor layer is formed by selective growth, the first conductive type semiconductor layer is formed.
It is characterized in that the body layer is formed of the first and second semiconductor layers .

[0012] Still another manufacturing method is to form a 3
A collector layer of the first conductivity type, a base layer of the second conductivity type, and a first group having a larger forbidden band width than the base layer.
A method of manufacturing a hetero-junction bipolar transistor including a step of sequentially epitaxially growing a conductive type emitter layer, wherein a part of said collector layer is etched, and said part is doped with impurities at a higher concentration than said collector layer. Forming a conductive semiconductor layer by selective growth
At this time, the first conductive type semiconductor layer is formed by the first and second semiconductor layers.
It is characterized by being formed by a body layer .

In the above-mentioned manufacturing method, a part of the collector layer is etched, and a low-resistance semiconductor layer doped with an impurity at a higher concentration than the collector layer is formed in the part by selective growth. Further, in the above manufacturing method, when a low-resistance semiconductor layer doped with an impurity at a higher concentration than the collector layer is formed by selective growth, the emitter cap layer is also formed simultaneously with the same semiconductor layer.

In the above manufacturing method, a semiconductor layer having a smaller forbidden band width than the collector layer may be formed by selective growth as a low-resistance semiconductor layer doped with an impurity at a higher concentration than the collector layer.

According to the present invention, a contact layer made of a high-concentration first conductivity type semiconductor layer is provided on the collector layer or on the side surface of the collector layer by selective growth, so that it is not necessary to form a collector mesa. By providing the contact layer with a certain thickness, planarization can be easily performed. If windows are formed in the collector and the emitter, the contact layer and the emitter cap layer can be formed simultaneously by selective growth, and the process can be simplified.

Further, as a contact layer, for example, G
If a semiconductor layer having a smaller forbidden band width than a collector layer of InGaAs or the like with respect to aAs is used, the contact resistance becomes low and T
The emitter, base, and collector electrodes can be formed simultaneously using an i / Pt / Au-based alloy.

[0017]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings in order to clarify the above objects, features and advantages of the present invention.

FIG. 1 is a sectional view showing the configuration of a heterojunction bipolar transistor according to a technique related to the present invention. In FIG. 1, a buffer layer 11 (thickness: 500 nm) made of i-GaAs or i-AlGaAs is formed on a semi-insulating GaAs substrate 10.
^N− doped with 5 × 10 ¹⁶ cm ⁻³ on 1
A GaAs collector layer 12 (thickness: 500 nm) is formed.

On the collector layer 12, carbon (C) is 2 ×
P ⁺ -GaAs base layer 1 doped with 10 ¹⁹ cm ^-3
3 (thickness: 80 nm) is formed on the base layer.
n-AlGaAs doped with 3 × 10 ¹⁷ cm ^{-3 of} i
Alternatively, the n-InGaP emitter layer 14 (thickness: 100
nm) is formed.

On the emitter layer 14, an emitter electrode is provided.
Therefore, high concentration of Si (1 × 10 ¹⁸cm^-3Above)
N⁺-GaAs layer 15 (thickness: 100 n)
m) and n⁺—InGaAs layer 16 (thickness: 100 nm)
Is formed. Also,
An emitter electrode made of WSi on the emitter cap layer
20 are formed.

Further, as a feature of this structure, n ⁺ doped with 1 × 10 ¹⁸ cm ⁻³ or more of Si in the external collector region.
Contact layer 18 of GaAs (thickness: 80 n)
m) + 6 * is provided, on which a collector electrode 22 made of a Ni / AuGe / Au alloy is formed. n ⁺ -G
An n ⁺ -InGaAs layer may be provided on the aAs contact layer 18, and by providing this layer, the contact resistance can be further reduced. In addition, the base electrode 21 includes
A Ti / Pt / Au alloy is used.

In the above related art , GaAs, I
The film thickness, doping concentration, and composition of nGaAs, AlGaAs, and InGaP are arbitrary as long as they are suitable for the purpose of the present structure. Although Si is used as the n-type impurity and C is used as the p-type impurity, for example, Se and Sn can be used as the n-type impurity. As the p-type impurity, any of Zn, Be, Mg, etc., which conforms to the gist of the present invention can be used.

Further, as the substrate, not only GaAs but also
Si may be used. Also, any alloy used for the electrode can be used as long as it is suitable for the purpose.

Next, a method for manufacturing a heterojunction bipolar transistor according to the related art will be described with reference to FIG. In FIG. 1, on a semi-insulating GaAs substrate 10,
Substrate temperature 600 using molecular beam epitaxy (MBE)
The buffer layer 11 made of i-GaAs (thickness: 5
Then, an n-GaAs collector layer 12 (thickness: 500 nm) doped with Si at 5 × 10 ¹⁶ cm ⁻³ is grown.

Subsequently, a p ⁺ -GaAs base layer 13 (thickness: 80 nm) doped with 4 × 10 ¹⁹ cm ^{−3 of} Be is grown. Further, an n-AlGaAs emitter layer 14 (thickness: 100 n) doped with 3 × 10 ¹⁷ cm ^{−3 of} Si.
m), n ⁺ doped with 5 × 10 ¹⁸ cm ⁻³ or more of Si
—GaAs emitter cap layer 15 (thickness: 100 n)
m), n ⁺ -InGaAs emitter cap layer 16 (thickness: 1 × 10 ¹⁹ cm ⁻³ or more doped with Si).
100 nm) in this order (FIG. 4A).

Next, an emitter electrode 20 made of WSi is formed by sputtering, masked with a photoresist 30, and processed by dry etching. Further, the emitter cap layers 15, 16 and n-AlG
The base layer is exposed by etching the aAs emitter layer 14 (FIG. 4B).

Next, the unnecessary base layer is wet-etched by masking with a photoresist 31 to expose the collector layer 12 (FIG. 4C). Then, the photoresist 31
After the removal, a window is opened only in the collector electrode portion by masking with the SiO ₂ film 32. An n ⁺ -GaAs contact layer 18 (thickness: 80 nm) doped with 1 × 10 ¹⁸ cm ⁻³ or more of Si is selectively grown on the portion by metal organic chemical vapor deposition (MOVPE) (FIG. d)). The raw materials are trimethylgallium (TMG) and arsine (AsH).
₃ ) Disilane (Si ₂ H ₆ ) was used as a Si dopant. When n ⁺ -InGaAs is selectively grown thereon, trimethylindium (TMI) may be further added as a raw material. In the case of InGaAs, 1 × 10 ¹⁹ cm
^-3 or more Si doping is possible. Finally, a photoresist mask is applied, and a base electrode 21 made of a Ti / Pt / Au alloy and a collector electrode 22 made of a Ni / AuGe / Au alloy are respectively formed by a lift-off method to complete the device (FIG. 4 (e)). )).

In the present manufacturing method, the growth method, growth conditions, composition of each layer, film thickness, doping concentration, types of n-type impurities and p-type impurities, alloys used for the electrodes, etc. are suitable for the purpose. Then, all are optional. Also in the process, any method may be used as long as it is suitable for the purpose. For example, as an etching method, dry etching may be used instead of wet etching. In particular, when AlGaAs / GaAs selective etching is used when etching the emitter cap layer, the formation of the emitter mesa is facilitated.

The selective growth can be performed not only by MOVPE but also by chloride VPE or metal organic molecular beam epitaxy (MOMBE).

The heterojunction bipolar transistor according to the present structure has a current amplification factor of 100 and a cutoff frequency (fT):
70 GHz, maximum oscillation frequency (fmax): 150 GH
z and good characteristics.

Next, a heterojunction bipolar transistor according to the first embodiment of the present invention and a method of manufacturing the same will be described.

FIG. 2 is a sectional view showing the configuration of the heterojunction bipolar transistor according to the first embodiment of the present invention. The intrinsic part of the transistor is the same as in FIG. 1 is different from FIG. 1 in that a portion of the collector layer where an electrode is formed is removed by etching, and Si is added to that portion by 1 ×.
This is to provide an n ⁺ -GaAs contact layer 18 (thickness: 580 nm) doped with 10 ¹⁸ cm ⁻³ or more, and to form the collector electrode 20 on the contact layers 18 and 19. By providing the contact layer 19 made of n ⁺ -InGaAs on the contact layer 18 made of n ⁺ -GaAs, the contact resistance can be further reduced.
The doping concentration of Si in the contact layer 19 is 1 × 10
¹⁹ cm ⁻³ or more, and Si
Is increased.

FIGS. 4A to 4C show a method of manufacturing a heterojunction bipolar transistor according to this embodiment.
This will be described with reference to FIGS. 5 (a) to 5 (c). The manufacturing method according to the present embodiment is different from the manufacturing method according to the related art in FIG. In the present embodiment, steps subsequent to FIG. 4C are shown in FIGS. 5A to 5C.

First, as in the above related art , FIGS.
4C, the buffer layer 11, the collector layer 12, the base layer 13, and the emitter layer 1 are formed on the GaAs substrate 10.
4, emitter cap layers 15 and 16, emitter electrode 20
And a photoresist 31 is formed.

Next, after masking with the SiO ₂ film 32 and opening only the collector electrode portion, the collector layer in that portion is removed by wet etching (FIG. 5).
(A)). Further, 1 × 10 ¹⁸ Si was applied to the portion removed by etching using metal organic chemical vapor deposition (MOVPE).
A contact layer 18 (thickness: 580 nm) made of n ⁺ -GaAs doped with cm ⁻³ or more is selectively grown (FIG. 5B). The raw material is trimethylgallium (TM
G), arsine (AsH ₃ ), and disilane (Si ₂ H ₆ ) as a Si dopant. On top of this, n ⁺ -InGa
When the contact layer 19 made of As is selectively grown,
Further, trimethylindium (TMI) may be added to the raw material. The impurity concentration of n ⁺ -InGaAs is 1 ×
More than 10 ¹⁹ cm ^-3 is desirable. Finally, a photoresist mask is applied, and a base electrode 21 made of a Ti / Pt / Au alloy and a collector electrode 22 made of a Ni / AuGe / Au alloy are respectively formed by a lift-off method to complete the device (FIG. 5C )).

The heterojunction bipolar transistor according to the present structure also exhibited good characteristics equal to or better than the heterojunction bipolar transistor of the related art .

Next, a heterojunction bipolar transistor according to a second embodiment of the present invention will be described. FIG. 3 is a sectional view showing the configuration of the heterojunction bipolar transistor of the present embodiment. The structure of the transistor is shown in FIG.
Same as related technology . In this structure, the contact layer provided on the collector layer 12 is formed of n ⁺ -GaAs and n ⁺ -In
It is formed of a GaAs multilayer film, and T
An i / Pt / Au alloy is used. n ⁺ -InGaAs
Has a low contact resistance with the metal, so that a contact can be made even with a Ti / Pt / Au-based metal. If the emitter cap layer is also formed of n ⁺ -InGaAs, all the contact metals are Ti / P together with the base electrode.
It can be formed of a t / Au-based alloy. As a manufacturing method, if the electrodes of the emitter, base, and collector layers are collectively formed at the end by a lift-off method, the process can be greatly simplified. Other metals that can be used for the same purpose include Ni / Ge and Pd / In. This structure can be applied to the first embodiment shown in FIG.

Next, a heterojunction bipolar transistor according to a third embodiment of the present invention and a method of manufacturing the same will be described. FIG. 6 is a cross-sectional view of a main part of the transistor for explaining the process flow.

In the same figure, a semi-insulating GaAs substrate 1
Buffer layer 11 made of i-GaAs at a substrate temperature of 600 ° C. using molecular beam epitaxy (MBE).
(Thickness: 500 nm), n-GaAs collector layer 12 doped with Si at 5 × 10 ¹⁶ cm ⁻³ (thickness: 500 n
m) grow. Subsequently, ap + -GaAs base layer 13 (thickness: 80 n) doped with Be at 4 × 10 ¹⁹ cm ^−3.
m) grow. Further, n-AlGaAs emitter layer 14 (thickness: 10 × 10 ¹⁷ cm ⁻³ doped with Si).
0 nm) (FIG. 6A).

Next, the photoresist 32 or SiO
_{Using the two} films as masks, the formation of the emitter mesas and the base layer are exposed using wet etching (FIG. 6B).
Further, the unnecessary base layer is wet-etched by masking with the photoresist 33 to expose the collector layer 12 (FIG. 6C).

Next, by masking with the SiO ₂ film 32, windows are opened only in the emitter electrode forming portion and the collector electrode forming portion. In this part, n ⁺ − doped with 1 × 10 ¹⁸ cm ⁻³ or more of Si using metal organic chemical vapor deposition (MOVPE).
Contact layer 18 of GaAs (thickness: 80 nm)
⁺ InG doped with Si and Si at 1 × 10 ¹⁹ cm ⁻³ or more
A contact layer 19 (thickness: 20 nm) made of aAs is selectively grown (FIG. 6D). The raw materials are trimethylgallium (TMG), trimethylindium (TMI),
Arsine (AsH ₃ ) and disilane (Si ₂ H ₆ ) were used as Si dopants.

Finally, a photoresist mask is applied and T
An emitter electrode 20, a base electrode 21, and a collector electrode 22 made of an i / Pt / Au alloy are formed by a lift-off method to complete the device (FIG. 6E).

In the present manufacturing method, since the contact layer and the emitter cap layer can be simultaneously formed, the process can be further simplified. This manufacturing method can be applied to the structure shown in the first embodiment (see FIG. 2).

In the present manufacturing method, the growth method, the growth conditions, the composition, the film thickness, the doping concentration of each layer, the types of n-type impurities and p-type impurities, the alloys used for the electrodes, etc., are suitable for the purpose. Then, all are optional.

Although the preferred embodiments of the present invention have been described above, it is apparent that the present invention is not limited to the above-described embodiments, but can be appropriately modified within the technical idea of the present invention. It is.

[0046]

As described above, according to the present invention,
In the hetero-junction bipolar transistor and the method of manufacturing the same, since a sub-collector layer is not used to make contact with the metal electrode, there is an effect that the parasitic capacitance can be reduced. Also, since the contact layer is formed by selective growth,
The step of the element becomes small, and flattening becomes easy. Further, by simultaneously forming the contact layer and the emitter cap layer and using the same electrode, there is an effect that the process can be simplified.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a heterojunction bipolar transistor according to a technique related to the present invention.

FIG. 2 is a structural sectional view of the heterojunction bipolar transistor according to the first embodiment of the present invention.

FIG. 3 is a structural sectional view of a heterojunction bipolar transistor according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a main part of a transistor for describing a method of manufacturing a heterojunction bipolar transistor according to a related technique of the present invention.

FIG. 5 is a cross-sectional view of a main part of the transistor for describing a method of manufacturing the heterojunction bipolar transistor according to the first embodiment of the present invention. .

FIG. 6 is a cross-sectional view of a main part of a transistor for describing a heterojunction bipolar transistor and a method of manufacturing the same according to a third embodiment of the present invention.

FIG. 7 is a structural cross-sectional view of a conventional heterojunction bipolar transistor.

FIG. 8 is a structural sectional view of a conventional heterojunction bipolar transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 GaAs substrate 11 Buffer layer 12 Collector layer 12a Sub-collector layer 12b, 18, 19 Contact layer 13 Base layer 14 Emitter layer 15, 16 Emitter cap layer 20 Emitter electrode 21 Base electrode 22 Collector electrode 30, 31, 33, 34 Photoresist 32 SiO ₂ film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 29/205 H01L 29/737

Claims (7)

(57) [Claims] 1. A first conductivity type collector layer made of a Group 3-5 compound semiconductor thin film, a second conductivity type base layer, and a first conductivity type emitter having a larger bandgap than the base layer on a semiconductor substrate. In a heterojunction bipolar transistor in which layers are sequentially formed and an electrode is formed in each layer, a low-resistance first conductivity type doped with an impurity at a higher concentration than the collector layer is provided between the collector layer and the collector electrode. The semiconductor layer is inserted and is higher than the collector layer.
Low-concentration half of the first conductivity type doped with impurities
The conductor layer is formed from a laminated film of the first semiconductor layer and the second semiconductor layer
Heterojunction bipolar transistor characterized by comprising. 2. A collector layer of a first conductivity type comprising a Group 3-5 compound semiconductor thin film, a base layer of a second conductivity type, and an emitter of a first conductivity type having a larger forbidden band width than the base layer on a semiconductor substrate. In a hetero-junction bipolar transistor in which layers are sequentially formed and an electrode is formed in each layer, a part of the collector layer is removed, and a low-resistance second impurity doped with a higher concentration than the collector layer in that part. A semiconductor layer of one conductivity type and a collector electrode are sequentially formed , and the semiconductor layer of the first conductivity type is formed as a first semiconductor layer.
A heterojunction bipolar transistor, comprising: a stacked film of a second semiconductor layer . Wherein said first semiconductor layer is an ⁿ + -GaAs, a second heterojunction bipolar transistor of the semiconductor layer is an ⁿ + -InGaAs <br/> claim 1 or 2 wherein. 4. The semiconductor device according to claim 1, wherein an impurity concentration in said second semiconductor layer is higher than an impurity concentration in said first semiconductor layer.
The heterojunction bipolar transistor according to claim 1, 2, or 3, which has a size of × 10 ¹⁹ cm ^-3 or more. 5. A semiconductor device comprising a group III-V compound semiconductor, a first conductivity type collector layer, a second conductivity type base layer, and a first conductivity type emitter layer having a larger forbidden band width than the base layer. In a method of manufacturing a heterojunction bipolar transistor including a step of sequentially epitaxially growing, a low-resistance first conductivity type semiconductor layer doped with an impurity at a higher concentration than the collector layer is selectively formed between the collector layer and a collector electrode. When performing this, the semiconductor layer of the first conductivity type is
A method for manufacturing a hetero-junction bipolar transistor, comprising a first and a second semiconductor layer . 6. A semiconductor substrate comprising a group III-V compound semiconductor, a collector layer of a first conductivity type, a base layer of a second conductivity type, and an emitter layer of a first conductivity type having a larger forbidden band width than the base layer. In a method for manufacturing a heterojunction bipolar transistor including a step of sequentially epitaxially growing, a portion of the collector layer is etched, and a portion of the collector layer is doped with an impurity at a higher concentration than the collector layer. Forming a second semiconductor layer by selective growth
At this time, the first conductive type semiconductor layer is formed by the first and second semiconductor layers.
A method for manufacturing a heterojunction bipolar transistor, wherein the method is formed by a body layer . 7. The semiconductor device according to claim 1, wherein an impurity concentration in said second semiconductor layer is higher than an impurity concentration in said first semiconductor layer.
× ¹⁰ 19 ^cm 5 also claims and as is ^-3
7. A method for manufacturing a heterojunction bipolar transistor according to item 6 .