JPH08330240A - Preparation of semiconductor epitaxial growth layer - Google Patents

Preparation of semiconductor epitaxial growth layer

Info

Publication number
JPH08330240A
JPH08330240A JP13656295A JP13656295A JPH08330240A JP H08330240 A JPH08330240 A JP H08330240A JP 13656295 A JP13656295 A JP 13656295A JP 13656295 A JP13656295 A JP 13656295A JP H08330240 A JPH08330240 A JP H08330240A
Authority
JP
Japan
Prior art keywords
layer
growth
epitaxial growth
semiconductor epitaxial
base layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13656295A
Other languages
Japanese (ja)
Inventor
Hirohiko Sugawara
裕彦 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13656295A priority Critical patent/JPH08330240A/en
Publication of JPH08330240A publication Critical patent/JPH08330240A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To obtain a preparation of a semiconductor epitaxial growth layer which can realize easily a semiconductor device which has a long-lifetime element and high reliability. CONSTITUTION: In regard to a semiconductor epitaxial growth layer for a heterojunction bipolar transistor formed by a growth according to an MOCVD method, growth temperatures of a base layer 3 and an emitter layer 4 are made to be 600-650 deg.C and from the growth temperature of the base layer to 700 deg.C respectively.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、MOCVD法により成
長されるヘテロ接合バイポーラトランジスタ用の半導体
エピタキシャル成長層の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor epitaxial growth layer for a heterojunction bipolar transistor grown by MOCVD.

【0002】[0002]

【従来の技術】AlGaAs/GaAsヘテロ接合バイ
ポーラトランジスタ(HBT)等の半導体装置を形成す
る場合に、従来その半導体エピタキシャル成長層には、
主としてMOCVD法により成長された多層構造の半導
体エピタキシャル成長層が用いられてきた。MOCVD
法によりカーボンドープ・ベースAlGaAs/GaA
sHBT用エピタキシャル成長層を成長する場合は、最
初にGaAs基板上にコレクタバッファ層とコレクタ層
を成長したのち、ベース層とエミッタ層を順次成長させ
る。このとき、ベース層はV族元素とIII族元素の構成
比であるV/III比等の通常の成長条件を大幅に変える
ことなく高濃度のカーボンをドープするために、500
〜550℃程度の比較的低温で成長させ、また、エミッ
タ層は100以上という高い電流増幅率の素子を実現す
るために、550〜590℃程度の比較的低温で成長す
ることが一般的であった。
2. Description of the Related Art When a semiconductor device such as an AlGaAs / GaAs heterojunction bipolar transistor (HBT) is formed, the semiconductor epitaxial growth layer has conventionally been
A semiconductor epitaxial growth layer having a multi-layer structure grown mainly by the MOCVD method has been used. MOCVD
Carbon-doped base AlGaAs / GaA
When growing an epitaxial growth layer for sHBT, a collector buffer layer and a collector layer are first grown on a GaAs substrate, and then a base layer and an emitter layer are sequentially grown. At this time, in order to dope the base layer with a high concentration of carbon without drastically changing the normal growth conditions such as the V / III ratio, which is the composition ratio of the group V element and the group III element,
It is common to grow at a relatively low temperature of about 550 to 590 ° C. and to grow the emitter layer at a relatively low temperature of about 550 to 590 ° C. in order to realize a device having a high current amplification factor of 100 or more. It was

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来の技術でエピタキシャル成長した半導体装置の場合
は、初期におけるHBTの電流増幅率が比較的高いにも
かかわらず、比較的短時間のうちに素子特性が劣化する
という問題があった。
However, in the case of the semiconductor device epitaxially grown by the above-mentioned conventional technique, although the HBT current amplification factor in the initial stage is relatively high, the device characteristics are relatively short. There was a problem of deterioration.

【0004】本発明は、素子寿命が長く高信頼性を有す
る半導体装置を容易に実現できる、半導体エピタキシャ
ル成長層の製造方法を得ることを目的とする。
It is an object of the present invention to obtain a method for manufacturing a semiconductor epitaxial growth layer, which can easily realize a semiconductor device having a long device life and high reliability.

【0005】[0005]

【課題を解決するための手段】上記目的は、MOCVD
法により成長するヘテロ接合バイポーラトランジスタ用
の半導体エピタキシャル成長層の製造方法において、ベ
ース層の成長温度が600℃以上650℃以下であり、
かつ、エミッタ層の成長温度が、上記ベース層の成長温
度以上で700℃以下とすることにより達成される。
The above-mentioned object is to achieve MOCVD.
In the method for manufacturing a semiconductor epitaxial growth layer for a heterojunction bipolar transistor grown by the method, the growth temperature of the base layer is 600 ° C. or higher and 650 ° C. or lower,
In addition, the growth temperature of the emitter layer is achieved by setting the growth temperature of the base layer to 700 ° C. or higher.

【0006】[0006]

【作用】上記のように比較的低温で成長させた半導体エ
ピタキシャル成長層を用いたHBTは、初期の電流増幅
率が比較的高いにもかかわらず、短時間で素子特性が劣
化する。それを防ぐため、半導体エピタキシャル成長層
の成長温度を500℃〜700℃の範囲で変化させ、エ
ピタキシャル層を成長させたところ、ベース層、エミッ
タ層の成長温度と素子寿命との間には正の相関が存在す
ることが明らかになった。すなわち、ベース層およびエ
ミッタ層の成長温度が高い半導体エピタキシャル成長層
を用いて製作した半導体装置ほど素子の寿命が長いこと
が明らかになった。これは高温で成長した半導体層ほど
再結合中心が少なく、結晶品質がすぐれているためと考
えられる。
In the HBT using the semiconductor epitaxial growth layer grown at a relatively low temperature as described above, the device characteristics deteriorate in a short time even though the initial current amplification factor is relatively high. In order to prevent this, when the growth temperature of the semiconductor epitaxial growth layer is changed in the range of 500 ° C. to 700 ° C. and the epitaxial layer is grown, a positive correlation is found between the growth temperature of the base layer and the emitter layer and the device life. It became clear that there exist. That is, it was revealed that the semiconductor device manufactured using the semiconductor epitaxial growth layer in which the growth temperature of the base layer and the emitter layer is high has a longer element life. It is considered that this is because the semiconductor layer grown at a higher temperature has less recombination centers and has better crystal quality.

【0007】なお、上記ベース層の成長温度が600℃
未満の場合は600℃以上の場合に比べて素子寿命が短
く、650℃を越えた場合には所望の高濃度カーボンを
ドープすることが困難なため、実用的な初期特性が得ら
れない。また、エミッタ層の成長温度がベース層の成長
温度に満たない場合には、ベース層の成長温度以上の場
合に比べて素子寿命が短く、エミッタの成長温度が70
0℃を越えた場合には電流増幅率の初期値が低く、初期
特性が実用的でない。
The growth temperature of the base layer is 600 ° C.
If it is less than 600 ° C., the device life is shorter than that at 600 ° C. or more, and if it exceeds 650 ° C., it is difficult to dope the desired high-concentration carbon, and practical initial characteristics cannot be obtained. Further, when the growth temperature of the emitter layer is lower than the growth temperature of the base layer, the device life is shorter than when the growth temperature of the base layer is higher than the growth temperature of the base layer, and the growth temperature of the emitter is 70%.
When the temperature exceeds 0 ° C, the initial value of the current amplification factor is low and the initial characteristics are not practical.

【0008】[0008]

【実施例】つぎに本発明の実施例を図面とともに説明す
る。図1は本発明により作製した半導体エピタキシャル
成長層を用いて形成した半導体装置の電流増幅率変化を
示す図、図2は本発明の半導体エピタキシャル成長層を
用いたヘテロ接合バイポーラトランジスタの一実施例を
示す断面図である。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a diagram showing a change in current amplification factor of a semiconductor device formed by using a semiconductor epitaxial growth layer manufactured according to the present invention, and FIG. 2 is a cross section showing an embodiment of a heterojunction bipolar transistor using the semiconductor epitaxial growth layer according to the present invention. It is a figure.

【0009】本発明に従ってベース層およびエミッタ層
の成長温度をそれぞれ600℃および650℃として形
成した、半導体エピタキシャル成長層を使用し、例えば
図2に示すようなHBTを製作した。図2において、半
絶縁性GaAs基板上に、n(+)GaAsコレクタ・
バッファ層1、i−GaAsコレクタ層2、p−GaA
sベース層3、n−AlGaAsエミッタ層4およびn
(+)GaAsエミッタ・キャップ層5を成長させる。
このときのベース層3およびエミッタ層4の成長温度
は、それぞれ600℃および650℃とする。上記成長
の半導体結晶層表面を選択的にエッチングし、エミッタ
・メサ、ベース・メサ、コレクタ・メサを形成するが、
この際、外部ベース領域にエミッタ層4の一部を残すこ
とにより、再結合電流を抑制する。コレクタ・バッファ
層1、ベース層3、エミッタ・キャップ層5上に、それ
ぞれコレクタ電極6、ベース電極7、エミッタ電極8を
形成する。なお、上記各電極部分以外はSiN膜9で覆
われている。
An HBT as shown in FIG. 2, for example, was manufactured using a semiconductor epitaxial growth layer formed according to the present invention with the growth temperatures of the base layer and the emitter layer being 600 ° C. and 650 ° C., respectively. In FIG. 2, an n (+) GaAs collector.
Buffer layer 1, i-GaAs collector layer 2, p-GaA
s base layer 3, n-AlGaAs emitter layer 4 and n
The (+) GaAs emitter cap layer 5 is grown.
The growth temperatures of the base layer 3 and the emitter layer 4 at this time are 600 ° C. and 650 ° C., respectively. The semiconductor crystal layer surface of the above growth is selectively etched to form an emitter mesa, a base mesa, and a collector mesa.
At this time, the recombination current is suppressed by leaving a part of the emitter layer 4 in the external base region. A collector electrode 6, a base electrode 7 and an emitter electrode 8 are formed on the collector / buffer layer 1, the base layer 3 and the emitter cap layer 5, respectively. The portions other than the above-mentioned electrode portions are covered with the SiN film 9.

【0010】上記HBTの電流増幅率の経時変化を示し
た図が図1である。図1には参考までにベース層の成長
温度を500℃、エミッタ層の成長温度を590℃とい
う、従来方法により成長した半導体エピタキシャル成長
層を用いて製作したHBTの場合についても、比較のた
めに併記して示している。本発明の製造方法により成長
した半導体エピタキシャル成長層を用いたHBTの場合
は、従来の半導体エピタキシャル成長層を用いたHBT
に比べて、10倍以上の長寿命を有することは図から明
らかである。本願発明によれば上記のように、従来素子
に比べてはるかに高い信頼性を有する半導体装置を、従
来素子の製造における結晶成長以降の製作工程を変更す
ることなく、容易に実現することが可能であるという利
点がある。なお、上記実施例のようにベース層の成長温
度を高くした場合には、ベース層中のキャリア濃度はや
や低下する傾向があるが、これはV/III比等の他の成
長条件を工夫することにより補うことができるので特に
問題はない。また、エミッタ層の成長温度を高くした場
合は、HBTにおける電流増幅率の初期値が低温成長の
場合に比べてやや低くなる傾向があるが、通常の回路動
作に必要な40以上程度の値は確保できるため実用上問
題はない。
FIG. 1 is a diagram showing the change over time in the current amplification factor of the HBT. For reference, FIG. 1 also shows, for comparison, the case of an HBT manufactured using a semiconductor epitaxial growth layer grown by a conventional method, in which the growth temperature of the base layer is 500 ° C. and the growth temperature of the emitter layer is 590 ° C. Is shown. In the case of the HBT using the semiconductor epitaxial growth layer grown by the manufacturing method of the present invention, the HBT using the conventional semiconductor epitaxial growth layer is used.
It is clear from the figure that it has a life of 10 times or more as compared with. According to the present invention, as described above, a semiconductor device having much higher reliability than that of the conventional element can be easily realized without changing the manufacturing process after crystal growth in the production of the conventional element. The advantage is that It should be noted that when the growth temperature of the base layer is increased as in the above-mentioned embodiment, the carrier concentration in the base layer tends to decrease slightly, but this is devised for other growth conditions such as V / III ratio. There is no particular problem because it can be compensated for. Further, when the growth temperature of the emitter layer is increased, the initial value of the current amplification factor in the HBT tends to be slightly lower than that in the case of low temperature growth, but the value of about 40 or more required for normal circuit operation is There is no practical problem because it can be secured.

【0011】種々の半導体結晶堆積膜を用いて形成され
た半導体装置について、上記実施例と同様の実験を行っ
たところ、ベース層の成長温度が600℃以上650℃
以下で、かつ、エミッタ層の成長温度がベース層の成長
温度以上でしかも700℃以下であるような半導体エピ
タキシャル成長層を用いて形成した半導体装置におい
て、上記実施例と同様の効果を確認することができた。
Experiments similar to those in the above-described examples were conducted on semiconductor devices formed by using various semiconductor crystal deposited films, and the growth temperature of the base layer was 600 ° C. or more and 650 ° C.
In the following, in the semiconductor device formed by using the semiconductor epitaxial growth layer in which the growth temperature of the emitter layer is higher than the growth temperature of the base layer and lower than 700 ° C., it is possible to confirm the same effect as that of the above embodiment. did it.

【0012】なお、本実施例ではAlGaAs/GaA
s系のHBTについて説明したが、ベース層としてAl
組成が10%程度と比較的少ないAlGaAsを用いた
場合においても、本発明は有効であって同様の効果を得
ることができる。
In this embodiment, AlGaAs / GaA is used.
The s-based HBT was explained, but Al as the base layer was used.
The present invention is effective and the same effect can be obtained even when AlGaAs having a relatively small composition of about 10% is used.

【0013】[0013]

【発明の効果】上記のように本発明による半導体エピタ
キシャル成長層の製造方法は、MOCVD法により成長
するヘテロ接合バイポーラトランジスタ用の半導体エピ
タキシャル成長層の製造方法において、ベース層の成長
温度が600℃以上650℃以下であり、かつ、エミッ
タ層の成長温度が、上記ベース層の成長温度以上で70
0℃以下であることにより、上記成長温度条件で作製し
た半導体エピタキシャル成長層を用いると、素子寿命が
長く高信頼性を有する半導体装置を、容易に実現するこ
とができるという効果がある。
As described above, the method for manufacturing a semiconductor epitaxial growth layer according to the present invention is the same as the method for manufacturing a semiconductor epitaxial growth layer for a heterojunction bipolar transistor grown by MOCVD, and the growth temperature of the base layer is 600 ° C. or more and 650 ° C. And the growth temperature of the emitter layer is equal to or higher than the growth temperature of the base layer.
When the temperature is 0 ° C. or less, the semiconductor epitaxial growth layer produced under the above growth temperature condition has an effect that a semiconductor device having a long device life and high reliability can be easily realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明により作製した半導体エピタキシャル成
長層を用いて形成した半導体装置の電流増幅率変化を示
す図である。
FIG. 1 is a diagram showing changes in current amplification factor of a semiconductor device formed using a semiconductor epitaxial growth layer manufactured according to the present invention.

【図2】本発明の半導体エピタキシャル成長を用いたヘ
テロ接合バイポーラトランジスタの一実施例を示す図で
ある。
FIG. 2 is a diagram showing an example of a heterojunction bipolar transistor using semiconductor epitaxial growth of the present invention.

【符号の説明】[Explanation of symbols]

2 i−GaAsコレクタ層 3 p−GaAsベース層 4 n−AlGaAsエミッタ層 2 i-GaAs collector layer 3 p-GaAs base layer 4 n-AlGaAs emitter layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】MOCVD法により成長するヘテロ接合バ
イポーラトランジスタ用の半導体エピタキシャル成長層
の製造方法において、ベース層の成長温度が600℃以
上650℃以下であり、かつ、エミッタ層の成長温度
が、上記ベース層の成長温度以上で700℃以下である
ことを特徴とする半導体エピタキシャル成長層の製造方
法。
1. A method of manufacturing a semiconductor epitaxial growth layer for a heterojunction bipolar transistor grown by MOCVD, wherein the growth temperature of the base layer is 600 ° C. or higher and 650 ° C. or lower, and the growth temperature of the emitter layer is the base. A method for producing a semiconductor epitaxial growth layer, characterized in that the temperature is 700 ° C. or lower at a layer growth temperature or higher.
JP13656295A 1995-06-02 1995-06-02 Preparation of semiconductor epitaxial growth layer Pending JPH08330240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13656295A JPH08330240A (en) 1995-06-02 1995-06-02 Preparation of semiconductor epitaxial growth layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13656295A JPH08330240A (en) 1995-06-02 1995-06-02 Preparation of semiconductor epitaxial growth layer

Publications (1)

Publication Number Publication Date
JPH08330240A true JPH08330240A (en) 1996-12-13

Family

ID=15178151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13656295A Pending JPH08330240A (en) 1995-06-02 1995-06-02 Preparation of semiconductor epitaxial growth layer

Country Status (1)

Country Link
JP (1) JPH08330240A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100396919B1 (en) * 2000-12-27 2003-09-02 한국전자통신연구원 Integrated semiconductor device and fabrication of this device
KR100494559B1 (en) * 2002-11-21 2005-06-13 한국전자통신연구원 Method of fabricating heterojunction bipolar transistor with emitter ledge

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100396919B1 (en) * 2000-12-27 2003-09-02 한국전자통신연구원 Integrated semiconductor device and fabrication of this device
KR100494559B1 (en) * 2002-11-21 2005-06-13 한국전자통신연구원 Method of fabricating heterojunction bipolar transistor with emitter ledge

Similar Documents

Publication Publication Date Title
JP2817995B2 (en) III-V compound semiconductor heterostructure substrate and III-V compound heterostructure semiconductor device
JPH06333937A (en) Bipolar transistor
JPH08293505A (en) Compound semiconductor device and its manufacture
JPH08162471A (en) Heterojunction bipolar transistor
JPH08306703A (en) Compound semiconductor crystal device and its fabrication
JPH08330240A (en) Preparation of semiconductor epitaxial growth layer
JP4883547B2 (en) Compound semiconductor epitaxial substrate
JPH09205101A (en) Production method for bipolar transistor
JP4961740B2 (en) Method for manufacturing compound semiconductor epitaxial substrate
JP2000323491A (en) Heterojunction bipolar transistor and manufacture thereof
JP3982109B2 (en) Method for producing compound semiconductor epitaxial wafer
JP3307371B2 (en) Heterojunction bipolar transistor and manufacturing method thereof
JP3399673B2 (en) Heterojunction bipolar transistor and method of manufacturing the same
JP2000133654A (en) Manufacture of bipolar transistor
JPH05129322A (en) Manufacture of semiconductor device
JP5543302B2 (en) Compound semiconductor wafer manufacturing method and compound semiconductor device
JP2010245547A (en) Compound semiconductor epitaxial substrate
JPH05326545A (en) Selective crystal growth method and manufacture of semiconductor device using the same
JP2001203216A (en) Semiconductor epitaxial wafer
JPH11330087A (en) Heterojunction bipolar transistor and its manufacture
JPH0729916A (en) Heterojunction bipolar transistor
JP2004079679A (en) Compound semiconductor and bipolar transistor using it
JP2001085445A (en) Heterobipolar transistor
JPS63127528A (en) Semiconductor device and manufacture thereof
JPH09162195A (en) Heterojunction bipolar transistor