JPH0883806A - Hetero junction bipolar transistor - Google Patents

Abstract

PURPOSE: To suppress the reduction in collector carrier efficiency and to achieve a high-speed operation by determining the thickness of a base region within a specific range and setting the energy of a first excitation state of electron at the base region within a range which is equal to or less than a specific electron volt from the conduction band of a collector region. CONSTITUTION: A prohibition bandwidth Ea of a semiconductor layer (base layer) 24 is in a double hetero structure which is smaller than a prohibition band Eg of a semiconductor layer (collector layer) 23 and semiconductor layers (grading layer, emitter layer, grading layer) 25, 26, and 27. Further, the thickness of the semiconductor layer 24 is equal to or less than a critical film thickness where at least dislocation occurs in either of semiconductor layers 23, 24, 25, 26, and 27 due to the stress caused by the difference of lattice constant between the semiconductor layer 24 and the semiconductor layers 23, 25, 26, and 27. Then, a quantum well structure is formed by the semiconductor layers 23, 24, 25, 26, and 27 and the semiconductor layer 24 is 5-15nm thick and then the energy of the first excitation state of electrons inside the quantum well is equal to or less than 0.05eV from the conduction band of the semiconductor layer 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor (hereinafter referred to as HBT) used for ultra-high speed LSI, ultra-high speed / large capacity optical communication, communication in the microwave band to terahertz band and the like. More specifically, the present invention relates to long life, high reliability and high speed of HBTs having a double hetero structure.

[0002]

2. Description of the Related Art It is required to improve the maximum oscillation frequency as an index for increasing the speed of a bipolar transistor. The maximum oscillation frequency f _max is

[Equation 1] Is represented. Where r _e = kT / nqI _c , R _e is the external emitter resistance, R _c is the collector series resistance, C _be , C _bc.
Is the base-emitter / base-collector junction capacitance, C _p is the parasitic capacitance, τ _F is the total electron transit time, and τ _B and τ _C are the base and collector transit times.

From the equation (1), in order to improve the maximum oscillation frequency, it is necessary to improve the cutoff frequency f _T and the base resistance R
It turns out that it is necessary to lower _B. These two factors pose conflicting requirements for the design of the base layer. That is, the base width W _B needs to be reduced in order to improve f _T , and the base width needs to be increased in order to reduce R _B. An HBT has been developed as a structure that can satisfy these conflicting requirements. In this structure, a wide bandgap emitter is used to improve the injection efficiency. As a result, the injection efficiency can be maintained at a predetermined value even if the emitter concentration is lowered, so the depletion layer between the base and emitter is set to extend to the emitter layer, and the base concentration is reduced while suppressing the tunnel current between the emitter and base. It has become possible to improve. As a result, even if the base width is reduced, the base resistance can be kept low, so that f _max can be significantly improved.

Behind the expectations for HBTs, threshold dispersion and driving capability may still be problems in GaAs FET integrated circuits. In the field of microwave ICs, GaAsFETs, which have overwhelming advantages over Si bipolar transistors, do not necessarily make full use of the performance of a single element due to wiring load capacitance and the like when the scale of integration increases in digital ICs. The operating characteristics of HBT are basically the same as those of Si bipolar transistor, and the mutual conductance is standard GaAsM.
10 to 20 times larger than ESFET (operating current 1
g _m = 40 mS in mA). With this high current drive capability,
The high speed resulting from the excellent electron transport characteristics of III-V semiconductors has been the driving force for the development of HBTs.

The features of the HBT with respect to the GaAs FET are summarized as follows: (1) High transconductance (2) Threshold is almost determined by the bandgap of the base, so it is stable (characteristic variation with epi thickness and doping concentration is small) ( 3) Since the current control depends on the potential of the base, FE
There is no characteristic deterioration due to scale-down, which is equivalent to the so-called short channel effect at T. (4) Output conductance is sufficiently small due to good input / output separation. (5) 1 / f noise due to small influence of element surface. (6) The device breakdown voltage is determined by the epi structure, and it can be made relatively large. (7) Since the intrinsic part of the device is determined by the epi structure, the influence of lithography variations is small. To date, the most successful HBT structures have been based on materials using a combination of AlGaAs and GaAs. This is mainly GaA
s electron transport characteristics are suitable for high-speed operation, and Ga
This is because there is almost no lattice mismatch between As and AlGaAs, and a high-quality heterojunction can be easily epitaxially grown.

[0006]

However, there are still some problems that cannot be overcome by the combination of AlGaAs and GaAs in the following two points.

(1) First, this material system has a short device life. HB consisting of AlGaAs and GaAs
T operates at a high current density, but at this time, a large number of defects occur in the element as the energization time increases, and for example, the current gain of the element decreases, and the element eventually becomes inoperable. The cause of this deterioration is not yet clear, but especially AlGa
This is a phenomenon peculiar to As and is considered to be unavoidable as long as AlGaAs is used. In particular, when a high concentration of Be is used as the base dopant, the current amplification factor decreases within several tens to several hundreds of hours and the device deteriorates when conducting an energization test at a high temperature of about 200 ° C. in ambient temperature. (Reference: Nozu et al., IEICE Technical Committee ED
91-163, MW91-146, ICD91-189). That is, Mean Time to Failure (MTT)
The shortcoming (F) was short. Similar results were obtained when C or Zn was used as the base dopant instead of Be, although there were some differences. These results mean that the device has poor reliability even at room temperature operation. So far, the cause of the decrease in current amplification factor in the high temperature current test is not completely understood. However, it is conceivable that the transition of non-radiative recombination centers in the base layer or the proliferation of defects at the time of high-temperature operation causes the current amplification factor to decrease.

(2) The second problem is that the power consumption is large. This is because the band gap of AlGaAs is as large as about 1.4 eV to 2.4 eV.
On the other hand, in a commonly used Si transistor, the bandgap is 1.1 eV, and therefore the operating voltage increases by several tens of percent, and an increase in power consumption cannot be avoided.

In order to avoid such a problem essentially, and to be stable, highly reliable, and preferable from the viewpoint of circuit application, it is necessary to realize an HBT having a substance having another band gap as a constituent material. is necessary. However, in general, it is impossible to obtain a sufficient lattice matching to obtain a heterojunction with any material, and there is a problem different from that of GaAs and AlGaAs. For example, in an HBT in which GaAs that does not use chemically unstable Al and InGaAs are combined, it is expected that the device life is improved and the power consumption is improved due to the small band gap of InGaAs. This InGaAs / GaAs heterojunction
In the field of optical devices that have functions and operations that are completely different from those of HBTs, it has been reported that a semiconductor laser using an InGaAs layer that is not lattice-matched with a GaAs substrate as an active layer has a long lifetime (SLYellen et al .: Electronics L
etters, 26, pp2083-2084 ('90)). However, in the field of HBT, the combination of GaAs and InGaAs has a large lattice mismatch, and so far satisfactory device characteristics have not been obtained. This is because when InGaAs is grown on a GaAs substrate, stress due to lattice mismatch increases as the film thickness increases, so that a transition occurs when the film thickness exceeds a certain film thickness (critical film thickness h _c ). FIG. 11 shows the critical film thickness and the composition ratio of In. For example, the HBT needs a hand gap difference of about 0.15 eV with respect to GaAs, and therefore an In composition ratio of 0.15 or more is required. However, the film thickness at that time is 3
It is limited to 0 nm or less. The problems described below occur under this limitation. In GaAs and InGaAs, the band gap difference is 40% and 60% on the conduction band side and the valence band side, respectively. Now, it is assumed that the npn transistor is configured and the emitter and collector are GaAs and the base is InG.
Considering the configuration of aAs, the band structure is as shown in FIG. One reason for making the double hetero structure as shown in FIG. 5 is HB of a material system using InGaAs as a base.
This is because the band gap of InGaAs at T is small, and thus the breakdown voltage between the base and the collector becomes small in the case of the normal single hetero HBT structure. Further, binary compounds such as GaAs and InP are industrially used at low cost as the substrate, but the collector layer needs to have an appropriate thickness from the viewpoint of ensuring the breakdown voltage. There is a problem that InGaAs cannot be used for the collector in order to suppress the above. In order to avoid such a problem, the collector layer has a wide bandgap G
A double hetero structure is formed using aAs, InP, or the like. In such a band structure, (1) First, the injection efficiency of the emitter becomes insufficient.
That is, the energy difference between the valence band edge of the emitter and the base must be 0.15 eV or more in order to obtain sufficient injection efficiency. To this end, the In composition ratio in the base is 0.25.
Therefore, the base film thickness needs to be set to 15 nm or less. For this reason, the base resistance increases and good device characteristics cannot be obtained. The In composition ratio in the base is 0.
In order to increase the injection efficiency while keeping the band at about 15, it is conceivable to provide a graded layer with an In composition ratio in the emitter depletion layer to smoothly connect the bands. However, in this case, the stress due to the lattice misalignment effectively increases, so that it is necessary to reduce the thickness of the base as well, and a desirable result cannot be obtained.

(2) Second, the efficiency of transportation to the collector is reduced. This is clear from the fact that an energy barrier for electrons is generated at the base-collector interface at the conduction band edge. As a result, the operating speed is rather reduced.
As a countermeasure against this, in general, a graded layer having an In composition ratio is provided in the collector depletion layer to smoothly connect the energy at the conduction band edge to eliminate the energy barrier. However, also in this case, the stress due to the lattice misalignment is effectively increased, so that it is necessary to reduce the thickness of the base as well, and a preferable result cannot be obtained.

The above-mentioned problems are generally found in the material system having the built-in lattice disorder, and the application development to the HBT has been considerably narrowed.

In order to solve the above problems, the present invention has an object to provide a highly reliable HBT having a long life and a small decrease in current amplification factor even at high temperatures.

Another object of the present invention is to improve the emitter injection efficiency without providing a graded layer on the emitter junction side and improve the collector transport efficiency without providing a graded layer on the collector junction side, and thus the base width. It is an object of the present invention to provide an HBT having a novel structure capable of reducing W _B to a critical film thickness h _c or less.

Still another object of the present invention is to make the base width W _B sufficiently thick and reduce the base resistance R _B to suppress the growth of dislocation generation in the base region.
Is to provide.

Still another object of the present invention is to increase the base width W _B to such an extent that effects such as negative differential resistance do not occur,
It is to provide a novel structure of HBT having a long life and high reliability.

[0016]

In order to solve the above problems, the first feature of the present invention is that the first conductivity type first semiconductor layer 22 formed on the semiconductor substrate 21 as shown in FIG.
And a first or second layer formed on the first semiconductor layer.
A second semiconductor layer 23 of any conductivity type, a third semiconductor layer 24 of the second conductivity type formed on the second semiconductor layer, and a third semiconductor layer 24 formed on the third semiconductor layer. And a fourth semiconductor layer 25, 26, 27 of the first conductivity type and a fifth semiconductor layer 2 of the first conductivity type formed on the fourth semiconductor layer.
8 and 29, the forbidden band width E _g of the third semiconductor layer is equal to the forbidden band width E of the second and fourth semiconductor layers.
has a double heterostructure smaller than _g , and the thickness of the third semiconductor layer 24 depends on the stress due to the difference in lattice constant between the third semiconductor layer and the second and fourth semiconductor layers. At least the critical thickness h _c at which dislocations occur in any of the second, third, or fourth semiconductor layers, and the first and second semiconductor layers, the collector region, and the third semiconductor layer are used as bases. Region, an npn or pnp bipolar transistor having an emitter top with the fourth and fifth semiconductor layers as emitter regions, forming a quantum well structure with the second, third, and fourth semiconductor layers, The thickness of the semiconductor layer 24 is 5 to 15 nm, and the energy of the first excited state of electrons inside the quantum well is an HBT within the range of 0.05 eV or less from the conduction band of the second semiconductor layer. is there. Preferably, the third semiconductor layer 24 contains In III
It is a group V compound semiconductor such as InGaAs.

A second feature of the present invention is that it is an HBT having an emitter top type double hetero structure, which is similar to the first feature, but it is provided in the vicinity of the third semiconductor region of the second and fourth semiconductor regions. A first planar doped region 3 and a second planar doped region 7 supplying charge carriers of the first conductivity type.
And the electric field generated by the planar-doped region allows the charge carriers to pass through the potential barriers at the emitter-side heterojunction and the collector-side heterojunction by the tunnel effect. Preferably, the potential drop Δ in the strong electric field region due to the collector-side planar doped region 3
V _C is larger than the first conductivity type band edge energy discontinuity ΔE _C at the collector side heterojunction (the interface between the second and third semiconductor layers), and the potential in the strong electric field region due to the emitter side planar doped region 7 is large. The drop ΔV _E is ΔE at the emitter-side heterojunction (the interface between the third and fourth semiconductor layers).
Characterized by being smaller than _C. More preferably, the second and fourth semiconductor layers are GaAs layers, and the third semiconductor layer 24 is a semiconductor layer containing In such as InGaAs. More preferably, the third semiconductor layer is made of In _x G
when the a _1-x As layer, the third thickness of the semiconductor layer (base width) W _B is, W _B <6 / x with respect to the composition of In (molar ratio) x [nm] ... (2) Is to be. Also preferably, the second and fourth semiconductor layers are Si and the fourth semiconductor layer is SiGe.

The third feature of the present invention is that it is an emitter-top type double hetero structure HBT, which is similar to the first and second features, but as shown in FIGS. The layer 8 is composed of two or more kinds of compound semiconductor layers 81, 82, 83 having different lattice constants. Preferably, the first and second semiconductor layers 22 and 23 are Ga
The third semiconductor layer 8 is an As layer, and the third semiconductor layer 8 includes a plurality of In _x Ga layers.
_{The 1-x} As layer 82 and the GaAs layer 81 are alternately laminated, and the In composition (molar ratio) x is 0.2 or less, and the In _x Ga _1-x As layer 82 is a _single layer film. Thickness is 12 nm
And the total thickness of the third semiconductor layer is 10 to 1
It is to be 00 nm. More preferably, the fourth semiconductor layer is the InGaP layer 91 or the AlGaAs layer 26.
It is any of 6. More preferably, the uppermost layer of the third semiconductor layer 8, that is, the layer on the emitter junction side is G
That is, the aAs layers 81 and 83. When it is desired to suppress the effects of negative differential resistance, the GaAs layers 81, 83,
In the superlattice structure formed by the InGaAs layer 82, G
It is to be thick enough not to cause quantum mechanical coupling between the aAs layers 81 and 83 and the InGaAs layer 82, that is, sufficiently thick as compared with the de Broglie wavelength.

[0019]

In the HBT of the first feature of the present invention, since the thickness W _B of the base region (third semiconductor layer) 24 is as thin as 5 to 15 nm, the occurrence and multiplication of transition into the base region is prevented. There is little reduction in the current amplification factor due to energization. Moreover a double heterostructure sandwiching a small base region bandgap E _g a large emitter and collector regions of the bandgap E _g, the quantum well is formed relates the base area, as shown in FIG. Figure 5 is a band structure in the case where the emitter region, GaAs layer collector region, a base region and an In _x Ga _1-x As layer. If the composition of In is x = 0.2, band discontinuity ΔEc = 0.1e generated in the conduction band
It becomes V. When the base width W _B is thin below the de Broglie wavelength of electrons, the energy level of electrons inside the well-type potential having the depth ΔE _C and width W _B shown in FIG. 5, that is, the conduction band level and valence electrons Each band level is quantized. The minimum quantized conduction level is the ground state (E
₀ ), and the next smallest value is the first excited state (E ₁ ), and the electron energy level with respect to the base width W _B is obtained. It can be seen that the electron energy levels in the ground state (E ₀ ) and the first excited state (E ₁ ) increase as the base width W _B , that is, the well width, decreases. From Figure 6
In the n _0.5 Ga _0.5 As / GaAs double hetero structure, when the base width W _B is 5 to 15 nm, the electron energy level E ₁ in the first excited state is in the range of 0.05 eV from the conduction band edge of the collector layer. to go into. Therefore, the electrons injected from the emitter to the base travel on the energy level E ₁ of the first excited state before relaxing to the energy level E ₀ of the ground state, so that the electrons at the base-collector interface. The barrier to feel is smaller than ΔE _C. Therefore, the probability of passing through the potential barrier at the base-collector interface due to the tunnel effect also increases, and the transport efficiency to the collector side decreases. That is, the potential barrier due to the collector-side heterojunction is relatively smaller than that when the base width W _B is thick, and the resistance between the base and the collector is effectively reduced.

In the HBT of the second feature of the present invention, in order to improve the emitter injection efficiency and the collector transport efficiency, electrons or holes pass through the potential barriers at the emitter side heterojunction interface and the collector side heterojunction interface by tunnel effect. To do. Therefore, it is not necessary to provide the inclined layers on the emitter junction side and the collector junction side, and the base width W _B can be set to the critical film thickness h _c or less. In _x Ga _1-x A of the base region in FIG.
If the composition x of s is 0.15, the discontinuity of the band occurring in the conduction band is ΔE _C = 0.06 eV. If the barrier on the conduction band side has a triangular potential shape and the WKB approximation can be used, the tunnel probability is

[Equation 2] Here, F is the electric field intensity in the barrier, and ΔE _C is the energy difference at the conduction band edge shown in FIG. FIG. 7 is a calculation of tunnel probability as a function of electric field strength. It can be seen from FIG. 7 that a sufficient tunnel probability can be obtained by providing 10 ⁸ V / m as the electric field strength in the barrier.

In the second aspect of the present invention, the second and third aspects are provided.
Semiconductor region of the wide gap side (GaAs
The planar doped region (donor sheet) is inserted in the side). The change in the electric field strength at both ends of the donor sheet (planar-doped region) depends on the donor sheet concentration N _s (cm
^-2 )

(Equation 3) Here, q is the elementary charge, and ε is the dielectric constant in GaAs.

Now, if F ₁ = F and F ₂ ≈0,

[Equation 4] Therefore, N _s ≈7 × 10 ¹² cm ^-2 . In order to prevent the flow of electrons from being disturbed, as shown in FIG. 8, the conduction band edge of the low electric field region of the emitter has higher energy than the conduction band edge of the base on the emitter side and the conduction band edge of the low electric field region of the collector on the collector side. Is preferably lower in energy than the conduction band edge of the base. Therefore, the positions of the donor sheet from the heterojunction are ΔX _E and Δ on the emitter side and the collector side, respectively.
X _C is the voltage drop ΔV _E in the strong electric field region on the emitter side and the voltage effect ΔV _C on the collector side.

(Equation 5) Now, if ΔV _E = 0.06 V and ΔV _C = 0.15 V, then ΔX _E = 0.6 nm and ΔX _C = 1.5 nm. It is considered that there is an upper limit to the range in which the concentration of the donor sheet in the planar doped region can be realized. It travels at high speed without reducing transport efficiency at the interface. That is, ΔV _C may be larger than ΔE _C and ΔV _E may be smaller than ΔE _C. pn
In the p-type HBT, the electric field strength in the vicinity of the emitter-base interface is increased so that holes can tunnel through the hetero barrier generated at the emitter-base interface, and
If the electric field strength near the base-collector interface is increased so that holes can pass through the barrier layer in the conduction band near the collector interface due to the tunnel effect, the transport efficiency at the heterojunction interface does not decrease.

The third feature of the present invention is that in the HBT, the semiconductor layer 82 in which the base layer 8 is lattice-matched with the substrate 21, the first semiconductor layer 22 and the second semiconductor layer 23 is not lattice-matched with the semiconductor layers 81 and 83. By using a structure in which two or more kinds of semiconductor layers having different lattice constants are alternately laminated, each layer uses a layer having a critical film thickness h _c or less, and the total thickness is maintained while maintaining strain. It is possible to change the film thickness W _{B of the} base layer to 100 nm, which is much larger than the practically necessary film thickness for ensuring a low base resistance, for example, h _c .

Further, by forming the emitter layer with InGaP91 and the emitter end of the base layer with the GaAs layer 83, the emitter layer can be selectively removed with respect to the base layer in the emitter layer removing step in the base electrode forming step. Is. At this time, since the base electrode 32 formed on the base layer is formed directly on the GaAs layers 83 and 81, the heat resistance is improved as compared with the case where it is formed on InGaAs.

Furthermore, if the film thickness and energy gap of each layer are controlled so that quantum mechanical coupling due to tunneling current or the like does not occur between the layers in the base layer, unfavorable effects on transistor operation such as negative differential resistance will be obtained. It is possible to avoid.

[0026]

1 is a sectional view of an emitter top npn type HBT according to an embodiment of the present invention. Semi-insulating GaAs
N ⁺ type GaAs collector contact layer 22, n type GaAs collector layer 23, p ⁺ type InGaA on the substrate 21 in this order.
s base layer 24, n-type Al _x Ga _1-x As layer 25, n-type Al _0.3 Ga _0.7 As emitter layer 26, n-type Al _x Ga
_1-x As layer 27, n-type In _y Ga _1-y As layer 28, n ⁺
The type In _0.5 Ga _0.5 As emitter contact layer 29 has a laminated structure. Here, for example, n ⁺ type GaAs
Collector contact layer 22 is 500 nm, Si concentration is 6 ×
10 ¹⁸ cm ⁻³ , n-type GaAs collector layer 23 is 600 n
m, Si concentration 5 × 10 ¹⁶ cm ⁻³ , p ⁺ type InGaAs base layer 24 is 7 nm, Be concentration 5 × 10 ¹⁹ cm ⁻³ , n type Al _x Ga _1-x As layer 25 is 30 nm, Si concentration 1 × 1
0 ¹⁸ cm ⁻³ , n-type Al _0.3 Ga _0.7 As emitter layer 26
Is 30 nm, Si concentration is 1 × 10 ¹⁸ cm ⁻³ , n-type Al _x G
a _1-x As layer 27 is 30 nm, Si concentration is 1 × 10 ¹⁸ cm
^-3 , the n-type InGa _1-y As layer 28 is 50 nm, the Si concentration is 3 × 10 ¹⁹ cm ^-3 , the n ⁺ -type In _0.5 GaAs _0.5 As emitter contact layer 29 is 50 nm, and the Si concentration is 3 × 10 3.
^{It is 19} cm ^-3 .

In FIG. 1, Ti / P is used as the emitter electrode 31.
t / Au is formed on the n ⁺ type In _0.5 Ga _0.5 As emitter contact layer 29 as Pt / Ti / Pt as a base electrode.
/ Au on the p ⁺ type InGaAs base layer 24, and AuGe / Ni / Ti / Au as the collector electrode on the n ⁺ type G
It has a structure in which it is laminated on each of the aAs collector contact layers. p ⁺ type InGaAs base layer 24 is 7
Since the thickness is as thin as nm, the energy level of the first excited state in the base layer is 0.05 eV from the conduction band of the collector layer.
Electrons injected from the emitter within the range of (1) hardly sense the potential barrier at the base-collector interface.

To manufacture the HBT shown in FIG. 1, first,
Low pressure MOCVD method, MBE method, CBE method (Chemical Beam
Epitaxy method) or MLE method (Molecular Layer Epi
tary method) or the like to form GaAs on the GaAs substrate 21.
Layers 22 and 23, InGaAs layer 24, AlGaAs layer 2
5, 26, 27 and InGaAs layers 28, 29 are formed.

For example, when growing by the CBE method, pressure 1.
At 3 × 10 ⁻³ Pa, substrate temperature of 520 ° C., TEG
(Triethylgallium) and AsH ₃ (arsine) were introduced to grow GaAs layers 22 and 23, and TEG and TMIn
InGaA by (trimethylindium) and AsH ₃
The s layer 24 is grown, and the AlGaAs layers 25 and 26 are formed by using TMAl (trimethylaluminum), TEG and AsH ₃ .
27, and InGa with TEG, TMIn and AsH ₃
The As layers 28 and 29 may be continuously grown in the same chamber. Instead of AsH ₃ , TBA (tertiary
Butyl arsine ((C ₄ H ₉ ) AsH ₂ )) may be used. As the p-type dopant gas, for example, solid B is used.
e source may be used. As n-type dopant gas, SiH ₄ (monosilane), Si ₂ H ₆ (disilane),
Alternatively, DESe (diethyl selenium), DETe (diethyl tellurium), or the like may be used. Further, if the source gas used for the CBE method is alternately introduced and the exchange surface reaction on the semiconductor substrate is used, the MLE method is obtained. For example, substrate temperature 450
Introduce TEG for 4 seconds at ℃ and pressure of 6 × 10 ^-4 Pa, 3
Second evacuation, AsH ₃ is introduced for 20 seconds, and then GaAs 1 molecular layer can be grown by 1 cycle of 3 seconds evacuation gas introduction. Therefore, according to the MLE method, the laminated wafer of FIG. 1 has a structure with an accuracy of a molecular layer unit. Becomes

Next, a mask pattern for etching the U-groove for taking out the base electrode is formed on this wafer with a photoresist, and the InGaAs layers 29, 2 are formed by using the mask pattern.
8 and AlGaAs layers 27, 26 and 25 are formed on the base layer 24 by RIE or ECR ion etching.
Etching is performed so that the Al _x Ga _1-x As layer 25 remains thin to form a U groove. Then, with the photoresist mask attached, the semiconductor layer on the sidewall of the U groove is slightly side-etched by wet etching. The amount of this side etching determines the separation between the base electrode and the emitter region. The optimum value of the side etching amount depends on the structure of the epitaxial film, the film quality, the pattern size, etc., but may be about 0.1 μm. Here, dry etching is used as the main etching means, but wet etching alone is also possible. Then Pt / for the base electrode
A base electrode 32 is formed on the bottom of the U groove by a so-called lift-off method in which Ti / Pt / Au is vapor-deposited on the entire surface of the wafer and then the photoresist is removed. After that, heat treatment is performed at about 350 ° C. in a lamp annealing furnace or the like, and Pt in the lowermost layer of the base electrode layer 32 is reacted and diffused with the nAlGaAs layer 25 to obtain electrical contact with the base layer 24. Note that although FIG. 1 is schematic and gives the impression that the base electrode layer 32 is not in contact with the base layer, it is in contact with the alloy layer of Pt. Through such a manufacturing process, the base region has a structure that also has a guard ring, and an improvement in current amplification factor can be obtained. Next, in order to form an insulating layer for the base electrode and the emitter electrode, a prepolymer solution of a polyimide resin is applied to the entire surface of the substrate by a spin coating method, and the polyimide resin is heated stepwise to a thermosetting temperature (350 ° C.). Then, the polyimide resin 34 is formed on the entire surface. Next, the polyimide resin is etched until the n ⁺ type In _0.5 Ga _0.5 As emitter contact layer 29 is exposed by the RIE method using CF ₄ / O ₂ , etc., and the polyimide resin 34 is formed only on the base electrode 32 in the U groove. leave. Then, Ti / Pt / Au is vacuum-deposited and patterned by photolithography as shown in FIG. 1 to form an emitter electrode 31. Then, an element isolation region 35 is formed by proton ion implantation, and finally the n ⁺ type GaAs collector contact layer 22 is exposed by wet etching to expose AuGe / Ni / Ti / Au.
Is vapor-deposited, patterned, and alloyed by heat treatment at about 370 ° C. to form a collector electrode 33 as shown in FIG. In this process, the contact hole opening for forming the emitter electrode is formed in a self-aligned manner,
The emitter area can be reduced and the structure is suitable for high frequency operation.

Of course, in the first embodiment of the present invention, the emitter layer may be made of other materials such as GaAs, InGaAs and InP.

FIG. 2 shows an emitter top npn type HBT according to a second embodiment of the present invention, in which the base layer is made thicker than in the first embodiment, and the energy level of the first excited state of electrons in the base layer is This is the case when it is made ineffective and, instead, electrons can pass through the base-collector interface by the tunnel effect. As shown in FIG. 2, n ⁺ with a thickness of 500 nm and a doping concentration of 5 × 10 ¹⁸ cm ⁻³ is formed on the semi-insulating GaAs substrate 21.
Type GaAs collector contact layer 22, thickness 300 nm
Undoped n-type GaAs collector layer 23, a 7 × 10 ¹² cm ⁻² Si planar-doped region 3 on the undoped n-type GaAs collector layer 23, and a 1.6 nm-thickness 1 undoped n-type GaAs collector layer 233 on which a 20 nm thick In _0.15 Ga _0.85 As base layer 24 doped with Be acceptor 5 × 10 ¹⁹ cm ⁻³ , and 1.6 nm of undoped GaAs
A layer 234, a 7 × 10 ¹² cm ⁻² planar-doped region 7 of Si, a 500 nm thick doping layer on the n-type GaAs emitter layer 236 having a doping concentration of 5 × 10 ¹⁷ cm ⁻³ , and a 700 nm thick doping layer thereon. Concentration 5 × 10 ¹⁸
A cm ⁻³ n ⁺ type GaAs emitter contact layer 237 is formed.

The manufacture of the second embodiment of the present invention can be performed by the same process as that of the first embodiment of the present invention described above. In addition,
In the first embodiment of the present invention, the U-groove etching of the base is performed so that the emitter layer 25 remains thin on the base layer 24, and then Pt of the bottom layer of the base metal reacts (alloys) with the emitter layer. Although the electric contact is made with the base layer 24, it is not limited to this method. In the second embodiment of the present invention, InGaAs is used for the base layer 24,
Since GaAs is used for the emitter layers 234, 236 and 237, InGaAs is selectively etched by GaAs.
It is also possible to precisely control the depth of the U-groove by using the layer 24 as an etching stopper. In this case, the base electrode 32 may be a so-called non-alloy contact that is not heat-treated.

The second embodiment of the present invention is not limited to III-V group compound semiconductors, but pnp type Si / SiGe.
It can also be applied to a double hetero structure HBT. In this case, the first to fifth semiconductor layers are formed by MBE method, ultra high vacuum CVD method, M
The continuous epitaxial growth may be performed by the LE method or the like. The ultra-high vacuum CVD method can be performed at a substrate temperature of 550 ° C to 700 ° C. If the MLE method using alternate introduction with SiH ₂ Cl ₂ , GeH ₄ and H ₂ is used, one molecule layer of Si / Si
HBT of Ge can be done. Boron (B) may be used for the planar doped layers 3 and 7.

FIG. 3 shows a sectional structure of an emitter top npn type HBT according to an embodiment of the present invention. This InGaP emitter / (InGaAs / GaAs) base HBT is a 500 nm thick n ⁺ type G on a semi-insulating GaAs substrate 21.
aAs collector contact layer (Si-doped: 5 × 10 ¹⁸
cm ⁻³ ) 22, 200 nm thick n-type GaAs collector layer (Si-doped 5 × 10 ¹⁶ cm ⁻³ ) 23, p-strained base layer 8, 85 nm thick nIn _0.5 Ga _0.5 P emitter layer (Si-doped: 5 × 10 ¹⁷ cm ^-3 ) 91, thickness 100n
m n-type GaAs layer (Si-doped: 5 × 10 ¹⁸ cm ⁻³ )
239, an n ⁺ type InGaAs emitter contact layer (Si doping: 2 × 10 ¹⁹ cm ⁻³ ) 29 having a thickness of 100 nm is sequentially laminated. The p strained base layer 8 is a GaAs layer (C-doped: 5 × 10 5 nm thick) from the substrate side.
¹⁹ cm ⁻³ ) 81, 4 nm thick In _0.2 Ga _0.8 As layer (C-doped: 2 × 10 ²⁰ cm ⁻³ ) 82, GaAs layer 8
1, an In _0.2 G _0.8 As layer 82, and a GaAs layer (C-doped: 5 × 10 ¹⁹ cm ⁻³ ) 83 having a thickness of 10 nm are alternately laminated. Is 28 nm. GaAs layer 83 only 10
It is as thick as nm. The In molar ratio in the nInGaP emitter layer 91 is selected so as to be approximately lattice-matched with the GaAs substrate 1. The Ti / Pt / Au emitter metal electrode 31 is an n ⁺ type InGaAs emitter contact layer 29.
A Ti / Pt / Au metal base electrode 32 on top of the p-strained base layer 8 on top of the GaAs layer 83, AuGe.
A / Ni / Au metal collector electrode is formed on the n ⁺ type GaAs collector contact layer 22. In this structure, the etching depth of the U groove for forming the base electrode is InGaP.
Since it can be performed using selective etching for GaAs, it has an advantage that it can be accurately controlled. That is, since the etching rate of a hydrochloric acid-based etchant such as HCl: H ₂ O or HCl: H ₃ PO ₄ is high for InGaP and InGaAs and very low for GaAs, the GaAs layer 83 acts as an etching stopper. The precise etching depth can be controlled.
In addition, the Ti / Pt / Au metal base electrode 32 is made of InG.
Since it is formed not on the aAs layer but on the GaAs layer 83, the metal / semiconductor junction of the base electrode portion has excellent heat resistance.

FIG. 4 is a cross-sectional structure of an emitter top npn type HBT according to the fourth embodiment of the present invention.
It has a strained base layer 8. Semi-insulating GaAs substrate 2
N ⁺ -type GaAs collector contact layer (Si-doped: 5 × 10 ¹⁸ cm ⁻³ ) 22 having a thickness of 500 nm and a thickness of 2
00 nm n-type GaAs collector layer (Si-doped: 5 ×
10 ¹⁶ cm ^-3 ) 23, p strained base layer 8, thickness 100n
m nAlGaAs emitter layer (Si-doped: 5 × 10
¹⁷ cm ⁻³ ) 266, 100 nm thick n-type GaAs layer (Si doping: 5 × 10 ¹⁸ cm ⁻³ ) 239, thickness 100
nm n ⁺ type InGaAs emitter contact layer (Si
Dope: 2 × 10 ¹⁹ cm ⁻³ ) 29 is sequentially laminated and configured. The p-strain base layer 8 is GaAs with a thickness of 5 nm.
Layer (C-doped: 5 × 10 ¹⁹ cm ⁻³ ) 81 and thickness 4n
m In _0.2 G _0.8 As layer (C-doped: 5 × 10 ¹⁹ cm
^-3 ) 82 is alternately laminated, and the emitter end and the collector end are a GaAs layer (C-doped: 5 × 10 ¹⁹ cm ^-3 ) 81 having a thickness of 5 nm, and the p-strained base layer 8
The total film thickness is 50 nm.

Although the emitter-top type HBT has been described in the above embodiments, the present invention may of course be applied to a collector-top type HBT.

[0038]

As described above, according to the present invention as set forth in claim 1, since the base layer (third semiconductor layer) 24 is as thin as 5 to 15 nm, the decrease in current amplification factor due to energization is small, Excellent long-term reliability. For example, the HBT shown in the first embodiment of the present invention is heated at 200 ° C. to 10 ⁵ A / cm ²
The MTTF when operated at the current density of 10 ⁸ hours was 10 ⁸ hours, and the lifespan of 100 times or more of the conventional HBT of AlGaAs / GaAs was achieved. Moreover, according to the present invention as set forth in claim 1, by using the energy level of the first excited state of the electrons in the base region, the reduction of the transport efficiency to the collector due to the potential barrier at the base-collector interface is suppressed, and g _m Is increased, and high speed operation becomes possible. FIG. 9 shows a typical I- of the HBT according to the first embodiment of the present invention.
6 is a comparison of the V characteristic and the I _C -V _CE characteristic of the HBT having the thick base layer in the conventional technique. It can be seen that the on-resistance is smaller, the rising of the current is steeper, and g _m is increased as compared with the conventional technique.

According to the second aspect of the present invention, in the double heterostructure HBT, the base width W _B can be reduced without lowering the emitter injection efficiency and the collector transport efficiency. Ie the emitter-base interface,
Further, the emitter injection efficiency and collector transport efficiency can be improved without providing the composition / gradient layer at the base / collector interface. Therefore, the base width W _B can be made equal to or less than the critical film thickness h _c , the generation and multiplication of dislocations are suppressed, and the current gain is not deteriorated even if a material having a lattice mismatch is used. According to the HBT according to the second example of the present invention, the MTTF when operating at a current density of 10 ⁵ A / cm ² at 200 ° C. was 10 ⁸ hours. According to the second aspect of the present invention, a double heterostructure HBT made of a combination of various materials causing lattice mismatch can be obtained with high reliability and long life. FIG. 10 shows the HBT shown in the second embodiment of the present invention, the HBT without the planar doped layers 3 and 7 (conventional example), the planar doped layer 7 is not present on the emitter junction side, and the planar doped layer is only on the collector junction side. The HBT (reference example) with the layer 3 is prepared and the current gains thereof are compared. In the conventional example, the electrons were significantly accumulated due to the hetero barrier at the collector-base interface, and the current gain could not be obtained (1 or less). On the other hand, in the reference example, the problem of the hetero barrier at the collector-base interface is alleviated, so that the current gain is improved to 20, but it cannot be said that the characteristics are still sufficient. On the other hand, in the HBT of the second embodiment of the present invention, the emitter injection efficiency was also improved, so that the current gain was 400 and a remarkable improvement was obtained. Therefore, according to the second aspect of the present invention, it is possible to realize a long service life and high reliability, and at the same time, to realize high frequency and high output. In particular, since it is stable at high temperatures, a large current can flow and it is easy to achieve high output.

According to the present invention as set forth in claim 3, since the base layer 8 is a composite film, it is much thicker than the critical film thickness h _{c in} the case of a single layer, and the whole film layer of the base layer 8 is formed. Therefore, the base resistance R _B of the HBT can be reduced while maintaining the characteristics of long life and high reliability. formula
As shown in (1), the main and essential factor that determines the high frequency characteristics of the bipolar transistor is R _B , and according to the present invention, the high frequency of the HBT can be easily realized. Further, according to the present invention of claim 3, the uppermost layer of the base layer 8 can be a GaAs layer. In this case,
The etching for forming the base electrode is realized by the selective etching, and the uppermost GaAs layers 83, 81 of the base layer 8 are formed.
Acts as a stopper, which enables precise control of the base width W _{B and the} like. Moreover, the metal / semiconductor interface of the base electrode has high thermal stability. Therefore, high reproducibility in manufacturing, reliability and productivity are improved, and at the same time, higher characteristics and longer life can be realized as characteristics of the HBT itself. Further, according to the present invention of claim 3, even if the base layer 8 is thickened to the extent that quantum mechanical coupling does not occur, generation and multiplication of dislocations in the base layer 8 can be suppressed. In addition, it is possible to prevent unfavorable effects such as negative differential resistance, and at the same time realize a long service life and high reliability of the HBT.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an HBT according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of an HBT according to a second embodiment of the present invention.

FIG. 3 is a schematic sectional view of an HBT according to a third embodiment of the present invention.

FIG. 4 is a schematic sectional view of an HBT according to a fourth embodiment of the present invention.

FIG. 5 is an energy band diagram of a GaAs / InGaAs / GaAs double heterostructure HBT.

FIG. 6 shows the relationship between the base width W _B and the energy level of electrons in the base region.

FIG. 7 shows the relationship between the electric field strength in a GaAs / InGaAs heterobarrier and the electron tunneling probability.

FIG. 8 is an energy band diagram of the HBT according to the second embodiment of the present invention.

FIG. 9 is an IV characteristic of the HBT according to the first embodiment of the present invention and the HBT of the related art.

FIG. 10 is a current gain of the HBT according to the second embodiment of the present invention, the reference example, and the HBT according to the related art.

FIG. 11 shows the relationship between the critical film thickness (h _c ) at which InGaAs is pseudo-epitaxially grown on a GaAs substrate and the In composition (x).

[Explanation of symbols]

21 semi-insulating GaAs substrate 22 n ⁺ type GaAs collector contact layer 23, 233 n type GaAs collector layer 24 p ⁺ type InGaAs base layer 25 n type Al _x Ga _1-x As grading layer 26 n type Al _0.3 Ga _0.7 As emitter Layer 27 n-type Al _x Ga _1-x As grading layer 28 n ⁺ type In _y Ga _1-y As grading layer 29 n ⁺ type In _0.5 Ga _0.5 As emitter contact layer 31 emitter electrode 32 base electrode 33 collector electrode 34 polyimide 35 High resistance region by ion implantation 3,7 Planar-doped region 234 Undoped GaAs layer 236,239 n-type GaAs emitter layer 237 n ⁺ -type GaAs emitter contact layer 8 p strained base layer 81,83 GaAs layer 82 In _0.2 Ga _0.8 As layer 91 nIn _0.5 Ga _0.5 P Emitter layer 266 nAlGaAs emitter layer

Claims (3)

[Claims] 1. A first semiconductor layer of a first conductivity type formed on a semiconductor substrate, and a second semiconductor layer of either a first conductivity type or a second conductivity type formed on the first semiconductor layer. A semiconductor layer,
A second conductive type third layer formed on the second semiconductor layer;
Semiconductor layer, a fourth semiconductor layer of the first conductivity type formed on the third semiconductor layer, and a fifth semiconductor of the first conductivity type formed on the fourth semiconductor layer. The third semiconductor layer has a forbidden band width smaller than the forbidden band widths of the second and fourth semiconductor layers, and the third semiconductor layer has a thickness smaller than that of the third semiconductor layer. A critical film thickness at which dislocations occur in either the second, third or fourth semiconductor layers due to the stress caused by the difference in lattice constant between the third semiconductor layer and the second and fourth semiconductor layers. A semiconductor device having the first and second semiconductor layers as a collector region, the third semiconductor layer as a base region, and the fourth and fifth semiconductor layers as an emitter region. The semiconductor layer has a thickness of 5 to 15 nm, and the electrons in the first excited state of electrons in the third semiconductor layer are A heterojunction bipolar transistor characterized in that the energy is in the range of 0.05 eV or less from the conduction band of the second semiconductor layer. 2. A first semiconductor layer of a first conductivity type formed on a semiconductor substrate, and a second semiconductor layer of either the first or second conductivity type formed on the first semiconductor layer. A semiconductor layer,
A second conductive type third layer formed on the second semiconductor layer;
Semiconductor layer, a fourth semiconductor layer of the first conductivity type formed on the third semiconductor layer, and a fifth semiconductor of the first conductivity type formed on the fourth semiconductor layer. The third semiconductor layer has a forbidden band width smaller than the forbidden band widths of the second and fourth semiconductor layers, and the third semiconductor layer has a thickness smaller than that of the third semiconductor layer. A critical film thickness at which dislocations occur in either the second, third or fourth semiconductor layers due to the stress caused by the difference in lattice constant between the third semiconductor layer and the second and fourth semiconductor layers. A semiconductor device in which the first and second semiconductor layers are collector regions, the third semiconductor layer is a base region, and the fourth and fifth semiconductor layers are emitter regions. First and second planar doped regions providing charge carriers of the first conductivity type to the fourth semiconductor layer And a potential barrier generated by a difference in forbidden band widths at the interfaces between the second and third semiconductor layers and the interfaces between the third and fourth semiconductor layers, so that the charge carriers can pass through the tunnel effect. A heterojunction bipolar transistor characterized by selecting an impurity density and a position of a doped region. 3. A first semiconductor layer of a first conductivity type formed on a semiconductor substrate, and a second semiconductor layer of either the first or second conductivity type formed on the first semiconductor layer. A semiconductor layer,
A second conductive type third layer formed on the second semiconductor layer;
Semiconductor layer, a fourth semiconductor layer of the first conductivity type formed on the third semiconductor layer, and a fifth semiconductor of the first conductivity type formed on the fourth semiconductor layer. The third semiconductor layer has an effective forbidden band width smaller than the forbidden band widths of the second and fourth semiconductor layers, and the first and second semiconductor layers are A semiconductor device having a collector region, the third semiconductor layer as a base region, and the fourth and fifth semiconductor layers as an emitter region, wherein the third semiconductor layer is two or more kinds of compound semiconductors having different lattice constants. A heterojunction bipolar transistor characterized in that it is composed of layers.