JP2006278544A - Active element and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To sharply enhance current density as compared with a conventional HBT by preventing the current from concentrating on one unit element even if the operating current becomes uneven among the unit elements thereby preventing puncture due to secondary breakdown. <P>SOLUTION: An HBT 101 and an FET are contiguously arranged through an isolation region, and a plurality of unit elements 100 where the base electrode of the HBT is connected with the source electrode of an MESFET 102 are connected to constitute an active element 200. In an active element connecting a plurality of unit elements in parallel, current does not concentrate on one unit element even if the operating current becomes uneven among the unit elements, and puncture due to secondary breakdown is prevented. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active device using a heterojunction bipolar transistor and a manufacturing method thereof, and more particularly to a temperature compensation type active device and a manufacturing method thereof.

Heterojunction bipolar transistor (Heterojunction Bipolar Transistor: hereinafter HBT) is a base concentration because of the high high current amplification factor _{h FE} emitter efficiency than normal homojunction bipolar transistor can be increased significantly, over the entire base Transistor operation can be made uniform. As a result, the current density is high and the on-resistance is low because of the high current density, low on-resistance, and high efficiency compared with GaAs MESFET (Metal Semiconductor Field Effect Transistor), GaAs JFET (Junction FET), and HEMT (High Electron Mobility Transistor). Are better.

  The structure of the HBT will be described with reference to FIG. An n-type GaAs subcollector layer 311 is formed on a semi-insulating GaAs substrate 310. An n-type AlGaAs collector layer 312, a p-type GaAs base layer 313, an n-type AlGaAs emitter layer 314, and an n-type GaAs are formed on the subcollector layer 311. The emitter contact layer 315 and the like are stacked in a mesa shape.

A collector electrode 316 is disposed on the surface of the subcollector layer 311 at a position sandwiching the collector layer 312. A base electrode 317 is disposed on the surface of the base layer 313 at a position sandwiching the emitter layer 314. An emitter electrode 318 is disposed on the emitter contact layer 315.
JP 2000-260782 A

  The emitter electrode 318, base electrode 317, and collector electrode 316 of the HBT are formed in a comb shape. Then, the structure shown in FIG. 14 is used as one unit element, and a plurality of unit elements are connected in parallel to form an active element such as a switching element.

  In the HBT, since the base-emitter current has a positive temperature coefficient, the collector current also has a positive temperature coefficient. Accordingly, when the current density is improved by increasing the base current, the current concentrates on one unit element among the plurality of HBT unit elements connected in parallel to cause a secondary breakdown, which easily leads to breakdown. .

  Conventionally, in order to avoid such a problem in reliability, there has been a problem that the current density cannot be sufficiently improved.

  The present invention has been made in view of such a problem. First, a compound semiconductor substrate in which a plurality of semiconductor layers forming at least one heterojunction are stacked, and the semiconductor layer provided on the substrate, the semiconductor layer being a collector layer, a base layer, A first transistor having an emitter layer, a collector electrode, a base electrode, and an emitter electrode; a second transistor provided on the substrate and having a gate electrode, a source electrode, and a drain electrode; and the first transistor and the second transistor; Are arranged adjacent to each other through an isolation region, and a unit element connecting the base electrode of the first transistor and the source electrode of the second transistor is connected, and a plurality of the unit elements are connected in parallel. A drain electrode of the second transistor of each unit element is connected to a power supply terminal, and the gate power of the second transistor is It said collector of said first transistor of each unit element by a voltage signal input to - solves by varying the current between the emitter.

  Second, stacking a plurality of semiconductor layers forming at least one heterojunction on a compound semiconductor substrate, forming a separation region in the semiconductor layer to separate the first region and the second region, Forming a first transistor having a collector electrode, a base electrode, and an emitter electrode in a first region; forming a second transistor having a gate electrode, a source electrode, and a drain electrode in the second region; and This is solved by providing a step of connecting the electrode and the source electrode.

According to the present embodiment, the HBT and the FET are arranged adjacent to each other via the isolation region, and an active element is configured by connecting a plurality of unit elements each having the source electrode of the MESFET connected to the base electrode of the HBT. In other words, the unit element has a MESFET connected to each base electrode of the comb-shaped HBT, and the HBT and the MESFET are arranged adjacent to each other via the isolation region. The active element connects the drain electrode of the MESFET to the power supply terminal _VDD , and changes the collector-emitter current of the HBT by a voltage signal input to the gate electrode of the MESFET. Since the distance between the HBT and the MESFET is close, heat generated by the operation of the HBT is transmitted to the MESFET. However, since the drain current of the MESFET has a negative temperature coefficient, the base current of the HBT of this embodiment also has a negative temperature coefficient. That is, in the present embodiment, the heat generation of the HBT decreases the collector current of the HBT.

Therefore, in an active element in which a plurality of unit elements are connected in parallel, even if the operating current is non-uniform for each unit element, the current does not concentrate on one unit element and the breakdown due to secondary breakdown does not occur. That is, the current density can be greatly improved as compared with the conventional HBT. Further amplification function, because the integration of the current amplification factor _{h FE} of the mutual conductance gm and HBT of MESFET than the conventional HBT, has a very large capacity. That gm of the active element is the integration of the current amplification factor _{h FE} of gm and HBT of MESFET.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  First, referring to FIG. 1, a circuit diagram of the active element of the present embodiment is shown. 1A is a circuit diagram of an active element, and FIG. 1B is a circuit diagram of a unit element constituting the active element.

  As shown in FIG. 1A, an active element 200 is formed by connecting a plurality of unit elements 100 (broken lines) in parallel. The unit element 100 includes a first transistor 101 and a second transistor 102. The first transistor is an HBT 101, and the second transistor is a compound semiconductor (for example, GaAs) MESFET (Metal Semiconductor Field Effect Transistor FET) 102. The MESFET may be either an enhancement type or a depletion type.

  The plurality of unit elements 100 are connected in parallel to form an active element 200. Specifically, one unit element 100 commonly connects the emitter and collector of the HBT 101 and the drain and gate of the FET 102 to the emitter, collector, drain and gate of the other unit element 100, respectively.

  In each unit element 100, the drain of the FET 102 is connected to the power supply terminal VDD. Then, the current between the collector and the emitter of the HBT 101 is changed by a voltage signal applied to the gate of the FET 102.

  Referring to FIG. 1B, the HBT 101 and the FET 102 of the unit element 100 are disposed adjacent to each other via an isolation region (described later), and the base of the HBT 101 and the source of the FET 102 are connected. The unit elements 100 are connected in parallel, but the base and source of one unit element 100 are not commonly connected to the base and source of other unit elements 100.

  FIG. 2 shows a plan view of the active device 200.

  A plurality of semiconductor layers are stacked on a compound semiconductor substrate to form a first transistor (HBT) 101 and a second transistor (FET) 102.

  As will be described later, in the HBT 101, each semiconductor layer is mesa-etched in a desired pattern to form each semiconductor layer serving as an emitter layer and a base layer in a mesa shape.

  The ohmic metal layer (AuGe / Ni / Au) provides the first emitter electrode 9 and the collector electrode 7 connected to the emitter layer and the subcollector layer, respectively, and the ohmic metal layer (Pt / Ti / Pt / Au) A base electrode 8 connected to the base layer is formed. The emitter electrode 9 and the collector electrode 7 are provided in a comb shape. The base electrode 8 is arranged like hatching around the emitter electrode 9 in the center. Two collector electrodes 7 sandwiching the base electrode 8 are arranged on the subcollector layer outside the base electrode 8.

  On the emitter electrode 9 and the collector electrode 7 of the first layer, the emitter electrode 15 and the collector electrode 13 of the second layer are provided by a wiring metal layer (Ti / Pt / Au) overlapping therewith. The second-layer emitter electrode 15 has a comb shape similar to that of the first layer. The second-layer collector electrode 13 is continuous with the collector wiring 130. The base electrode 8 has a single-layer structure with only an ohmic metal layer. On the emitter electrode 15 of the second layer, an emitter wiring 150 is provided by a gold plating layer.

  As will be described later, the FET 102 is provided on the same substrate and semiconductor layer as the HBT 101. The semiconductor layer is mesa-etched in a desired pattern, and each semiconductor layer to be a contact layer and a channel layer is formed in a mesa shape.

  By the ohmic metal layer (AuGe / Ni / Au), the first drain electrode 10 and the source electrode 11 that are in contact with the respective contact layers are provided. On the surface of the channel layer between the drain electrode 10 and the source electrode 11, a gate electrode 12 is provided by a gate metal layer (Pt / Mo). The gate electrode 12 extends between the island-shaped source electrode 11 and the drain electrode 10 in a direction orthogonal to the extending direction of each electrode of the comb-shaped HBT 101.

  The operation region of the FET 102 in which the drain electrode 10, the source electrode 11, and the gate electrode 12 are disposed is formed on the impurity region 23 in which the semiconductor layer is separated by the separation region 20. Since the isolation region 20 is an insulating region by ion implantation of B + or the like, in this embodiment, a region other than the isolation region 20, that is, a region surrounded by a two-dot chain line is an impurity region 23.

  On the drain electrode 10 of the first layer, the drain electrode 16 of the second layer is provided by a wiring metal layer (Ti / Pt / Au). On the drain electrode 16 of the second layer, a drain wiring 160 is provided by a gold plating layer.

  The gate electrode 12 is connected to a gate wiring 120 made of a wiring metal layer. The gate wiring 120 connects the gate electrodes 12 to each other and is connected to a terminal to which a voltage signal is input. An isolation region 20 is also arranged around the gate wiring 120.

  On the source electrode 11 of the first layer, a connection wiring 17 made of a wiring metal layer is provided. The connection wiring 17 connects the source electrode 11 of the FET 102 and the base electrode 8 of the HBT 101.

  The FET 102 and the HBT 101 are provided on the same substrate and semiconductor layer, but some of the semiconductor layers are formed in a mesa shape and separated by a space. The region that is not mesa-etched is separated by the separation region 20 by ion implantation. That is, the HBT 101 and the FET 102 are disposed adjacent to each other via the isolation region 20 provided on the same substrate and semiconductor layer, and the base electrode 8 of the HBT 101 and the source electrode 11 of the FET 102 are connected by the connection wiring 17. In the present embodiment, the base layer and the collector layer of the HBT 101 are each continuous with the corresponding semiconductor layer of the FET 102.

  In the present embodiment, as indicated by a broken line, the HBT 101 is a minimum unit including the emitter electrodes 9 and 15, the base electrode 8, and the collector electrodes 7 and 13, and a pair of the source electrode 11, the gate electrode 12, and the drain electrodes 10 and 16. One unit element 100 is configured by connecting the FET 102.

  The active element 200 is configured by connecting a plurality of HBTs 101 and FETs 102 of the unit element 100 in parallel. That is, collector electrodes 13 and 7 of each HBT 101 are connected to each other by collector wiring 130, and emitter electrodes 15 and 9 of each HBT 101 are connected to each other by emitter wiring 150. The collector electrodes 7 and 13 are shared by the adjacent unit elements 100. Further, the gate electrodes 120 of the FETs 102 connect the gate electrodes 12 of the FETs 102 to each other.

  Here, the base electrode 8 of the HBT 101 and the source electrode 11 of the FET 102 are connected by the connection wiring 17 in one unit element 100, but the base electrode of the HBT 101 is arranged in a layout in which a plurality of unit elements 100 are arranged in a comb shape. 8 and the source electrodes 11 of the FET 102 are not directly connected.

The drain electrode 16 of the FET 102 is wired by a drain wiring 160 made of a gold plating layer, and the drain wiring 160 is connected to the power supply terminal V _DD . The gate wiring 120 of the FET 102 is connected to a terminal to which a voltage signal is input.

  3A and 3B are diagrams illustrating the unit element 100. FIG. 3A is a cross-sectional view taken along the line aa in FIG. 2, and FIG. 3B is a cross-sectional view taken along the line bb in FIG. . FIG. 3C is a perspective view of the HBT 101 when the unit element is cut into the two regions in the cross section indicated by the line cc in FIG. 3A, and FIG. FIG. In FIG. 3, the electrodes of the second and higher layers other than the connection wiring 17 are omitted. In addition, the connection electrode 17 is omitted in FIGS.

  As shown in FIG. 3A, a plurality of semiconductor layers, that is, an n + GaAs layer 2, an n-GaAs layer 3, a p + GaAs layer 4, an nInGaP layer 5, and an n + GaAs layer 6 are stacked on a semi-insulating GaAs substrate 1. A part of the semiconductor layer is removed by etching to form a mesa shape. A separation region 20 reaching the substrate 1 is also provided. The isolation region 20 is an insulating region by ion implantation of B + or the like as described above.

  The unit element 100 is separated into two regions by a mesa-like semiconductor layer and an insulating region 20, and an HBT 101 is formed in one region and an FET 102 is formed in the other region.

3B and 3C, the subcollector layer 2 of the HBT 101 is formed on the substrate 1 by an epitaxial growth method, and is an n + GaAs layer doped with silicon (Si) at a relatively high impurity concentration of ³ to 6E18 cm ^−3. It is. Its film thickness is several thousand mm. The collector layer 3 is an n-GaAs layer formed on a partial region of the sub-collector layer 2 and doped to an impurity concentration of about 1 to 10E16 cm ⁻³ by silicon doping. Its film thickness is several thousand mm. The base layer 4a is a p + GaAs layer formed on the collector layer 3 and doped to an impurity concentration of about 1 to 50E18 cm ⁻³ by carbon (C) doping. The film thickness is several hundred to 2,000 mm. The emitter layer 5a is an n-type InGaP layer formed on a partial region of the base layer 4a and doped to an impurity concentration of about 1 to 10E17 cm ⁻³ by silicon doping. The film thickness is 1000 to 5000 mm. The emitter layer 5a is lattice-matched with the upper and lower GaAs layers. The emitter contact layer 6a is an n + GaAs layer formed on the emitter layer 5a and doped to an impurity concentration of about ³ to 6E18 cm ⁻³ by silicon doping, and has a thickness of several thousand Å.

  In the HBT 101 of this embodiment, the emitter layer 5a and the base layer 4a form an InGaP / GaAs heterojunction. The semiconductor layer to be the emitter layer 5a may be an AlGaAs layer instead of the InGaP layer, and in this case, lattice matching is performed with the upper and lower GaAs layers. An insulating region 20 for separation is provided in the vicinity of the surface S1 'below the base layer 4a. Further, as shown in FIG. 3B (omitted in FIG. 3C), a ledge (shelf) L having a shape projecting toward the base electrode 8 on both sides is provided at the lower portion of the emitter layer 5a. The ledge L is depleted and prevents the emitter-base recombination current from flowing on the surface of the base layer 4a below the ledge L.

  On the surface of the subcollector layer 2, a first collector electrode 7 made of an ohmic metal layer (AuGe / Ni / Au) is disposed at a position sandwiching the collector layer 3. A base electrode 8 made of an ohmic metal layer (Pt / Ti / Pt / Au) is arranged on the surface of the base layer 4a in a pattern surrounding the emitter layer 5a. A first emitter electrode 9 made of an ohmic metal layer (AuGe / Ni / Au) is disposed on the emitter contact layer 6a.

  FIG. 3D is a perspective view of the FET 102 when the unit element is cut along the cross section indicated by the line cc in FIG. The FET 102 uses the nInGaP layer 5 as a channel layer 5b. The uppermost n + GaAs layer 6 is used as contact layers 6bs and 6bd. The contact layers 6bd and 6bs become the drain region and the source region of the FET, respectively. The contact layers 6bd and 6bs are also formed in a mesa shape, and the gate electrode 12 is provided on the channel layer 5b exposed between them. On the contact layers 6bd and 6bs, the first drain electrode 10 and the source electrode 11 are formed by ohmic metal layers, respectively.

  Here, the channel layer 5 b of the FET 102 is the same InGaP layer as the emitter layer 5 a of the HBT 101. Thereby, the high breakdown voltage of the FET 102 and the stabilization of the surface of the channel layer 5b can be achieved.

  A p + GaAs layer 4b is disposed below the channel layer 5b. This layer can prevent carriers leaking from the channel to the substrate side.

  Since the layer below the p + GaAs layer 4b does not particularly affect the operation as the FET 102, it may be designed so that the characteristics of the HBT 101 are optimized.

  Referring again to FIG. 3A, the unit element 100 has a structure in which the surface S1 'of the HBT 101 shown in FIG. 3C and the surface S1 of the FET 102 shown in FIG. The contact surface is the surface of line cc in FIG. A connection wiring 17 is provided on the source electrode 11 of the FET 102 by a wiring metal layer (Ti / Pt / Au). The connection wiring 17 extends along the mesa of the FET 102 and over the insulating region 20 to the base electrode 8 of the HBT 101.

  In the present embodiment, the HBT 101 and the FET 102 are formed on the same semiconductor layer. The method for separating the HBT 101 and the FET 102 is as follows.

  The n + GaAs layer 6 and the nInGaP layer 5 have a mesa shape and are separated by a space. On the other hand, the layer below the p + GaAs layer 4 is separated by an isolation region (insulating region) 20. That is, the base layer 4a, the collector layer 3, and the subcollector layer 2 of the HBT 101 are electrically separated from the buffer layer 4b, the n-GaAs layer 3, and the n + GaAs layer 2 of the FET 102, but are continuous in structure. The unit element 100 has an HBT 101 and an FET 102 which are arranged adjacent to each other with an isolation region 20, and has a structure in which the base electrode 8 of the HBT 101 and the source electrode 11 of the FET 102 are connected by a connection wiring 17.

  In the present embodiment, the FET 102 and the HBT 101 are connected in close proximity to each unit element 100. The stacked structure of the semiconductor layers of the unit HBT 101 and the unit FET 102 is the same, and the base layer 4a, the collector layer 3, and the sub-collector layer 2 of the unit HBT 101 are each continuous with the corresponding semiconductor layer of the unit FET 102. Therefore, heat generated by the operation of the HBT 101 can be transmitted to the FET 102. Since the drain current of the FET 102 has a negative temperature coefficient, the base current of the HBT 101 also has a negative temperature coefficient. Therefore, the heat generation of the HBT 101 reduces the collector current of the HBT 101.

  In an active element (for example, an HBT) configured by connecting a plurality of unit elements in parallel, the operating current may be nonuniform between the unit elements. In that case, since the base current and the collector current have a positive temperature coefficient in the HBT, a positive feedback process starts in a unit element having the HBT, and as a result, a secondary breakdown is caused that the breakdown occurs due to current concentration. However, according to the present embodiment, since the collector current has a negative temperature coefficient, the current does not concentrate on one unit element 100, and the breakdown due to secondary breakdown does not occur. That is, in this embodiment, the temperature compensation type active element 200 is realized by connecting the FET adjacent to each unit element of the conventional active element (HBT), and compared with the conventional active element (HBT). It can be operated with greatly improved current density.

Further amplification function of the active element 200, since the integrated value of the current amplification factor _{h FE} and MESFET of gm of HBT, has a very large capacity. That gm of the active element 200 is the integrated value of the current amplification factor _{h FE} of gm and HBT of MESFET.

  Here, the mesa shape and the wiring direction will be described.

  When wet etching is employed for GaAs mesa etching, the crystal plane affects the mesa shape. As the relationship between the crystal direction and the mesa shape, the mesa shape when tracing the surface of the etching step in the direction parallel to the direction of [01 bar 1 bar] (hereinafter referred to as [01-1-) is a forward mesa shape (trapezoidal shape). Shape). Further, the mesa shape when the etching step surface is traced in the direction perpendicular to the [01-1-] direction is an inverted mesa shape (overhang shape).

  That is, when the metal layer moves up and down the mesa step, a step coverage problem occurs depending on the mesa shape or the extending direction of the metal layer. When the metal layer extends in the direction parallel to the [01-1-] direction and moves up and down the mesa step, the problem of step coverage does not occur because of the forward mesa shape. However, when the wiring extends in the direction perpendicular to the [01-1-] direction and goes up and down the mesa level difference, it has an inverted mesa shape, which causes a step coverage problem.

  In the present embodiment, a mesa is simultaneously formed in the region of the FET 102 by mesa etching for forming the emitter contact layer 6 a and the emitter layer 5 a of the HBT 101. That is, in FIG. 2, the emitter mesa EM is formed simultaneously.

  Further, a mesa is also formed in the region of the FET 102 at the same time by mesa etching for forming the base layer 4 a and the collector layer 3 of the HBT 101. That is, in FIG. 2, the base mesa BM is formed simultaneously.

  Therefore, the connection wiring 17 connecting the source electrode 11 of the FET 102 and the base electrode 8 of the HBT 101 moves up and down the emitter mesa EM, and the gate wiring 120 moves up and down the base mesa BM.

  Therefore, in the present embodiment, the connection wiring 17 and the gate wiring 120 are aligned in the direction in which the mesa is moved up and down, and both extend in a direction parallel to the [01-1-] direction (the direction of the arrow in the drawing).

  Next, with reference to FIG. 4 and FIG. 5, an example of a circuit using the active element 200 of this embodiment is shown.

  FIG. 4 shows an example in which a switch circuit device is configured using the active element 200. The switch circuit device is an SPDT (Single Pole Double Throw) switch MMIC. 4A is a circuit diagram of the SPDT switch MMIC, and FIG. 4B is a cross-sectional view of the HBT 101 constituting the unit element 100.

  As shown in FIG. 4A, the unit elements 100 of this embodiment are connected in parallel to form the first switching element SW1 and the second switching element SW2. In the first and second switching elements SW1 and SW2, the collector of the HBT 101 is connected to the common input terminal IN. The emitters are connected to the first output terminal OUT1 and the second output terminal OUT2, respectively.

In the first and second switching elements SW1 and SW2, the source of the FET 102 is connected to the base of each HBT 101, and the drain is connected to the power supply terminal V _DD . Further, each gate is connected to the first control terminal Ctl1 and the second control terminal Ctl2.

  In the unit element 100, the collector, emitter, drain, and gate are commonly connected in parallel with the collector, emitter, drain, and gate of the other unit element 100, respectively, but the base is commonly connected to the bases of the other unit elements 100. In other words, the source is not commonly connected to the sources of the other unit elements 100.

This switch circuit device applies complementary signals to the first and second control terminals Ctl1 and Ctl2. The collector of the HBT 101 - emitter voltage V _CE is biased to 0V, and by applying a predetermined base current collector - to conduct between emitter. In addition, the base current is set to 0 to cut off the collector-emitter. Thereby, a signal path is formed either between the common input terminal IN and the first output terminal OUT1 or between the common input terminal IN and the second output terminal OUT2.

A high frequency signal separation element 30 is connected to the emitter and collector of the HBT 101. The separation element 30 is a resistor having a resistance value of 5 KΩ to 10 KΩ, for example, and prevents the high frequency signal from leaking with respect to the bias potential (GND potential). Further, a high frequency signal separating element 30 is also connected between the power supply terminal V _DD to which the drain bias is applied and the FET 102.

  Here, when configuring the switch circuit device as described above, the HBT 101 of the unit element 100 is preferably a symmetric HBT that can operate symmetrically in both the forward and reverse directions.

  FIG. 4B is a cross-sectional view illustrating an example of the symmetric HBT 101. This cross-sectional view corresponds to the cross section taken along the line bb in FIG. 2, and the second and higher electrodes are omitted.

An n + GaAs subcollector layer 2 is formed on a semi-insulating GaAs substrate 1. An n-type InGaP collector layer 3, a p-type GaAs base layer 4 a, an n-type InGaP emitter layer 5 a, and n + GaAs are formed on the subcollector layer 2. The emitter contact layer 6a is stacked in a mesa shape. The collector layer 3 is an n-type InGaP layer formed on a partial region of the sub-collector layer 2 and doped to an impurity concentration of about 1 to 5E17 cm ⁻³ by silicon doping. The film thickness is 1000 to 5000 mm. Except this, it is the same as FIG. The collector layer 3 and the emitter layer 5a may be AlGaAs layers instead of the InGaP layers.

The symmetric HBT 101 forms an InGaP / GaAs heterojunction between the emitter layer 5a and the base layer 4a, and also forms an InGaP / GaAs heterojunction between the collector layer 3 and the base layer 4a. . The transistor characteristics are different between a forward transistor operation that operates using the emitter layer 5a as an emitter (forward transistor operation) and a reverse transistor operation that operates using the emitter layer 5a as a collector (reverse transistor operation). Each structural parameter is controlled so that the characteristics are almost the same. Specifically, the on-resistance Ron (= ΔV _CE / ΔI _C ) during forward transistor operation and the on-resistance Ron ′ (= ΔV _CE ′ / ΔI _C ′) during reverse transistor operation are configured to be substantially equal. Then, the collector-emitter voltage is operated with a bias of 0 V, and the collector-emitter current is operated with a bias of about 0 A.

  Since the HEMT generally used in the switch MMIC is a unipolar device, the HBT is a bipolar device, so that the current density can be greatly increased and the on-resistance Ron can be extremely reduced. Further, by using the symmetric HBT 101 for the switch MMIC, the collector-emitter consumption current can be reduced to zero. This makes it possible to perform an energy saving operation in the same way as the HEMT sets the drain-source current consumption to zero. The reason is that the collector-emitter voltage can be biased to 0V in the symmetric HBT 101 in the same manner as the drain-source voltage is biased to 0V in the HEMT.

  The HBT can potentially obtain a very high current density compared to the HEMT, and can obtain a very low on-resistance Ron. However, the HBT has a problem that current is concentrated on one unit element due to a positive feedback action due to temperature and is destroyed by secondary breakdown. For this reason, the current density cannot actually be increased sufficiently. In order to solve this problem, generally, a countermeasure is always taken to insert an emitter ballast resistor or a base ballast resistor into each unit element of the HBT. However, when an emitter ballast resistor or a base ballast resistor is inserted, a new problem arises that the high-frequency characteristics are degraded accordingly.

  According to the present embodiment, it is possible to provide a temperature compensated active element that fundamentally solves these problems. That is, the unit element 100 is configured in which the FET 102 is disposed adjacent to the HBT 101 and the source of the FET 102 is connected to the base of the HBT 101. In a layout in which a plurality of unit elements 100 are arranged in a comb shape, the sources of the FETs 102 and the bases of the HBT 101 are not connected, and the other drains, gates, emitters, and collectors are connected in parallel. Thus, the active element 200 is configured. As a result, a temperature compensated system is configured without taking a method of deteriorating high-frequency characteristics such as emitter ballast resistance and base ballast resistance as a countermeasure against secondary breakdown.

In some cases, the base-emitter voltage V _BE bias is slightly applied to one unit element with respect to another unit element due to some design nonuniformity in the HBT. The characteristics of the base-emitter voltage V _{BE -base} current of the HBT have a positive coefficient with respect to the temperature, so that a large amount of base current and collector current flow in the unit element, and the base temperature increases further as the temperature rises. The normal secondary breakdown process is to pass current and collector current. However, in the unit element 100 of the present embodiment, the secondary breakdown process is not actually started. The FET 102 supplies the base current of the HBT 101 of the unit element 100. Unlike the HBT 101, the FET 102 has a negative temperature coefficient with respect to the temperature. Further, since the HBT 101 and the FET 102 are close to each other, the heat generated by the HBT 101 is transmitted to the adjacent FET 102 and the source current of the FET 102 is reduced. Since the source and base are connected, the source current of the FET 102 becomes the base current of the HBT 101, and the source current of the FET 102 decreases due to the heat generation of the HBT 101, and the base current of the HBT 101 decreases. As a result, the collector current of the HBT 101 decreases, and conversely, the HBT 101 is cooled. That is, as a result, occurrence of secondary breakdown can be prevented.

  By adopting such a mechanism, it is possible to prevent the occurrence of secondary breakdown without adding any factors that degrade the high-frequency characteristics such as emitter ballast resistance and base ballast resistance. Can be significantly increased. As a result, the on-resistance Ron of the first and second switching elements SW1 and SW2 can be made very small, and the insertion loss of the switch MMIC can be made very small.

  FIG. 5 shows a power amplifier circuit device using the temperature compensated active element 200 of this embodiment. FIG. 5A is a circuit diagram, and FIG. 5B is a circuit block diagram.

  The main application of HBT in the current market is a power amplifier (high power amplifier) of a mobile phone. In the power amplifier of a mobile phone, in particular, since the third generation, how many communication lines are secured in a limited frequency band is the technically biggest key, and a high-density communication method such as CDMA. Has been adopted. As communication systems become more dense, power amplifier devices with higher linearity are required. HEMTs are also used in power amplifiers for mobile phones, but the usage ratio of HBTs with higher current density and higher linearity than HEMTs has increased since the third generation. Since the HEMT is a unipolar device and the HBT is a bipolar device, the current density can be significantly increased.

  According to the present embodiment, it is possible to provide the amplifier 200 that avoids secondary breakdown without inserting an emitter ballast resistor or a base ballast resistor into each unit element of the HBT.

As shown in FIG. 5A, an amplifier 200 is configured by connecting unit elements 100 in parallel. In the amplifier 200, an input signal is input from the gate of the FET 102 constituting each unit element 100, and an output signal is output from the collector of the HBT 101. The drain of the FET 102 is connected to the power supply terminal V _DD via a separation element (inductor) 30 that prevents leakage of high-frequency signals. The power supply terminal V _DD supplies current to the FET 102. The emitter is connected to GND. The FET 102 may be any of MESFET, J-FET, and HEMT. For example, a J-FET can be formed in the same manner as a MESFET by simply changing the gate formation process. In the case of HEMT, an HEMT epitaxial layer is laminated and formed. The unit element 100 of this embodiment has a configuration in which an FET 102 is connected to an HBT 101. That is, the FET as the amplifier 102 is connected to the front stage of the HBT 101 as the amplifier.

  That is, as shown in FIG. 5B, when the amplifier 200 is configured by connecting the unit elements 100 in parallel, the two-stage amplifier in which the HBT as the second-stage amplifier is connected to the subsequent stage of the FET as the first-stage amplifier. Function as.

That is, the mutual conductance gm of the FET is applied to the current amplification factor _{h FE} of the HBT, amplification performance of one amplifier 200 is the integrated value of the mutual conductance gm and the current amplification factor _{h FE.} That gm of one amplifier 200 is the integrated value of _{h FE} of gm and HBT of the FET. Compared with the amplification performance of an amplifier composed only of the HBT being only the current amplification factor _hFE , the gain of the amplifier is greatly improved.

The HBT 101 employed in the amplifier 200 will be described with reference to cross-sectional views of FIGS. The structure of the epitaxial layer of HBT 101 is basically the structure shown in FIG. 3B, but may be the structure shown below. The cross-sectional view corresponds to the cross section taken along the line bb of FIG. 2, but is an outline for explaining the epitaxial layer, and the second and higher electrodes are omitted.

FIG. 6A shows the case where the emitter contact layer is a non-alloy ohmic layer.
In order to reduce the contact resistance of the emitter contact layer 6a, a non-alloy ohmic layer 31 may be provided on the emitter contact layer 6a. The non-alloy ohmic layer 31 is an n + InGaAs layer. In this case, the emitter contact layer 6a is an nGaAs layer, but the other semiconductor layers are the same as in FIG.

  FIG. 6B shows a case where a grading layer is inserted.

In some cases, an Al _0.3 Ga _0.7 As layer is employed as the emitter layer 5a, and a heterojunction is formed between the base layer 4a and the GaAs layer. This heterojunction has a band spike at the bottom of the conduction band, and this band spike is one of the causes of the generation of the offset voltage. In order to eliminate this band spike, a grading layer 32 for gradually transitioning from GaAs to AlGaAs may be disposed to reduce the offset voltage.

Grading layer 32 is, for example, a n-type _{Al X Ga 1-X As (} X = 0 → 0.3) layer, thereby the base - gradually from GaAs in the emitter to _Al 0.3 _{Ga 0.7} As Change. The structure of other semiconductor layers is the same as that in FIG.

  FIG. 7A shows a case where a ballast resistance layer is inserted. Depending on the design of the FET 102 and the HBT 101 constituting the unit element 100, secondary breakdown may not be sufficiently prevented. Even when a very large current is passed through the HBT 101, it is difficult to completely avoid the occurrence of secondary breakdown. In such a case, it is advisable to take measures against secondary breakdown by adding a ballast resistance layer to the epi structure of the HBT.

  That is, the n-GaAs layer 33 is disposed as a ballast resistance layer on the emitter layer 5a side. Since the n-GaAs layer 33 having a predetermined resistance value becomes a ballast resistance layer, it is possible to prevent the occurrence of secondary breakdown due to current concentration in one unit element.

  The ballast resistor layer 33 may be formed of a non-doped GaAs layer, or may be an n-InGaP layer or a non-doped InGaP layer when the emitter layer 5a is an InGaP layer. When the emitter layer 5a is an AlGaAs layer, the ballast resistor layer 33 may be formed of an n-AlGaAs layer or a non-doped AlGaAs layer. Other semiconductor layers are similar to those in FIG.

  FIG. 7B shows a case where the heterojunction is shifted from the pn junction between the emitter and the base, and the emitter layer 5a is an n-type AlGaAs layer.

  In a general HBT structure, the emitter-base pn junction between the n-type AlGaAs layer of the emitter layer 5a and the p-type GaAs layer of the base layer 4a coincides with the heterojunction. In this junction, a band spike exists at the bottom of the conduction band, and this band spike is one of the causes of the generation of the offset voltage. In order to prevent generation of an offset voltage due to a band spike, an n-type GaAs layer 34 is added between the p-type GaAs layer of the base layer 4a and the n-type AlGaAs layer of the emitter layer 5a, so that the heterojunction position is between the base and the emitter. It may be shifted from the pn junction position. In this case, since the heterojunction position does not coincide with the pn junction between the emitter and the base, the offset voltage can be made very small.

  As the principle of HBT, in order not to inject holes in the base to the emitter side, an AlGaAs layer having a band gap larger than that of the GaAs layer as the base layer 4a is arranged as the emitter layer 5a.

  In the case of this structure, the junction between the added nGaAs layer 34 and the nAlGaAs layer 5a which is the emitter layer located thereon is a heterojunction.

  FIG. 8 shows a structure in which the ledge L can be formed by selective etching. In each of FIGS. 8A to 8C, the emitter layer 5a that forms a heterojunction with the base layer 4a has a thickness of the ledge L, and a semiconductor layer having a large etching selectivity is stacked thereon.

  For example, in FIG. 8A, an nGaAs layer 35 is added on the emitter layer (nInGaP layer) 5a, and a ledge L is formed by selective etching of GaAs / InGaP.

  In FIG. 8B, an nAlGaAs layer 36 is added on the emitter layer (nInGaP layer) 5a, and a ledge L is formed by selective etching of AlGaAs / InGaP.

  In FIG. 8C, an nInGaP layer 37 is added on the emitter layer (nAlGaAs layer) 5a, and a ledge L is formed by selective etching of InGaP / AlGaAs.

  Next, with reference to FIG. 9 to FIG. 13, a method for manufacturing the active element of this embodiment will be described.

  In the active element of this embodiment, a step of laminating a plurality of semiconductor layers forming at least one heterojunction on a compound semiconductor substrate, and forming an isolation region in the semiconductor layer to separate the first region and the second region Forming a first transistor having a collector electrode, a base electrode, and an emitter electrode in the first region; and forming a second transistor having a gate electrode, a source electrode, and a drain electrode in the second region. And a step of connecting the base electrode and the source electrode.

  In addition, the left of each figure shows the sectional view along the line aa in FIG. 2, and the right side shows the sectional view along the line bb.

  First step (FIG. 9): A step of laminating a plurality of semiconductor layers forming at least one heterojunction on a compound semiconductor substrate.

An n + GaAs layer 2 doped with silicon (Si) at a relatively high impurity concentration of ³ to 6E18 cm ⁻³ is formed on the GaAs substrate 1. The film thickness is several thousand mm. An n-GaAs layer 3 doped with an impurity concentration of about 1 to 10E16 cm ⁻³ by silicon doping is formed on the upper layer to a thickness of several thousand Å. Further, a p + GaAs layer 4 doped to an impurity concentration of about 1 to 50E18 cm ⁻³ by carbon (C) doping is formed on the upper layer to have a film thickness of several hundred to 2000 μm, and an impurity concentration of about 1 to 10E17 cm ⁻³ by silicon doping. An n-type InGaP layer 5 doped with is formed to a thickness of 1000 to 5000 mm. The nInGaP layer 5 is lattice-matched with the upper and lower GaAs layers, and the nInGaP layer 5 and the lower p + GaAs layer 4 form a heterojunction. On top of the nInGaP layer 5, an n + GaAs layer 6 doped to an impurity concentration of about ³ to 6E18 cm ⁻³ by silicon doping is formed to a thickness of several thousand Å.

  Second step (FIG. 10): A step of forming a separation region in the semiconductor layer to separate the first region and the second region.

  A through ion implantation nitride film 51 is deposited on the entire surface of the substrate. A resist (not shown) is provided, and a mask having an alignment mark pattern is formed by a photolithography process. The nitride film 51 and part of the n + GaAs layer 6 are etched using this mask to form alignment marks (not shown).

  After removing the resist, a new resist (not shown) is provided, and a mask for forming the isolation region 20 is formed by a photolithography process. Boron (B +) is ion-implanted from above the nitride film 51 and the resist is removed, followed by annealing at 500 ° C. for about 30 seconds. As a result, an insulating region 20 that reaches the substrate 1 and serves as an isolation region is formed.

  The insulating region 20 is not electrically completely insulated, but is a region where carrier traps are provided in the epitaxial layer by ion implantation of impurities (B +). Each semiconductor layer is separated into a first region 21 and a second region 22 by an insulating region 20. The first region 21 is a region where an HBT is formed in a later step, and the second region 22 is a region where a MESFET is formed in a later step. In this embodiment, the region other than the insulating region 20 becomes the impurity region 23. Although not shown, impurity regions necessary as active elements such as resistors of the switch circuit device are also separated by the insulating region 20.

  In the plan view of FIG. 2, the region surrounded by the alternate long and two short dashes line, that is, the lower region where each electrode of the HBT is arranged, the FET operation region, and the lower portion of the gate wiring 120 is the impurity region 23. An insulating region 20 is formed.

  Due to the insulating region 20, each semiconductor layer in the first region 21 becomes an emitter contact layer 6 a, an emitter layer 5 a, a base layer 4 a, a collector layer 3, and a subcollector layer 2 from the upper layer. On the other hand, each semiconductor layer in the second region 22 becomes the contact layer 6b, the channel layer 5b, and the p-type buffer layer 4b from the upper layer. The p-type buffer layer 4b is a p + GaAs layer and can be used as a layer for preventing leakage of carriers flowing through the channel to the substrate side. In the FET, the n-GaAs layer 3 and the n + GaAs layer 2 are layers that do not particularly affect the operation. That is, what is necessary is just to design so that the characteristic of HBT formed in the 1st area | region 21 may become the optimal.

  Third step (FIG. 11): A step of forming a first transistor having a collector electrode, a base electrode, and an emitter electrode in the first region.

  The nitride film 51 is removed, and a photoetching process for forming an emitter layer of HBT is performed. First, the n + GaAs layer 6 is mesa-etched, and then the nInGaP layer 5 is partially mesa-etched. Thereafter, the remaining nInGaP layer 5 is mesa-etched by a new photoetching process to remove the resist. As a result, the emitter contact layer 6a and the emitter layer 5a are formed in a mesa shape (emitter mesa EM), and a ledge (shelf) L is formed below the emitter layer 5a.

  Next, a photoetching process for forming the base layer is performed. The p + GaAs layer 4 and the n−GaAs layer 3 are mesa-etched to remove the resist.

  Thereby, the base layer 4a and the collector layer 3 are formed in a mesa shape (base mesa BM). The emitter contact layer 6a is exposed at the uppermost layer, and the base layer 4a is exposed outside the emitter layer 5a. The subcollector layer 2 is exposed outside the base layer 4a.

  Further, by mesa etching of the emitter layer 5a, the FET contact layer 6b and the channel contact layer 5b separated from the emitter contact layer 6a and the emitter layer 5a by a space are formed as shown in the left figure. The layers below the p + GaAs layer 4 are separated by the insulating region 20 (FIG. 11A).

  Next, a first layer electrode is formed. First, a photolithography process for forming an emitter electrode, a collector electrode of the HBT, and a source electrode and a drain electrode of the FET is performed. After vapor deposition of the ohmic metal layer (AuGe / Ni / Au), lift-off and alloy are performed to form the emitter electrode 9 of the HBT, the collector electrode 7, the drain electrode 10 and the source electrode 11 of the FET. The first-layer emitter electrode 9 and collector electrode 7 are formed in a comb shape, and the drain electrode 10 and the source electrode 11 are formed in an island shape (see FIG. 2).

  Thereafter, a photolithography process for forming the base electrode is performed. After depositing the ohmic metal layer (Pt / Ti / Pt / Au), lift-off and alloying are performed to form the base electrode 8 of the HBT. The base electrode 8 surrounds the emitter electrode 9 and is formed in a pattern indicated by hatching in FIG.

  Thus, the basic structure of the HBT 101 is formed in the first region 21 (FIG. 11B).

  Fourth step (FIG. 12): A step of forming a second transistor having a gate electrode, a source electrode, and a drain electrode in the second region.

  The nitride film 51 is again deposited on the entire surface. The nitride film 51 is etched by performing a photolithography process. Thus, a mask for recess etching of the gate of the FET is formed in the second region 22.

  Next, recess etching of the gate is performed. That is, the contact layer 6b (n + GaAs layer) exposed from the recess etching mask is removed by etching. At this time, the contact layer 6b is side-etched larger than the opening width of the mask to ensure a predetermined breakdown voltage.

  The contact layer 6b is separated into a contact layer 6bs serving as a source region of the FET and a contact layer 6bd serving as a drain region. Further, the protruding portion of the mask is removed by plasma etching, and a gate metal layer (Pt / Mo) is deposited. Thereafter, lift-off and heat treatment are performed, and a part of Pt is embedded in the surface of the channel layer 5b to form the gate electrode 12.

  As a result, the basic structure of the FET 102 is formed in the second region 22.

  Further, a nitride film 51 serving as a passivation film is deposited on the entire surface. A photolithography process is performed to form contact holes with the second-layer electrode and wiring. The nitride film 51 is etched to form a contact hole CH, and the resist is removed.

  Fifth step (FIG. 13): A step of connecting the base electrode and the source electrode.

  A new photolithography process is performed to deposit a second-layer electrode and a wiring metal layer (Ti / Pt / Au) to be a wiring on the entire surface. The wiring metal layer is lifted off, and the second-layer electrode and wiring are formed. That is, in the first region 21, the second-layer collector electrode 13 and emitter electrode 15 that are in contact with the first-layer collector electrode 7 and emitter electrode 9, respectively, are formed. In the second region 22, a second drain electrode 16 is formed in contact with the first drain electrode 10.

  Then, a connection wiring 17 that connects the source electrode 11 of the FET 102 and the base electrode 8 of the HBT 101 is formed. The connection wiring 17 passes on the insulating region 20 along the mesa of the FET 102 from above the source electrode 11 and extends to the base electrode 8. Thus, the unit element 100 in which the HBT 101 and the FET 102 are adjacent to each other through the isolation region (insulating region) 20 and the base electrode 8 of the HBT 101 and the source electrode 10 of the FET 102 are connected is formed (FIG. 13A).

  The connection wiring 17 is in contact with the base electrode 8 protruding in the direction of the insulating region 20 from the emitter electrodes 9 and 15 and the collector electrodes 7 and 13 in the planar pattern. Further, the collector electrode 13 in the second layer is continuous with the collector wiring 130 for wiring the collector electrodes 7 of the plurality of unit elements 100. (See FIG. 2).

  Thereafter, polyimide 60 is applied to the entire surface. A photolithography process is performed to etch the polyimide 60 on the second-layer emitter electrode 15 and the second-layer drain electrode 16. Thereafter, the resist is removed and the polyimide 60 is cured.

  Next, a base metal layer (Ti / Pt / Au) 70 is deposited on the entire surface. A photolithography process is performed to expose the pattern of the emitter wiring and the drain wiring and to perform gold plating. After removing the resist, unnecessary base metal layer 70 is removed by ion milling. Thereby, an emitter wiring 150 for wiring the emitter electrodes 15 and 9 of each HBT 101 and a drain wiring 160 for wiring the drain electrodes 16 and 10 of each FET 102 are formed.

The separation region 20 forming step of the second step may be performed at any stage as long as it is before the formation of the first ohmic metal layer.

It is a circuit diagram for demonstrating this invention. It is a top view for demonstrating this invention. It is (A) sectional drawing for demonstrating this invention, (B) sectional drawing, (C) perspective view, (D) perspective view. BRIEF DESCRIPTION OF THE DRAWINGS (A) Circuit diagram for demonstrating this invention, (B) It is sectional drawing. 1A is a circuit diagram and FIG. 1B is a circuit block diagram for explaining the present invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 Subcollector layer 3 Collector layer 4a Base layer 5a Emitter layer 6a Emitter contact layer 7, 13 Collector electrode 8 Base electrode 9, 15 Emitter electrode 4b P-type buffer layer 5b Channel layer 6bs, 6bd Contact layer 10, 16 Drain Electrode 11 Source electrode 12 Gate electrode 17 Connection wiring 20 Separating region 21 First region 22 Second region 23 Impurity region 30 Separating element 31 Non-alloy ohmic layer 32 Grading layer 33 Ballast resistor layer 34 n-type GaAs layer 51 Nitride film 60 Polyimide 70 Base metal layer 100 Unit element 101 HBT
102 MESFET
120 Gate wiring 130 Collector wiring 150 Emitter wiring 160 Drain wiring 200 Active element L Ledge CH Contact hole SW1 First switching element SW2 Second switching element IN Common input terminal OUT1 First output terminal OUT2 Second output terminal Ctl1 First control terminal Ctl2 Second control terminal

Claims (11)

A compound semiconductor substrate in which a plurality of semiconductor layers forming at least one heterojunction are stacked;
A first transistor provided on the substrate and having the semiconductor layer as a collector layer, a base layer, and an emitter layer, and having a collector electrode, a base electrode, and an emitter electrode;
A second transistor provided on the substrate and having a gate electrode, a source electrode, and a drain electrode;
A unit element in which the first transistor and the second transistor are arranged adjacent to each other via an isolation region, and the base electrode of the first transistor and the source electrode of the second transistor are connected;
A plurality of the unit elements are connected in parallel, a drain electrode of the second transistor of each unit element is connected to a power supply terminal, and a voltage signal input to the gate electrode of the second transistor is used for each unit element. An active device characterized in that a current between a collector and an emitter of the first transistor is changed.   One unit element includes the drain electrode, the gate electrode, and the emitter electrode and the collector electrode of the second transistor in parallel with the corresponding electrodes of the other unit elements, respectively. The active device according to claim 1, wherein the active devices are connected in common.   The active element according to claim 1, wherein the channel layer of the second transistor is provided in the same semiconductor layer as the emitter layer.   The active element according to claim 1, wherein the semiconductor layer serving as the base layer and the collector layer is continuous with the second transistor.   The said each electrode of the said 1st transistor is provided in the comb shape, and it extends in a 1st direction, The said gate electrode of the said 2nd transistor is extended in a 2nd direction, The 1st aspect is characterized by the above-mentioned. The active device as described.   The active device according to claim 1, wherein the base layer is a p + GaAs layer.   The active device according to claim 1, wherein the emitter layer is an InGaP layer or an AlGaAs layer.   The active device according to claim 1, wherein the collector current of the first transistor has a negative temperature coefficient. Laminating a plurality of semiconductor layers forming at least one heterojunction on a compound semiconductor substrate;
Forming a separation region in the semiconductor layer to separate the first region and the second region;
Forming a first transistor having a collector electrode, a base electrode, and an emitter electrode in the first region;
Forming a second transistor having a gate electrode, a source electrode, and a drain electrode in the second region;
And a step of connecting the base electrode and the source electrode. Laminating a plurality of semiconductor layers forming at least one heterojunction on a compound semiconductor substrate;
Forming a separation region in the semiconductor layer to separate the first region and the second region;
Forming, in the first region, a first transistor having a collector electrode, a base layer, and an emitter electrode, and a collector electrode, a base electrode, and an emitter electrode connected to each of the semiconductor layers;
Forming, in the second region, a second transistor having a gate electrode, a source electrode, and a drain electrode using the semiconductor layer that is the same layer as the emitter layer as a channel layer;
And a step of connecting the base electrode and the source electrode. 11. The method of manufacturing an active element according to claim 9, wherein the isolation region is formed by ion-implanting impurities to a depth reaching the substrate to electrically insulate the isolation region. .