JP2006278541A - Compound semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid complication of fabrication process by forming all epitaxial layers through a single epitaxial growth step thereby eliminating the need for a large number of times of ion injection and anneal steps or a step for processing a semiconductor layer, e.g. for forming a base pedestal. <P>SOLUTION: In the compound semiconductor device 100, the emitter layer 5a of a HBT and the channel layer 5b of an FET employ an identical n-type InGaP layer. The base layer of the HBT, i.e. a p+-type GaAs layer is utilized as the p-type buffer layer 4b of the FET. Consequently, pinch-off properties of the FET are improved and mutual inductance gm can be increased. Since epitaxial growth is required only once and ion implantation and anneal steps are not required, fabrication process can be simplified and wafer cost can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a compound semiconductor device in which a heterojunction bipolar transistor and a field effect transistor are integrated, and a method for manufacturing the compound semiconductor device.

Heterojunction bipolar transistor (Heterojunction Bipolar Transistor: hereinafter HBT) is a base concentration because of the high high current amplification factor _{h FE} emitter efficiency than normal homojunction bipolar transistor can be increased significantly, over the entire base Transistor operation can be made uniform. A semiconductor device in which HBT and other devices are integrated on the same substrate is also known.

  A semiconductor device in which an HBT and a MESFET (Metal Semiconductor Field Effect Transistor) are integrated will be described with reference to FIG.

  An n-type GaAs subcollector layer 314 is formed on a semi-insulating GaAs substrate 312, and an n-type GaAs collector layer 316, a p-type GaAs base layer 318, an n-type AlGaAs emitter layer 320, and an n-type GaAs are formed on the subcollector layer 314. An emitter cap layer 322 and an emitter contact layer 324 are stacked in a mesa shape, and an HBT 311 and an FET 315 are integrated (see, for example, Patent Document 1).

Also, multiple semiconductor layers are stacked on one substrate, and HBT and E / D-HFET (Heterojunction Field Effect Transistor), MESFET, or JFET (Junction FET) are integrated in the region separated by the impurity implantation region. Such a structure is also known (see, for example, Patent Document 2).
US Pat. No. 5,250,826 JP-A-6-177332

  An HBT is a transistor formed by stacking semiconductor layers to be a collector layer, a base layer, and an emitter layer so as to have at least one heterojunction. In other words, when the HBT and other devices are integrated on the same substrate, the other devices are not limited by the substrate structure of the HBT. In view of this, in the formation region of other devices, an unnecessary semiconductor layer is removed by etching or impurities are ion-implanted into the semiconductor layer so that the other device has desired characteristics.

  For example, in Patent Document 1, the FET 315 has a source contact S and a drain contact D provided on the emitter contact layer 324, and the n-type GaAs layer 322 constituting the emitter cap layer of the HBT 311 serves as a channel layer of the FET 315. ing. Then, an n-type AlGaAs layer 320 serving as an emitter layer of the HBT 311 is disposed below the channel layer 322, and a p-type GaAs layer 318 constituting a base layer of the HBT 311 is disposed below the n-type AlGaAs layer 320 as a p-type buffer layer of the FET 315. Yes.

  An n-type AlGaAs layer 320 is disposed between the n-type GaAs layer 322 and the p-type buffer layer 318 of the channel layer. However, since the n-type AlGaAs layer 320 is an unnecessary layer for the FET operation, this provides a carrier leak path, resulting in poor channel pinch-off. That is, the pinch-off voltage becomes excessively large. When the n-type AlGaAs layer 320 is also used as a channel layer, the channel layer is composed of two kinds of compounds of GaAs and AlGaAs having different band gaps, and the gate voltage-drain current of the FET due to the discontinuity. The linearity of the characteristics is lost, and the distortion characteristics of the circuit are deteriorated.

  On the other hand, in Patent Document 2, the integration of the HBT and other devices is realized by impurity implantation without using the mesa structure.

  For example, all of the HFET, MESFET, and J-FET integrated with the HBT are formed by ion implantation into the collector layer (GaAs) of the HBT. The HFET is provided with a p-type buffer layer for preventing carriers leaking from the channel to the substrate side, and this is also formed by ion implantation of impurities into the collector layer. Further, on the HBT side, the base layer is processed (base pedestal formation), and multiple times of ion implantation and annealing are performed. Furthermore, after that, a second epitaxial growth process for forming an emitter layer and an emitter contact layer is required. However, this complicates and lengthens the manufacturing process, and there is a problem that costs increase.

  The present invention has been made in view of such a problem. First, a bipolar transistor and a field effect transistor are integrated in a first region and a second region, respectively, of a compound semiconductor substrate in which a plurality of semiconductor layers forming at least one heterojunction are stacked. In the compound semiconductor device to be manufactured, one one-conductivity-type semiconductor layer in the first region is used as an emitter layer of the bipolar transistor, and the one-conductivity-type semiconductor layer in the second region is used as a channel layer of the field effect transistor. To solve this problem.

  Second, a method for manufacturing a compound semiconductor device in which a bipolar transistor and a field effect transistor are integrated in a first region and a second region of a compound semiconductor substrate, respectively, wherein at least one heterogeneous layer is formed on the substrate by one epitaxial growth. A step of continuously forming a plurality of semiconductor layers including a junction and forming the bipolar transistor and the field effect transistor; and a first mesa etching; Forming an emitter layer, forming a channel layer of the field effect transistor from the one-conductivity-type semiconductor layer in the second region, and performing a second mesa etching to form the one-conductivity-type semiconductor layer in the first region; The base layer of the bipolar transistor is formed by the reverse conductive semiconductor layer below A step of forming an isolation region, separating the first region and the second region, and forming an electrode of the first layer of the bipolar transistor and the field effect transistor by an ohmic metal layer, A step of depositing a gate metal layer on the surface of the one-conductivity-type semiconductor layer in the second region to form a gate electrode of the field effect transistor; and a second contact with the first layer electrode by a wiring metal layer And a step of forming a layer electrode.

  According to the present embodiment, first, a p + -type GaAs layer serving as a base layer of the HBT is disposed under and in contact with the channel layer (n-type InGaP layer or n-type AlGaAs layer) of the FET. Therefore, at the bottom of the channel layer where the impurity concentration of the n-type impurity gradually decreases, the n-type impurity having a low impurity concentration can be electrically canceled by the p-type impurity of the p-type buffer layer. As a result, the same effect can be obtained as when the impurity concentration profile is electrically steep at the bottom of the channel layer, and as a result, the pinch-off voltage Vp can be reduced.

  Further, since there is a pn junction at the bottom of the channel layer, a depletion layer is generated by the built-in voltage of the pn junction, and carriers can be prevented from leaking out of the channel layer. Therefore, the pinch-off voltage Vp can be further reduced, and as a result, the mutual conductance gm can be increased.

  When an InGaP layer is employed as the channel layer of the FET, a high breakdown voltage can be obtained because the band gap is large. In addition, since the InGaP layer is resistant to chemical stress due to its composition, the channel layer can be sufficiently protected in the case where the channel layer is exposed around the gate electrode of the FET.

  Secondly, by providing a non-doped layer on the emitter layer (channel layer), in the HBT, the non-doped layer becomes an emitter ballast resistance layer and can be prevented from being destroyed by secondary breakdown. In the FET, the non-doped layer serves as a stabilization layer, and the surface depletion layer on the channel surface can be prevented from extending into the channel. That is, it is possible to achieve high current density and low on-resistance of the FET. That is, by adding a single epitaxial layer, it is possible to simultaneously improve the reliability of the HBT and improve the performance of the FET. For example, when the stabilization layer is formed of an InGaP layer, the channel layer protection effect is very large.

  Third, in the present embodiment, all epitaxial layers are formed in one epitaxial growth step. Further, since the semiconductor layer processing steps such as ion implantation and annealing steps and base pedestal formation are not required, the manufacturing process can be prevented from becoming complicated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  FIG. 1 is a cross-sectional view showing a first embodiment of the present invention. In the compound semiconductor device 100, the HBT 101 and the FET 102 are integrated on a compound semiconductor substrate in which a plurality of semiconductor layers forming at least one heterojunction are stacked. Hereinafter, a GaAs MESFET will be described as an example of the FET 102. In the figure, the configuration of the minimum unit of the HBT 101 and the FET 102 is shown, and the second and higher electrodes are omitted.

  As shown in FIG. 1, a plurality of semiconductor layers, that is, an n + type GaAs layer 2, an n− type GaAs layer 3, a p + type GaAs layer 4, an n type InGaP layer 5, and an n + type GaAs layer are formed on a semi-insulating GaAs substrate 1. 6 are stacked. A part of the semiconductor layer is removed by etching to form a mesa shape. The n + -type GaAs layer 2 is continuous, and an isolation region 20 reaching the substrate 1 is provided. The isolation region 20 is an insulating region by ion implantation of impurities such as B +.

  The semiconductor device 100 is separated into a first region 31 and a second region 32 by the mesa and the insulating region 20. The HBT 101 is formed in the first region 31, and the FET 102 is formed in the second region 32. Each electrode of the HBT 101 and the FET 102 is formed in a comb shape in a planar pattern although illustration is omitted. The configuration shown in the figure is the minimum unit (unit element), and an active element is configured by connecting a plurality of comb-shaped unit elements in parallel. In the figure, the first region 31 and the second region 32 are disposed adjacent to each other, but may not be adjacent to each other on the same substrate.

The subcollector layer 2 of the HBT 101 is an n + type GaAs layer formed on the substrate 1 by an epitaxial growth method and doped with silicon (Si) to a relatively high impurity concentration of ³ to 6E18 cm ⁻³ . Its film thickness is several thousand mm. The collector layer 3 is an n − type GaAs layer formed on a partial region of the subcollector layer 2 and doped to an impurity concentration of about 1 to 10E16 cm ⁻³ by silicon doping. Its film thickness is several thousand mm. The base layer 4a is a p + type GaAs layer formed on the collector layer 3 and doped to an impurity concentration of about 1 to 50E18 cm ⁻³ by carbon (C) doping. The film thickness is several hundred to 2,000 mm. The emitter layer 5a is an n-type InGaP layer formed on a partial region of the base layer 4a and doped to an impurity concentration of about 1 to 10E17 cm ⁻³ by silicon doping. The film thickness is 1000 to 5000 mm. The emitter layer 5a is lattice-matched with the upper and lower GaAs layers. The emitter contact layer 6a is an n + type GaAs layer formed on the emitter layer 5a and doped to an impurity concentration of about ³ to 6E18 cm ⁻³ by silicon doping, and has a film thickness of several thousand Å.

  In the HBT 101, the emitter layer 5a and the base layer 4a form an InGaP / GaAs heterojunction.

  In addition, a ledge (shelf) L having a shape projecting toward the base electrode 8 disposed on both sides is provided at the lower portion of the emitter layer 5a. The ledge L is depleted and prevents the emitter-base recombination current from flowing on the surface of the base layer 4a below the ledge L.

  On the surface of the subcollector layer 2, a first collector electrode 7 made of an ohmic metal layer (AuGe / Ni / Au) is disposed at a position sandwiching the collector layer 3. A base electrode 8 made of an ohmic metal layer (Pt / Ti / Pt / Au) is arranged on the surface of the base layer 4a in a pattern surrounding the emitter layer 5a. A first emitter electrode 9 made of an ohmic metal layer (AuGe / Ni / Au) is disposed on the emitter contact layer 6a.

  The FET 102 uses the n-type InGaP layer 5 as a channel layer 5b. Specifically, the channel layer 5b is a region where carriers (electrons) flow. The channel layer 5b is the same semiconductor layer as the emitter layer 5a of the HBT 101.

  The InGaP layer has a large band gap and is resistant to chemical stress. That is, since the band gap of the channel layer 5b is increased, a high breakdown voltage can be obtained. Further, even if the channel layer 5b is exposed around the gate electrode 12 as shown in FIG. 1, the channel layer 5b can be sufficiently protected because it is resistant to chemical stress.

  Contact layers 6bd and 6bs are provided on the channel layer 5b. The contact layers 6bd and 6bs are the same semiconductor layers as the emitter contact layer 6a of the HBT 101. The contact layers 6bd and 6bs are also formed in a mesa shape, and the gate electrode 12 is provided on the channel layer 5b exposed between them. On the contact layers 6bd and 6bs, the first drain electrode 10 and the source electrode 11 are formed by ohmic metal layers, respectively.

  Further, by making the channel layer 5b the same semiconductor layer as the emitter layer 5a of the HBT 101, the p + GaAs layer 4 which is the same semiconductor layer as the base layer of the HBT 101 is disposed below the channel layer 5b. The p + GaAs layer 4 becomes the p-type buffer layer 4b, improves the pinch-off property, and can prevent carriers leaking from the channel layer 5b to the substrate side.

  Improving the pinch-off property of GaAsFET is one of the most important themes in GaAsFET device design. In the impurity concentration profile of GaAsFET, the bottom of the channel layer is ideally a structure that is suddenly non-doped from a certain impurity concentration. At this time, the pinch-off voltage Vp can be minimized.

  However, in practice, it is impossible to make the impurity concentration profile abruptly non-doped from a certain concentration, and the impurity concentration can only be gradually reduced at the bottom of the channel layer. As a result, the gate voltage-drain current characteristic becomes slow in the vicinity of the pinch-off voltage (the drain current does not immediately become zero even when the gate voltage is lowered), and the pinch-off voltage Vp increases accordingly. In practice, carrier leakage occurs on the substrate side outside the channel layer, so that the pinch-off voltage Vp is further increased. If the pinch-off voltage Vp of the FET becomes excessively large, it is necessary to distribute an excessive voltage for the FET operation in terms of circuit design, resulting in deterioration of the high-frequency characteristics of the circuit. Therefore, it is necessary to devise measures that do not deteriorate the high-frequency characteristics, and it is necessary to take measures to prevent the pinch-off voltage from becoming excessively high, that is, to improve the pinch-off property.

  In the present embodiment, as a method for improving the pinch-off property, a method in which the p-type buffer layer 4b is disposed in contact with the channel layer 5b is employed. By this method, the n-type impurity having a low impurity concentration can be electrically canceled by the p-type impurity in the p-type buffer layer 4b at the bottom of the channel layer where the impurity concentration of the n-type impurity gradually decreases. Therefore, the same effect as that of making the impurity concentration profile steep at the bottom of the channel layer can be obtained electrically, and as a result, the pinch-off voltage Vp can be reduced. Further, since there is a pn junction at the bottom of the channel layer, a depletion layer is generated by the built-in voltage of the pn junction, and carriers can be prevented from leaking out of the channel. Therefore, the pinch-off voltage Vp can be further reduced. As a result, the mutual conductance gm can be increased.

  In this embodiment, the p + -type GaAa layer 4 serving as the base layer 4a of the HBT 101 is used as the p-type buffer layer 4b, so that the channel layer is not added without any special process such as ion implantation, annealing, or base pedestal formation. A buffer layer 4b having a conductivity type opposite to that of 5b can be obtained.

  Instead of the n-type InGaP layer 5, an n-type AlGaAs layer may be used. In this case, in the HBT 101, the emitter layer 5a and the base layer 4a form an AlGaAs / GaAs heterojunction.

  FIG. 2 is a cross-sectional view showing a second embodiment of the present invention. In the second embodiment, a non-doped layer is disposed between an n-type InGaP layer and an n + -type GaAs layer.

  The figure shows a case where a non-doped InGaP layer 21 is disposed. In the HBT 101, the non-doped InGaP layer 21 is disposed between the emitter layer 5a and the emitter contact layer 6a and becomes the emitter ballast resistance layer 21a.

  In general, an HBT can obtain a potentially very high current density and a very low on-resistance Ron as compared with a HEMT (High Electron Mobility Transistor). However, the HBT usually has a plurality of unit elements of the HBT 101 as shown in FIG. In that case, the current concentrates on one unit element and easily breaks due to secondary breakdown.

The characteristics of the HBT base-emitter voltage V _{BE -base} current have a positive coefficient with respect to temperature. For this reason, the base-emitter voltage V _BE bias may be applied to the unit element (HBT 101) slightly larger than the other unit elements (HBT 101) due to some design non-uniformity factor. As a result, a large amount of base current and collector current flow, the temperature rises, more base current and collector current flow, and finally breakdown. This is the normal secondary yielding process. For this reason, the current density cannot actually be increased sufficiently.

  However, in the HBT 101 of this embodiment, the emitter ballast resistor layer 21a is disposed on the emitter layer 5a. That is, since the ballast resistor is connected to the emitter of the HBT 101, the secondary breakdown process is not actually started. That is, even if positive feedback that increases base current and collector current due to temperature rise in a unit element starts, the increased base current increases the voltage drop across the ballast resistor, resulting in a decrease in base current and collector current. Decrease. The above is the mechanism by which general ballast resistance prevents secondary breakdown. In the case of the present embodiment, the ballast resistor is incorporated as an epitaxial layer in the device of the HBT 101, and the heat generated by the HBT 101 is directly transmitted to the ballast resistor. Since the ballast resistor has a negative temperature coefficient, when the HBT 101 generates heat, the resistance value of the emitter ballast resistor layer 21b increases. Therefore, the heat generation of the HBT 101 further reduces the collector current of the HBT 101 and further cools the HBT 101. That is, as a result, the occurrence of secondary breakdown can be effectively prevented, and the reliability can be greatly improved.

  That is, the current density of the HBT can be significantly increased as compared with the conventional case. As a result, for example, when a power amplifier (high power amplifier) or the like is configured by the HBT of the present embodiment, secondary breakdown can be avoided and the current density can be increased overwhelmingly as compared with HEMT.

  On the other hand, in the FET 102, the non-doped InGaP layer 21 is disposed between the channel layer 5b and the contact layer 6b, and becomes the stabilization layer 21b. By disposing the stabilization layer 21b, the surface depletion layer on the surface of the channel layer 5b can be prevented from extending into the channel layer 5b. That is, high current density and low on-resistance of the FET 102 can be achieved, and high performance can be realized.

  Further, when the stabilization layer 21b is formed of an InGaP layer that is resistant to chemical stress, there is an advantage that the protective effect of the channel layer 5b is very large.

  The non-doped InGaP layer 21 may be formed by epitaxial growth continuously from the n-type InGaP layer 5. That is, the reliability of the HBT 101 and the performance of the FET 102 can be improved at the same time by only adding an epitaxial growth sequence for one semiconductor layer in the middle. Since other components are the same as those in the first embodiment, the description thereof will be omitted.

  When the emitter layer 5a and the channel layer 5b are n-type AlGaAs layers, the emitter ballast resistor layer 21a and the stabilization layer 21b may be non-doped InGaP layers or non-doped AlGaAs layers.

  FIG. 3 is a cross-sectional view showing a third embodiment. FIG. 3A is a cross-sectional view of the semiconductor device 100, and FIG. 3B is a characteristic diagram of the HBT 101.

  When the switching element is configured by the semiconductor device of the present embodiment, the HBT 101 may be an HBT that can operate symmetrically in both the forward and reverse directions (hereinafter referred to as a symmetric HBT).

With reference to FIG. 3A, a symmetric HBT 101 is formed in the first region 31. In the symmetric HBT 101, an n + type GaAs subcollector layer 2 is formed on a semi-insulating GaAs substrate 1, an n type InGaP collector layer 3, a p type GaAs base layer 4a, an n type An InGaP emitter layer 5a and an n + -type GaAs emitter contact layer 6a are stacked in a mesa shape. The collector layer 3 is an n-type InGaP layer formed on a partial region of the sub-collector layer 2 and doped to an impurity concentration of about 1 to 5E17 cm ⁻³ by silicon doping. The film thickness is 1000 to 5000 mm. Other configurations are the same as those of the first embodiment shown in FIG. The collector layer 3 and the emitter layer 5a may be AlGaAs layers instead of the InGaP layers.

  In addition to the InGaP / GaAs heterojunction formed by the emitter layer 5a and the base layer 4a, the symmetric HBT 101 also forms the InGaP / GaAs heterojunction by the collector layer 3 and the base layer 4a. .

  The transistor characteristics are different between a forward transistor operation that operates using the emitter layer 5a as an emitter (forward transistor operation) and a reverse transistor operation that operates using the emitter layer 5a as a collector (reverse transistor operation). Each structural parameter is controlled so that the characteristics are almost the same. Details of the symmetric HBT will be described later with reference to FIG.

  In the second region 32, the FET 102 is formed. The channel layer 5 b of the FET 102 is made of the same n-type InGaP layer 5 as the emitter layer 5 a of the symmetric HBT 101. A p-type buffer layer 4b made of the same p + -type GaAs layer 4 as the base layer 4a of the symmetric HBT 101 is disposed under the channel layer 5b.

  For the symmetric HBT 101, the same n-type InGaP layer 3 as the collector layer is disposed below the buffer layer 4b. However, the layer below the buffer layer 4b does not affect the operation of the FET 102. That is, even if the symmetric HBT 101 is integrated on the same substrate, the FET 102 can obtain good characteristics similar to those of the first embodiment. Other configurations are the same as those of the first embodiment, and a description thereof is omitted.

FIG. 3B is a characteristic diagram of the symmetric HBT 101. Figure symmetric HBT 101, a collector at a given base current _{I B} - shows the V-I curve of the emitter voltage _{V CE} and the collector current Ic.

In a given base current I _B collector - refers to a transistor that indicates the value of the emitter voltage V _CE and the collector current Ic is positive (+) and forward transistors, negative (-) value transistor of the opposite transistor shown a.

As shown in the figure, in the symmetric HBT 101, the on-resistance Ron (= ΔV _CE / ΔI _C ) during forward transistor operation and the on-resistance Ron ′ (= ΔV _CE ′ / ΔI _C ′) during reverse transistor operation are substantially equal. The HBT is configured as follows. In order to realize this, the emitter layer 5a and the collector layer 3 have basically the same structure. For example, when an InGaP layer is used for the emitter layer 5a, an InGaP layer is also used for the collector layer 3. When InGaP layers are used for the emitter layer 5a and the collector layer 3, they are lattice-matched with the GaAs layers (sub-collector layer 2 and emitter contact layer 6a), respectively. Further, when AlGaAs layers are used for the emitter layer 5a and the collector layer 3, the molar ratio of Al is made the same.

  Then, the impurity concentration of the emitter layer 5a and the impurity concentration of the collector layer 3 are set to substantially the same value. As a result, the base-collector breakdown voltage is lower than that of a normal HBT. However, in the switch circuit device, a base-collector breakdown voltage of 7 to 8 V is sufficient.

  By operating the collector-emitter voltage with a bias of 0 V, the symmetric HBT 101 can basically reduce the current consumption between the collector and the emitter to 0A.

  Since the HEMT generally used for the switching element is a unipolar device, the HBT is a bipolar device. Therefore, the current density can be increased significantly, and the on-resistance Ron can be extremely reduced. Further, by using the symmetric HBT 101, the collector-emitter consumption current can be reduced to zero. This is the same as the drain-source current consumption being zero in the HEMT, which means that an energy saving operation is possible. The reason is that the collector-emitter voltage can be biased to 0V in the symmetric HBT 101 in the same manner as the drain-source voltage is biased to 0V in the HEMT.

  FIG. 4 shows a fourth embodiment of the present invention. In the fourth embodiment, the non-doped layer 21 is arranged on the n-type InGaP layer 4 in the structure of the third embodiment.

  A non-doped InGaP layer 21 is provided on the emitter layer 5a of the symmetric HBT 101 and the n-type InGaP layer 5 which is the channel layer of the FET 102 and 5b. The non-doped InGaP layer 21 becomes the emitter ballast resistor layer 21a in the symmetric HBT 101 and the stable layer 21b in the FET 102. The operations of the emitter ballast resistor layer 21a and the stable layer 21b are the same as in the second embodiment.

  Further, since the symmetric HBT 101 is used, the non-doped InGaP layer 22 is also disposed below the n-type InGaP layer 3 that is the collector layer. The non-doped InGaP layer 22 becomes the collector ballast resistance layer 22a in the symmetric HBT 101. The FET 102 does not affect the operation.

  By using the symmetric HBT 101, the collector-emitter consumption current can be reduced to zero. In addition, the HBT can potentially obtain a very high current density compared to the HEMT, and can obtain a very low on-resistance Ron. However, the HBT has a problem of breaking due to secondary breakdown.

  Therefore, by arranging the emitter ballast resistor layer 21a and the collector ballast resistor layer 22a, secondary breakdown can be prevented and the on-resistance Ron of the switching element can be made extremely small. That is, when the switch MMIC is configured, the insertion loss can be very small.

  With reference to FIGS. 5 to 11, the method for manufacturing a compound semiconductor device of the present invention will be described by taking the case of the first embodiment as an example.

First step (FIG. 5): An n + -type GaAs layer 2 doped with silicon (Si) at a relatively high impurity concentration of ³ to 6E18 cm ⁻³ is formed on a GaAs substrate 1. The film thickness is several thousand mm. An n − type GaAs layer 3 doped with an impurity concentration of about 1 to 10E16 cm ⁻³ by silicon doping is formed on the upper layer to a thickness of several thousand Å. Further, a p + -type GaAs layer 4 doped to an impurity concentration of about 1 to 50E18 cm ⁻³ by carbon (C) doping is formed on the upper layer to a thickness of several hundred to 2000 mm, and about 1 to 10E17 cm ⁻³ by silicon doping. An n-type InGaP layer 5 doped to an impurity concentration is formed to a thickness of 1000 to 5000 mm. The n-type InGaP layer 5 is lattice-matched with the upper and lower GaAs layers, and the n-type InGaP layer 5 and the lower p + type GaAs layer 4 form a heterojunction. On the n-type InGaP layer 5, an n + -type GaAs layer 6 doped to an impurity concentration of about ³ to 6E18 cm ⁻³ by silicon doping is formed to a thickness of several thousand Å. All these semiconductor layers are laminated successively in one epitaxial growth process.

  A resist (not shown) is provided, and a mask having an alignment mark pattern is formed by a photolithography process. With this mask, a part of the n + -type GaAs layer 6 is etched to form an alignment mark (not shown).

  Second Step (FIG. 6): First mesa etching for forming an emitter layer of HBT in the first region 31 is performed. First, the n + -type GaAs layer 6 is mesa-etched with a desired pattern in the first region 31, and the n-type InGaP layer 5 is subsequently mesa-etched. At this time, the etching is performed while leaving a part below the n-type InGaP layer 5. Thereafter, the remaining n-type InGaP layer 5 is mesa-etched by a new photoetching process to remove the resist. Thereby, in the first region 31, the emitter contact layer 6a and the emitter layer 5a are formed in a mesa shape, and a ledge (shelf) L is formed below the emitter layer 5a.

  At the same time, an FET channel layer 5 b is formed in the second region 32. That is, the contact layer 6b and the channel layer 5b are formed in a mesa shape with a desired pattern by the first mesa etching.

  Thus, in this embodiment, the channel layer 5b that improves the characteristics of the FET can be obtained only by adding an epitaxial growth sequence for one semiconductor layer in the middle. Furthermore, an epitaxial structure that simultaneously improves the reliability of the HBT and enhances the performance of the FET can be realized without adding special processes such as ion implantation, annealing, and formation of a base pedestal.

  Third Step (FIG. 7): Next, second mesa etching for forming the base layer is performed. In the first region 31, the p + type GaAs layer 4 and the n− type GaAs layer 3 are mesa-etched with a desired pattern, and the resist is removed.

  Thereby, the base layer 4a and the collector layer 3 are formed in a mesa shape. The emitter contact layer 6a is exposed at the uppermost layer, and the base layer 4a is exposed outside the emitter layer 5a. The subcollector layer 2 is exposed outside the base layer 4a.

  In the second region 32, the p-type buffer layer 4b is formed by etching with the same pattern as the first mesa etching. As described above, the p-type buffer layer 4b is formed simultaneously by the mesa etching process of the base layer 4a of the HBT regardless of the ion implantation of impurities.

  Fourth step (FIG. 8): A part of the semiconductor layer of the first region 31 and the second region 32 is separated by space by mesa etching, but the lower layer is continuous from the n − -type GaAs layer serving as a collector layer. . Next, a nitride film for through ion implantation (not shown) is deposited on the entire surface of the substrate.

  A new resist (not shown) is provided, and a mask for forming the isolation region 20 is formed by a photolithography process. Boron (B +) ions are implanted and the resist is removed, followed by annealing at 500 ° C. for about 30 seconds. As a result, an insulating region 20 that reaches the substrate 1 and serves as an isolation region is formed. Thereafter, the nitride film for through ion implantation (not shown) is removed.

  The insulating region 20 is not electrically completely insulated, but is a region where carrier traps are provided in the epitaxial layer by ion implantation of impurities (B +). Thereby, the 1st field 31 and the 2nd field 32 are separated.

  Fifth step (FIG. 9): Next, a first layer electrode is formed. First, a photolithography process for forming a first-layer electrode is performed. After vapor deposition of the ohmic metal layer (AuGe / Ni / Au), lift-off and alloy are performed to form the emitter electrode 9 of the HBT, the collector electrode 7, the drain electrode 10 and the source electrode 11 of the FET. The first-layer emitter electrode 9, collector electrode 7, drain electrode 10 and source electrode 11 are formed in a comb shape, for example.

  Thereafter, a photolithography process for forming the base electrode is performed. After depositing the ohmic metal layer (Pt / Ti / Pt / Au), lift-off and alloying are performed to form the base electrode 8 of the HBT. The base electrode 8 is formed at a position surrounding the emitter electrode 9. Thereby, the basic structure of the HBT 101 is formed in the first region 31.

  Sixth step (FIG. 10): The nitride film 51 is again deposited on the entire surface. The nitride film 51 is etched by performing a photolithography process. Thus, a mask for recess etching of the gate of the FET is formed in the second region 32.

  Next, recess etching of the gate is performed. That is, the contact layer 6b (n + type GaAs layer) exposed from the recess etching mask is removed by etching. At this time, the contact layer 6b is side-etched larger than the opening width of the mask to ensure a predetermined breakdown voltage.

  The contact layer 6b is separated into a contact layer 6bs serving as a source region of the FET and a contact layer 6bd serving as a drain region. Further, the protruding portion of the mask is removed by plasma etching, and a gate metal layer (Pt / Mo) is deposited. Thereafter, lift-off and heat treatment are performed, and a part of Pt is embedded in the surface of the channel layer 5b to form the gate electrode 12.

  As a result, the basic structure of the FET 102 is formed in the second region 32.

  Further, a nitride film 51 serving as a passivation film is deposited on the entire surface. A photolithography process is performed to form contact holes with the second-layer electrode and wiring. The nitride film 51 is etched to form a contact hole CH, and the resist is removed.

  Seventh step (FIG. 11): a step of forming a second layer electrode in contact with the first layer electrode by a wiring metal layer.

  A new photolithography process is performed to deposit a second-layer electrode and a wiring metal layer (Ti / Pt / Au) to be a wiring on the entire surface. The wiring metal layer is lifted off, and the second-layer electrode and wiring are formed. That is, in the first region 31, the second-layer collector electrode 13 and the emitter electrode 15 that are in contact with the first-layer collector electrode 7 and the emitter electrode 9, respectively, are formed. In the second region 32, a second drain electrode 16 and a source electrode 17 are formed in contact with the first drain electrode 10 and the source electrode 11, respectively. The second layer electrode serves as a wiring for connecting the unit elements of the HBT 101 and the FET 102 shown in the figure to other unit elements. Furthermore, the wiring is also used for connection with resistors, capacitors and bonding pads.

  Further, if necessary, wiring by gold plating may be performed thereafter.

Note that the separation region 20 formation step of the fourth step may be performed at any stage as long as it is before the formation of the first ohmic metal layer.

It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is (A) sectional drawing and (B) characteristic view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 Subcollector layer 3 Collector layer 4a Base layer 5a Emitter layer 6a Emitter contact layer 7, 13 Collector electrode 8 Base electrode 9, 15 Emitter electrode 4b P-type buffer layer 5b Channel layer 6bs, 6bd Contact layer 10, 16 Drain Electrode 11, 17 Source electrode 12 Gate electrode 20 Separating region 21 Non-doped InGaP layer
22 Non-doped InGaP layer
31 1st area | region 32 2nd area | region 100 Semiconductor device 101 HBT
102 MESFET

Claims (14)

A compound semiconductor device in which a bipolar transistor and a field effect transistor are respectively integrated in a first region and a second region of a compound semiconductor substrate in which a plurality of semiconductor layers forming at least one heterojunction are stacked,
One compound semiconductor layer in the first region is used as an emitter layer of the bipolar transistor, and the one conductivity type semiconductor layer in the second region is used as a channel layer of the field effect transistor. .   The compound semiconductor device according to claim 1, wherein a reverse conductivity type semiconductor layer is disposed below the one conductivity type semiconductor layer.   The compound semiconductor device according to claim 1, wherein the one conductivity type semiconductor layer is an InGaP layer.   The compound semiconductor device according to claim 1, wherein the one conductivity type semiconductor layer is an AlGaAs layer.   The compound semiconductor device according to claim 2, wherein the reverse conductivity type semiconductor layer is a GaAs layer.   3. The reverse conductivity type semiconductor layer in the first region is used as a base layer of the bipolar transistor, and the reverse conductivity type semiconductor layer in the second region is used as a buffer layer of the field effect transistor. The compound semiconductor device described.   The compound semiconductor device according to claim 1, wherein a non-doped layer is disposed on the upper layer of the one conductivity type semiconductor layer.   2. The compound semiconductor device according to claim 1, wherein another one conductivity type semiconductor layer of the same compound as the one conductivity type semiconductor layer in the first region is used as a collector layer of the bipolar transistor.   9. The compound semiconductor device according to claim 8, wherein a non-doped layer is disposed under the other one conductivity type semiconductor layer. A method of manufacturing a compound semiconductor device in which bipolar transistors and field effect transistors are integrated in a first region and a second region of a compound semiconductor substrate, respectively.
Continuously forming a plurality of semiconductor layers including at least one heterojunction on the substrate to form the bipolar transistor and the field effect transistor by one-time epitaxial growth;
Performing a first mesa etching to form an emitter layer of the bipolar transistor by the one-conductivity-type semiconductor layer of the first region, and forming a channel layer of the field-effect transistor by the one-conductivity-type semiconductor layer of the second region; And a process of
Performing a second mesa etching to form a base layer of the bipolar transistor with a reverse conductivity type semiconductor layer below the one conductivity type semiconductor layer in the first region;
Forming a separation region and separating the first region and the second region;
Forming a first layer electrode of the bipolar transistor and the field effect transistor by an ohmic metal layer;
Depositing a gate metal layer on the surface of the one-conductivity-type semiconductor layer in the second region to form a gate electrode of the field effect transistor;
Forming a second layer electrode in contact with the first layer electrode by a wiring metal layer;
A method of manufacturing a compound semiconductor device comprising:   The method of manufacturing a compound semiconductor device according to claim 10, wherein a buffer layer of the field effect transistor is formed by the second mesa etching.   The method of manufacturing a compound semiconductor device according to claim 10, wherein the one conductivity type semiconductor layer is an InGaP layer.   The method of manufacturing a compound semiconductor device according to claim 10, wherein the one-conductivity-type semiconductor layer is an AlGaAs layer. 11. The method of manufacturing a compound semiconductor device according to claim 10, wherein a GaAs layer is formed under the one conductivity type semiconductor layer.