JP6463214B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Semiconductor devices used in the field of power electronics include field effect transistors such as MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), and JFETs (Junction Field Effect Transistors). These semiconductor devices are required to have high reliability from the viewpoint of application to power electronics.

  For example, if an arm short circuit or load short circuit (hereinafter referred to as “short circuit”) occurs when an inductive load or a resistive load is driven by applying the MOSFET to an inverter circuit or the like, an abnormally large current is generated in the MOSFET. (Overcurrent) flows. In this state, a drain current several times to several tens of times the rated current is induced in the MOSFET, and if the device does not have an appropriate protection function, the MOSFET element is destroyed.

  In general, as a method of preventing destruction of a MOSFET element (element destruction), an excessive drain current is detected before the element destruction, and an off signal is input to the gate electrode when the drain current is detected. A method is used to shut off. In this case, the MOSFET element is required to have robustness that does not cause element destruction over a period of time from when a short circuit occurs until an overcurrent is detected and an off signal is input to the gate electrode. That is, as one of the high reliability of the semiconductor device, it is strongly desired that the short circuit tolerance is high. Note that the short-circuit tolerance is substantially defined by the time from the occurrence of a short-circuit until the element is destroyed, and it can be said that the short-circuit tolerance is higher as the time until the destruction is longer.

  For example, in Patent Document 1 below, a structure of an emitter region (corresponding to a source region of a MOSFET) serving as an on-current path of an IGBT is described as a high-resistance emitter layer (high resistance) in order to improve the short-circuit withstand capability of the IGBT. Region) and a low resistance emitter layer (low resistance region) are alternately arranged in parallel between the emitter electrode (corresponding to the source electrode of the MOSFET) and the channel region (corresponding to the well region of the MOSFET). A method of providing a structured structure is disclosed.

JP 2003-332577 A

  Since a semiconductor device generates heat due to an overcurrent, it is desirable as a characteristic of the semiconductor device that the on-resistance increases and the overcurrent is suppressed at a high temperature. In the semiconductor device of Patent Document 1, since the emitter region is configured by a high resistance region and a low resistance region connected in parallel, the emitter electrode is connected not only to the low resistance region but also to the high resistance region. For this reason, the contact resistance between the emitter electrode and the emitter region is increased, and the on-resistance of the semiconductor device is increased. On the other hand, the contact resistance is reduced at a high temperature, so that the contact resistance between the emitter electrode and the emitter region is reduced at the time of a short circuit. Therefore, the method of increasing the contact resistance among the on-resistance components cannot sufficiently reduce the overcurrent at a high temperature.

  The present invention has been made to solve the above-described problems, and provides a semiconductor device capable of improving the short-circuit tolerance by suppressing an overcurrent during a short circuit while suppressing an increase in on-resistance. The purpose is to do.

A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate, a first conductivity type drift layer formed on the semiconductor substrate, and a second conductivity type well formed on a surface layer portion of the drift layer. A first conductivity type source region formed in the well region and partially narrowed in plan view, a gate insulating film formed on the drift layer, and on the gate insulating film A semiconductor device including a gate electrode formed above and extending above the well region and the source region, a channel region that is a portion of the well region below the gate electrode, and a source electrode connected to the source region comprising a device, source stenosis is a narrowing portion of said source region, it said provided separated from the channel region and the source electrode, on the source stenosis of the insulating film is formed To have.

A semiconductor device according to a second aspect of the present invention includes a semiconductor substrate, a first conductivity type drift layer formed on the semiconductor substrate, and a second conductivity type well formed on a surface layer portion of the drift layer. A region, a plurality of first conductivity type source regions formed in the well region, a first conductivity type source bridge portion that partially bridges between the source regions, and the drift layer A formed gate insulating film; a gate electrode formed on the gate insulating film and extending above the well region and the source region; and a channel region that is a portion of the well region below the gate electrode; , comprising a semiconductor device comprising a source electrode connected to said source region, said plurality of source regions and the source bridge section, it is connected in series between the source electrode and the channel region The source bridge portion are spaced apart from the channel region and the source electrode, on the source bridge portion is formed an insulating film.

  According to the present invention, when a large current flows through the semiconductor element, the source constriction portion or the source bridge portion generates heat, and the resistance value thereof increases, so that the on-resistance increases, and the overcurrent is suppressed. Furthermore, since the voltage drop at the source constriction portion or the source bridge portion becomes large, the overcurrent is suppressed even when the effective gate voltage is lowered. As a result, the time until the semiconductor device is destroyed at the time of a short circuit becomes longer, and the short-circuit tolerance of the semiconductor device is improved.

FIG. 3 is a top view schematically showing the configuration of the MOSFET according to the first embodiment. 4 is a schematic top view of a unit cell of MOSFET according to the first embodiment. FIG. FIG. 3 is a cross-sectional view of a MOSFET half unit cell according to the first embodiment. FIG. 3 is a cross-sectional view of a MOSFET half unit cell according to the first embodiment. 3 is a schematic top view of a comb-shaped cell of a MOSFET according to the first embodiment. FIG. 6 is a schematic top view of a unit cell of a modification of the MOSFET according to the first embodiment. FIG. 6 is a schematic top view of a unit cell of a modification of the MOSFET according to the first embodiment. FIG. 6 is a schematic top view of a unit cell of a modification of the MOSFET according to the first embodiment. FIG. 6 is a schematic top view of a comb-shaped cell of a modification of the MOSFET according to the first embodiment. FIG. 6 is a schematic top view of a comb-shaped cell of a modification of the MOSFET according to the first embodiment. FIG. FIG. 10 is a cross-sectional view of a half unit cell of a modification of the MOSFET according to the first embodiment. FIG. 10 is a cross-sectional view of a half unit cell of a modification of the MOSFET according to the first embodiment. 6 is a diagram for explaining the method of manufacturing the MOSFET according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the MOSFET according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the MOSFET according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the MOSFET according to the first embodiment. FIG. 6 is a schematic top view of a unit cell of a MOSFET according to Embodiment 2. FIG. 6 is a schematic top view of a comb-shaped cell of a MOSFET according to a second embodiment. FIG. FIG. 5 is a cross-sectional view of a half unit cell of a MOSFET according to a second embodiment. FIG. 10 is a schematic top view of a unit cell of a modification of the MOSFET according to the second embodiment. FIG. 10 is a cross-sectional view of a half unit cell of a modification of the MOSFET according to the second embodiment. FIG. 10 is a cross-sectional view of a half unit cell of a modification of the MOSFET according to the second embodiment. FIG. 10 is a schematic top view of a unit cell of a modification of the MOSFET according to the second embodiment. FIG. 10 is a cross-sectional view of a half unit cell of a modification of the MOSFET according to the second embodiment. 6 is a schematic top view of a unit cell of a MOSFET according to a third embodiment. FIG. FIG. 5 is a cross-sectional view of a half unit cell of a MOSFET according to a third embodiment. FIG. 5 is a cross-sectional view of a half unit cell of a MOSFET according to a third embodiment. FIG. 6 is a cross-sectional view of a half unit cell of a trench MOSFET according to a fourth embodiment. FIG. 6 is a cross-sectional view of a half unit cell of a trench MOSFET according to a fourth embodiment. FIG. 10 is a cross-sectional view of a half unit cell of a modification of the trench MOSFET according to the fourth embodiment. FIG. 6 is a cross-sectional view of a half unit cell of a trench MOSFET according to a fourth embodiment. FIG. 9 is a schematic top view of a unit cell of a MOSFET according to a fifth embodiment. FIG. 9 is a schematic top view of a unit cell of a MOSFET according to a fifth embodiment. FIG. 10 is a cross-sectional view of a MOSFET half unit cell according to a sixth embodiment. FIG. 16 is a cross-sectional view of a half unit cell of a modification of the MOSFET according to the sixth embodiment.

  In the following embodiments, the definition of the impurity conductivity type is n-type “first conductivity type” and p-type “second conductivity type”, but this definition may be reversed. That is, the “first conductivity type” may be p-type and the “second conductivity type” may be n-type.

  Further, in this specification, each semiconductor element is referred to as a “semiconductor device” in a narrow sense. For example, a free wheel diode connected to a chip of a semiconductor element and anti-parallel to the semiconductor element on a lead frame. In addition, a semiconductor module (for example, a power module such as an inverter module) mounted with a control circuit that applies a voltage to the gate electrode of the semiconductor element and integrally sealed is also referred to as a “semiconductor device” in a broad sense. included.

<Embodiment 1>
FIG. 1 schematically shows a top surface configuration of a silicon carbide MOSFET that is a semiconductor device according to the first embodiment. As shown in FIG. 1, a source pad 41, a gate wiring 44, and a gate pad 45, which are source electrodes, are formed on the outermost surface of the MOSFET. The gate wiring 44 is connected to the gate pad 45 and is formed so as to surround the source pad 41. The gate pad 45 is disposed near the center of one side of the gate wiring 44. A region 7 surrounded by a dotted line in FIG. 2 is an active region, and a plurality of MOSFET cells (unit cells) are arranged in parallel.

  In FIG. 1, the outside of the active region 7 is a termination region and extends to the end of the chip 5. A feature of the present invention relates to a semiconductor device structure disposed in the active region 7, and the structure of the termination region may be arbitrary. Therefore, description of the termination region is omitted.

  The gate electrode of each unit cell is connected to the gate pad 45 via the gate wiring 44, and the gate voltage applied to the gate pad 45 from an external control circuit (not shown) is Applied to the gate electrode. Similarly, the source region of each unit cell is connected to the source pad 41.

  In an actual product of a semiconductor device, each electrode for a temperature sensor and a current sensor for operating an external protection circuit is often provided on a semiconductor element such as a MOSFET. Since it is not related to the embodiment, it is omitted in this embodiment.

  The layout of the gate pad 45, the gate wiring 44, and the source pad 41 is not limited to that shown in FIG. Their shape, number, etc., vary widely depending on the product. The presence / absence of electrodes for the temperature sensor and the current sensor and the layout of each electrode do not significantly affect the effect of this embodiment, and may be arbitrary.

  FIG. 2 is a top view of the unit cell of the MOSFET according to the first embodiment. A plurality of unit cells shown in FIG. 2 are formed in a lattice pattern in the active region 7 of FIG. 3 and 4 are cross-sectional views of the unit cell. 3 corresponds to a cross section taken along line A1-A2 in FIG. 2, and FIG. 4 corresponds to a cross section taken along line B1-B2 in FIG. 2, each showing a right half of one unit cell. FIG. That is, FIGS. 3 and 4 each show a cross section of the half unit cell, and the cross section across the entire unit cell has a structure in which FIG. 3 or FIG. 4 is combined with the mirror inverted to the left. ing. In FIG. 2, the source pad 41, the interlayer insulating film 32, the gate electrode 35, and the gate insulating film 30 shown in FIGS. 3 and 4 are not shown.

  As shown in FIGS. 3 and 4, the MOSFET includes a semiconductor substrate 1 made of silicon carbide of a first conductivity type (n-type) and a first conductivity type drift layer 2 (epitaxially grown on the surface thereof) ( And an epitaxial substrate made of a silicon carbide semiconductor layer. A drain electrode 43 is formed on the back surface of the semiconductor substrate 1 via a back surface ohmic electrode 42 that is in ohmic contact with the semiconductor substrate 1.

  A second conductivity type (p-type) well region 20 is selectively formed in the surface layer portion of the drift layer 2. Further, a first conductivity type source region 12 and a second conductivity type well contact region 25 are formed in the surface layer portion in the well region 20.

  In the drift layer 2, a region 11 adjacent to the well region 20 (a region sandwiched between the well regions 20 of adjacent unit cells) is called a “JFET region”. In the well region 20, the surface layer portion of the region sandwiched between the JFET region 11 and the source region 12 is a region where a channel is formed when the MOSFET is conductive, and is called a “channel region”.

  A gate insulating film 30 is formed on the drift layer 2, and a gate electrode is formed on the gate insulating film 30 so as to straddle the source region 12, the well region 20 (channel region), and the JFET region 11. 35 is formed.

  The gate electrode 35 is covered with an interlayer insulating film 32. A contact hole (source contact hole) reaching a part of the source region 12 and the well contact region 25 is formed in the interlayer insulating film 32 and the gate insulating film 30, and the source region 12 and the well contact region are formed at the bottom thereof. A source ohmic electrode 40 that is in ohmic contact with the electrode 25 is formed. In FIG. 2, the formation region of the source ohmic electrode 40 (corresponding to the source contact hole) is indicated by a dotted line.

  A source pad 41 is formed on the interlayer insulating film 32, and the source pad 41 is connected to the source ohmic electrode 40 through a source contact hole. Thereby, the source pad 41 is electrically connected to the source region 12 and the well contact region 25. 1 is connected to the gate electrode 35 through a contact hole (gate contact hole) formed in a region (not shown).

  Here, as shown in FIG. 2, the source region 12 of the MOSFET according to the first embodiment has a source constriction portion 15 whose width (length in a direction perpendicular to the current path) is narrowed in plan view. ing. That is, in the B1-B2 cross section including the source constriction portion 15, the source region 12 continuously extends from the source ohmic electrode 40 to the channel region as shown in FIG. 4, but the A1-A2 cross section does not include the source constriction portion 15. Then, as shown in FIG. 3, there is a portion where the source region 12 is divided between the source ohmic electrode 40 and the channel region. Although the source region 12 appears to be divided into a plurality of parts in FIG. 3, as can be seen from FIG. 2, the source region 12 is integrally formed in the unit cell.

  The source constriction 15 is disposed between the source ohmic electrode 40 and the channel region so as to be separated from the channel region. Therefore, the source constriction 15 is a path through which current flows.

  2 shows a unit cell having a quadrangular planar structure, the unit cell may have any shape, and may be, for example, a polygon (rectangle, hexagon, etc.) or a circle. Further, it may be a comb shape or a stripe structure as shown in FIG. 5 (a unit cell having this structure is referred to as a “comb cell”). In the comb cell of FIG. 5, an ohmic electrode 40b connected to the well contact region 25 is formed apart from the source ohmic electrode 40 connected to the source region 12.

  2 and 5, the source region 12 has a plurality of source confinement portions 15. However, the width W15 (length in the direction perpendicular to the current path) and length L15 (length of each source confinement portion 15). The length in the direction along the current path is constant within an error range of about 10%. By doing so, the resistance of each source constriction part 15 becomes substantially the same, the current distribution in the unit cell becomes non-uniform (current imbalance), the variation in the heat generation distribution, and the semiconductor element resulting therefrom The deterioration of the semiconductor device can be suppressed, and the reliability of the semiconductor device is improved.

  In the structure shown in FIG. 2, the width W15 of the source constriction 15 may be 0.1 μm or more and 5 μm or less, and preferably 0.2 μm or more and 1 μm or less. Further, the length L15 of the source constriction 15 may be 0.1 μm or more and 5 μm or less, and preferably 0.2 μm or more and 1 μm or less. By setting the width W15 and the length L15 of the source confinement portion 15 in the above ranges, the source constriction portion 15 does not excessively increase the on-resistance during the rated operation of the MOSFET and generates a large current such as during a short circuit. The resistance can be increased by promoting local fever. As a result, the overcurrent is suppressed, so that the time until the element is destroyed can be extended, and the short-circuit tolerance of the MOSFET is improved.

  Further, as shown in FIG. 2, the first conductivity type source constriction portion 15 is sandwiched between the second conductivity type well regions 20, and a parasitic JFET is formed by the configuration of the source confinement portion 15 and its periphery. By setting the width W15 and the length L15 of the source confinement portion 15 in the above ranges, the parasitic JFET effect, that is, the effect of increasing resistance due to the depletion layer entering the source confinement portion 15 and narrowing the current path is more effective. It becomes remarkable and the short circuit tolerance can be further improved.

  For example, FIG. 4 and FIG. 14 of International Publication No. WO2013 / 172079 disclose a structure in which a source resistance control region is provided between two source regions. Compared with this, since the source constriction portion 15 of the present embodiment is formed by constricting a part of the source region 12, an increase in on-resistance during the rated operation of the MOSFET is suppressed. Furthermore, the above-mentioned parasitic JFET effect cannot be obtained in the semiconductor device disclosed in International Publication No. WO2013 / 172079. In the present invention, since these effects are obtained in addition to the effects described in International Publication No. WO2013 / 172079, the short-circuit resistance can be further improved.

  2 shows an example in which the source constriction portion 15 is arranged at the center of each side of the unit cell, the position of the source constriction portion 15 is not limited to this. For example, as shown in FIG. 6, the source constriction portion 15 may be shifted from the central portion of each side, or as shown in FIG. 7 and FIG. 8, the source constriction portion 15 is arranged at each corner portion of the unit cell. Also good. Although the number and arrangement | positioning of the source constriction part 15 can assume various things, it is preferable to arrange | position the several source confinement part 15 so that it may become point-symmetrical with respect to the center of a unit cell. By doing so, the current distribution and the heat generation distribution are leveled, and variations in the heat generation distribution due to current imbalance and element degradation caused by the variation can be suppressed.

  On the other hand, FIG. 5 shows an example in which the source constriction portions 15 having a uniform width are arranged at equal intervals in the comb cell, but the arrangement of the source constriction portions 15 in the comb cell is not limited to this. If the distance from the source ohmic electrode 40 connected to the source region 12 to each source constriction 15 is not uniform, current imbalance may occur. To prevent this, for example, as shown in FIG. The source confinement portion 15 near the source ohmic electrode 40 connected to the source region 12 has a narrow width (increases resistance), and the source constriction portion 15 far from the source ohmic electrode 40 has a wide width (low resistance). May be. For example, as shown in FIG. 10, the source constriction 15 near the source ohmic electrode 40 connected to the source region 12 is long (resistance is increased), and the source constriction 15 far from the source ohmic electrode 40 is short. Even if the resistance is reduced, current imbalance is similarly prevented. Furthermore, both the width and length of each source constriction 15 may be changed according to the distance from the source ohmic electrode 40 connected to the source region 12.

  By the way, in the MOSFET, the drain current at the time of ON or short-circuit in rated operation is changed from the drain electrode 43 on the back surface of the semiconductor substrate 1 to the back ohmic electrode 42, the semiconductor substrate 1, the drift layer 2, the JFET region 11, and the channel region. , Flows through the source region 12 and the source ohmic electrode 40 to the source pad 41. When the source region 12 has the source constriction portion 15 as in the present embodiment, current concentration occurs in the source constriction portion 15, so that the temperature of the source constriction portion 15 rises locally. Since the carrier mobility decreases as the temperature rises, the sheet resistance increases as the temperature of the source constriction portion 15 rises, and the voltage drop at the source constriction portion 15 becomes remarkable.

  Originally, the contact resistance between the source region 12 and the source ohmic electrode 40 and the parasitic resistance of the source region 12 are almost negligible, so the potential of the source region 12 is fixed to a potential substantially equal to the source potential (earth potential). However, when a voltage drop occurs in the source constriction portion 15, the potential of the source region 12 adjacent to the channel region becomes higher than the ground potential by the voltage drop. As a result, the effective gate voltage applied to the channel region is lowered and the drain current is reduced.

  This decrease in the drain current serves to improve the short-circuit tolerance of the MOSFET when a large current flows during a short circuit. That is, when the current density of the source constriction portion 15 increases transiently due to a short circuit, the resistance of the source constriction portion 15 increases and the voltage drop at the source constriction portion 15 increases. As a result, the effective gate voltage is lowered and the drain current (overcurrent) is reduced, thereby improving the short-circuit tolerance. As described above, the source constriction 15 not only increases the resistance by heat generation and suppresses the overcurrent when a large current flows, but also reduces the effective gate voltage by increasing the voltage drop. There is a synergistic effect that current can be suppressed.

  On the other hand, the parasitic resistance of the source region 12 is increased by providing the source constriction 15 in the source region 12 during the rated operation, but the source region 12 and the source constriction 15 are at a temperature close to room temperature during the rated operation. The resistance of the source constriction 15 does not increase as in the case of a short circuit. Therefore, the resistance of the source region 12 at the rated operation does not increase excessively. Therefore, according to the semiconductor device of the present embodiment, it is possible to improve the short-circuit tolerance while suppressing an increase in on-resistance during rated operation.

  Such an effect of the source constriction portion 15 is particularly high in a semiconductor device formed using a wide band gap semiconductor such as silicon carbide, compared to a semiconductor device formed using silicon. The reason will be described below.

  As a method of increasing the short-circuit tolerance of the semiconductor device, for example, a method of increasing the channel resistance is also conceivable. In general, the channel resistance can be increased by increasing the channel length. However, in a semiconductor device formed using a wide band gap semiconductor, since the interface state density between the channel region and the gate insulating film is high, electrons trapped in the interface state when the temperature of the element rises due to a large current Since (or holes) are emitted and the channel resistance is reduced, an increase in channel resistance due to an increase in channel length is offset. Therefore, when a material having a high interface state density is used, the channel length needs to be significantly increased in order to improve the short-circuit resistance. For example, in a MOSFET, since the channel mobility at the rated operation temperature is low, it is not preferable to increase the channel length because the on-resistance is remarkably increased and the loss of the device is increased. Therefore, it can be said that it is not suitable for a semiconductor device using a wide band gap semiconductor by increasing the channel resistance and increasing the short-circuit tolerance.

  On the other hand, in the present invention, by providing the source constriction 15, the short-circuit withstand capability can be improved without increasing the channel length, so that the semiconductor device using a wide band gap semiconductor such as silicon carbide can be used. It is very effective.

  Here, the positional relationship between the source constriction 15 and the gate electrode 35 is that the gate electrode 35 does not exist on the source constriction 15 as shown in FIGS. 3 and 4 and the gate electrode 35 on the source constriction 15. (FIG. 11 shows the A1-A2 cross section in that case) and the end portion of the gate electrode 35 is located on the source constriction portion 15 so that the source constriction portion 15 is partially covered with the gate electrode 35 (FIG. 12 shows an A1-A2 cross section in that case). The source constriction portion 15 has a higher resistance than other portions of the source region 12 and is likely to generate heat. In the present invention, the heat generation is used to improve the short-circuit resistance. However, when the MOS structure including the gate electrode 35 is formed on the source constriction portion 15, the gate leakage current increases due to heat generation of the source constriction portion 15, or the short circuit withstand capability decreases due to the dielectric breakdown of the gate insulating film 30. May cause another problem. Therefore, a configuration in which the gate electrode 35 does not exist on the source constriction 15 as shown in FIGS. 3 and 4 is preferable.

  When the gate electrode 35 is formed on the source constriction 15 as shown in FIG. 11, the portion of the well region 20 sandwiching the source constriction 15 becomes the second channel region, but in parallel therewith the source constriction 15 Therefore, the second channel region does not function during rated operation. When a large current flows, such as during a short circuit, a potential drop occurs in the source constriction portion 15, so that the current starts to flow also in the second channel region. However, since the channel resistance of the second channel region is large, the potential of the source region 12 adjacent to the original channel region rises, and the effect of improving the short-circuit resistance due to the effective reduction of the gate voltage is obtained.

  Hereinafter, a method of manufacturing the semiconductor device (MOSFET) according to the first embodiment will be described with reference to FIGS. First, a semiconductor substrate 1 made of first conductivity type silicon carbide is prepared. The semiconductor substrate 1 may be made of silicon carbide, silicon, or another wide band gap semiconductor having a band gap larger than that of silicon. Examples of wide band gap semiconductors include gallium nitride, aluminum nitride, and diamond in addition to silicon carbide. The plane orientation of the semiconductor substrate 1 may be arbitrary. For example, the surface vertical direction may be inclined by 8 ° or less with respect to the c-axis direction, or may not be inclined. The thickness of the semiconductor substrate 1 may be arbitrary, for example, about 350 μm or about 100 μm.

Subsequently, the first conductivity type drift layer 2 is formed on the semiconductor substrate 1 by epitaxial crystal growth. The impurity concentration of the first conductivity type of the drift layer 2 is about 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and the thickness is ³ μm to 200 μm. The drift layer 2 may not be formed directly on the semiconductor substrate 1 but may be formed on the semiconductor substrate 1 via a buffer layer.

  The impurity concentration distribution of the first conductivity type of the drift layer 2 is desirably constant in the thickness direction, but may not be constant, for example, the impurity concentration may be intentionally lowered near the surface. In that case, the electric field generated in the gate insulating film 30 when a reverse bias is applied to the MOSFET element is reduced, the reliability of the element is improved, and the threshold voltage of the element can be set high.

  Next, the second conductivity type well region 20 and the well contact region 25 are formed by ion implantation of impurities (dopant) using an implantation mask (for example, a photoresist or a silicon oxide film) patterned by photolithography. FIG. 13).

The depth of the bottom of the well region 20 needs to be set so as not to exceed the bottom of the drift layer 2 and is, for example, about 0.2 μm to 2.0 μm. Further, the maximum value of the second conductivity type impurity concentration in the well region 20 exceeds the value of the first conductivity type impurity concentration of the drift layer 2, for example, 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁹ cm ^−3. Is set within the range.

Further, the depth of the bottom of the well contact region 25 needs to be set so as not to exceed the well region 20, for example, about 0.1 to 1.5 μm. Further, the impurity concentration of the second conductivity type in the well contact region 25 exceeds that of the well region 20, and for example, the maximum impurity concentration is set to about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ^−3. Is done.

  These ion implantations may be performed by heating the semiconductor substrate 1 to, for example, 150 ° C. or higher. By doing so, for example, the well contact region 25 has a low sheet resistance, and a low contact resistance with the metal electrode can be realized. Note that, as an impurity to be ion-implanted, nitrogen or phosphorus is preferable as an n-type impurity, and aluminum or boron is preferable as a p-type impurity.

  Further, the first conductivity type source region 12 is formed by ion implantation of impurities using an implantation mask patterned by photolithography. The source region 12 is formed in a pattern in which a part thereof becomes the source constriction portion 15. Thus, since the source constriction 15 is formed by the same ion implantation process as other portions of the source region 12, the impurity concentration distribution of the first conductivity type in the source confinement 15 is different from that of the source region 12. In the portion, the impurity concentration distribution of the first conductivity type is the same. In addition, by doing so, an increase in the number of processes can be suppressed, which can contribute to a reduction in manufacturing cost.

  In the half unit cell, the cross section including the region where the source constriction 15 is formed (corresponding to the cross section A1-A2 in FIG. 2) has a structure in which the source region 12 is divided into two as shown in FIG. In the cross section of the region where the portion 15 is not formed (corresponding to the B1-B2 cross section of FIG. 2), the integrated source region 12 extends as shown in FIG.

The bottom depth of the source region 12 is set so as not to exceed the bottom depth of the well region 20. The impurity concentration of the first conductivity type in the source region 12 exceeds the impurity concentration of the second conductivity type in the well region 20 in the unit cell. For example, the maximum impurity concentration is 1 × 10 ¹⁸ cm ⁻³ to It is set to about 1 × 10 ²¹ cm ⁻³ . As for the impurity to be ion-implanted in this step, nitrogen or phosphorus is preferable as the n-type impurity, and aluminum or boron is preferable as the p-type impurity.

  Here, the thermal diffusion coefficient of impurities in silicon carbide is much smaller than the thermal diffusion coefficient of impurities in silicon conventionally used for power devices. Therefore, even when a high temperature heat treatment such as activation annealing is performed, redistribution of implanted impurities due to thermal diffusion hardly occurs, and the distribution at the time of implantation is substantially maintained. Therefore, the width and length of the source constriction 15 are substantially determined by the width and length of the implantation mask when the source region 12 is formed.

  Subsequently, ion implantation for forming the structure of the termination region (not shown), additional ion implantation into the JFET region 11 and the channel region as necessary, etc. are performed, and then the impurity implanted into the drift layer 2 is implanted. Heat treatment for electrical activation is performed. This heat treatment is preferably performed in an inert gas atmosphere such as argon or nitrogen or in a vacuum at a temperature of 1500 ° C. to 2200 ° C. for a time of 0.5 to 60 minutes.

  In this heat treatment, the surface of the drift layer 2 is covered with a film made of carbon, or the surface of the drift layer 2, the back surface of the semiconductor substrate 1, and the end faces of the semiconductor substrate 1 and the drift layer 2 are made of carbon. You may carry out in the state covered. Thereby, it is possible to prevent the surface of the drift layer 2 from being roughened by etching due to a reaction with residual moisture or residual oxygen in the apparatus during the heat treatment.

  Thereafter, a gate insulating film 30 made of, for example, a silicon oxide film is formed on the surface of the drift layer 2. Examples of the method for forming the gate insulating film 30 include a thermal oxidation method and a deposition method. Further, after a silicon oxide film is formed by a thermal oxidation method or a deposition method, a heat treatment in a nitriding oxide gas (NO, N 2 O, etc.) atmosphere or an ammonia atmosphere, or a heat treatment in an inert gas (argon, etc.) atmosphere may be performed. Good. If heat treatment is performed in a nitriding gas atmosphere, a high-quality MOS interface having a low interface state density can be formed by nitrogen pileup and passivation effect on the MOS interface.

  Then, polycrystalline silicon or polycrystalline silicon carbide is deposited on the gate insulating film 30 by the CVD method, and patterning is performed by photolithography and etching to form the gate electrode 35 (FIG. 16). FIG. 16 corresponds to the B1-B2 cross section of FIG.

  The polycrystalline silicon or polycrystalline silicon carbide used for the gate electrode 35 preferably contains phosphorus, boron, aluminum, or the like and has an n-type or p-type low sheet resistance. Phosphorus, boron, or aluminum contained in polycrystalline silicon or polycrystalline silicon carbide may be incorporated during the film formation, or may be subjected to activation heat treatment or thermal diffusion by ion implantation after the film formation. Furthermore, the material of the gate electrode 35 may be a metal, an intermetallic compound, or a multilayer film thereof.

  Next, an interlayer insulating film 32 is formed on the drift layer 2 by a CVD method or the like. Then, a contact hole (source contact hole) for connecting the source pad 41 to the source region 12 and the well contact region 25 by selectively removing the interlayer insulating film 32 and the gate insulating film 30 by, for example, a dry etching method. Form. Further, a contact hole (gate contact hole) for connecting the gate wiring 44 to the gate electrode 35 may be formed at the same time. Thereby, the process steps are simplified and the manufacturing cost can be reduced.

  Subsequently, a source ohmic electrode 40 is formed on the surface of the drift layer 2 exposed at the bottom of the source contact hole. The source ohmic electrode 40 realizes ohmic contact with the source region 12 and the well contact region 25.

  The source ohmic electrode 40 is formed, for example, by the following procedure. First, a metal film containing nickel as a main component is formed on the entire surface of the drift layer 2 including the inside of the source contact hole. Next, the metal film is reacted with silicon carbide (the source region 12 and the well contact region 25) at the bottom of the source contact hole by heat treatment at 600 to 1100 ° C. to form a silicide film that becomes the source ohmic electrode 40. Finally, the unreacted metal film remaining on the interlayer insulating film 32 is removed by wet etching using nitric acid, sulfuric acid, hydrochloric acid, or a mixed solution thereof with hydrogen peroxide. Thereby, the source ohmic electrode 40 is formed at the bottom of the source contact hole. The heat treatment may be performed again after the metal film remaining on the interlayer insulating film 32 is removed. In this case, an ohmic contact with a lower contact resistance is formed by performing the heat treatment at a higher temperature than the previous heat treatment.

  If a gate contact hole has been formed in the previous step, an ohmic electrode made of silicide is also formed at the bottom of the gate contact hole. If the gate contact hole is not formed in the previous step, the gate contact hole to be filled later by the gate wiring 44 is formed by photolithography and etching.

  The source ohmic electrode 40 may be entirely made of the same intermetallic compound, and the portion connected to the p-type region and the portion connected to the n-type region are made of different intermetallic compounds suitable for each. It may be. By separately forming a portion connected to the p-type region and a portion connected to the n-type region in the source ohmic electrode 40, both reduction of contact resistance to the n-type region and the p-type region can be more effectively realized. This can be realized by performing patterning of the metal film for forming the silicide film by using photolithography.

  The source ohmic electrode 40 having a sufficiently low ohmic contact resistance with respect to the source region 12 is important for reducing the on-resistance of the MOSFET element. On the other hand, the source ohmic electrode 40 having a sufficiently low ohmic contact resistance with respect to the well contact region 25 fixes the source potential (earth potential) of the well region 20 and improves the forward characteristic of the body diode built in the MOSFET. And from the viewpoint of realizing low switching loss.

  In the process of forming the source ohmic electrode 40 on the surface of the drift layer 2, a silicide film to be the back ohmic electrode 42 is formed on the back surface of the semiconductor substrate 1 by the same method. The back surface ohmic electrode 42 is in ohmic contact with the back surface of the semiconductor substrate 1 and realizes good electrical connection between the drain electrode 43 to be formed thereafter and the semiconductor substrate 1.

  Subsequently, a predetermined metal film is formed by sputtering or vapor deposition, and patterned to form a source pad 41, a gate wiring 44, and a gate pad 45 on the interlayer insulating film 32. Examples of the metal film include Al, Ag, Cu, Ti, Ni, Mo, W, Ta, nitrides thereof, laminated films thereof, alloy films thereof, and the like. Further, a drain electrode 43 is formed by forming a metal film such as Ti, Ni, Ag, or Au on the back surface ohmic electrode 42 formed on the back surface of the semiconductor substrate 1. Through the above steps, the MOSFET having the configuration shown in FIGS. 3 and 4 is completed (the A1-A2 cross section is as shown in FIG. 11 or FIG. 12 depending on the formation position of the gate electrode 35).

  Although not shown, the formed MOSFET may be covered with a protective film such as a silicon nitride film or polyimide. This protective film has openings on the gate pad 45 and the source pad 41 so that the gate pad 45 and the source pad 41 can be connected to an external control circuit.

  In the MOSFET of the present embodiment, the impurity concentration of the portion of the source region 12 adjacent to the channel region is kept high. Therefore, an effect of reducing the connection resistance at the boundary between the channel region and the source region 12 is also obtained. Further, since the impurity concentration of the source region 12 adjacent to the channel region is high, more carriers can be supplied to the MOS interface, and the effect of reducing channel resistance can be obtained.

  In the configuration shown in FIGS. 3 and 4, the source constriction 15 is not formed immediately below the gate insulating film 30. That is, the gate insulating film 30 is formed on the source region 12 having a high impurity concentration. Therefore, when the gate insulating film 30 is formed by thermal oxidation, the gate insulating film 30 on the source region 12 becomes thicker than other regions due to accelerated oxidation. Thereby, the capacitance (Cgs) between the gate and the source is reduced, and the effect that the switching loss is reduced is obtained.

<Embodiment 2>
17 and 18 are schematic top views of unit cells of the silicon carbide MOSFET according to the second embodiment. FIG. 17 shows an example of a square unit cell, and FIG. 18 shows an example of a comb cell. FIG. 19 is a diagram showing a cross-sectional configuration of the half unit cell of the MOSFET, and FIG. 19 corresponds to the B1-B2 cross section of FIG. 17 or FIG. The structure of the A1-A2 cross section is the same as FIG.

  In the MOSFET of the second embodiment, the source constriction portion 15 which is a part of the source region 12 of the MOSFET of the first embodiment is replaced with a source bridge portion 16 having a first conductivity type impurity distribution different from that of the source region 12. Is. That is, in the unit cell of the present embodiment, the source region 12 is divided into a plurality (two in this case) from the well contact region 25 to the channel region, and two adjacent source regions 12 are separated from each other. It is configured to be partially connected by a source cross-linking portion 16 that cross-links between the two. The number, position, and shape of the source bridging portion 16 may be the same as those of the source constriction portion 15 of the first embodiment.

  Therefore, the inner source region 12, the source bridge portion 16, and the outer source region 12 are connected in series between the well contact region 25 and the channel region. Accordingly, the source bridging portion 16 becomes a path through which current flows.

  The source bridge portion 16 shown in FIG. 19 is formed in the upper layer portion of the drift layer 2 (upper layer portion of the well region 20) by ion implantation. That is, the source bridge portion 16 in FIG. 19 is formed by ion-implanting the first conductivity type impurity into the drift layer 2 using an implantation mask different from the ion implantation step for forming the source region 12.

  The source bridge portion 16 preferably has a lower impurity concentration of the first conductivity type than the source region 12. In other words, it is preferable that the impurity concentration of the first conductivity type of the source bridge portion 16 is smaller than that of the source constriction portion 15 of the first embodiment. As a result, the effect of increasing the resistance of the source bridge portion 16 due to heat generation when a large current is generated and the effect of narrowing the current path of the source bridge portion 16 due to the parasitic JFET effect are more significant than in the case of the source constriction portion 15. become. As a result, the effect of improving the short-circuit tolerance can be made higher than that of the first embodiment.

  20 and 21 are diagrams showing modifications of the MOSFET according to the second embodiment. 20 is a top view of the unit cell, and FIG. 21 is a cross-sectional view taken along line A1-A2 of FIG. A cross section taken along line B1-B2 of FIG. 20 is the same as FIG. In this modification, the region where the source bridge portion 16 and the source region 12 are in contact with each other is enlarged. That is, a part of the source bridge portion 16 extends along the boundary between the source region 12 and the well region 20, and the four source bridge portions 16 are connected to each other.

  FIG. 22 is a cross-sectional view showing another modification of the MOSFET according to the second embodiment. In FIG. 22, the source bridge portion 16 is constituted by a conductive layer made of a semiconductor material or a ceramic material formed on the surface of the drift layer 2. The source bridge portion 16 is formed across the two source regions 12 and the well region 20 therebetween so as to bridge two adjacent source regions 12. Examples of the material of the source bridging portion 16 include polycrystalline silicon, single crystal silicon carbide (epitaxial silicon carbide), or a ceramic material having a high resistance increasing effect at a high temperature (preferably 300 ° C. or higher).

  In the source bridge portion 16 of FIG. 22, a semiconductor material or a ceramic material is formed on the drift layer 2 in a step before the gate insulating film 30 and the gate electrode 35 are formed, and photolithography and etching techniques are used. It can be formed by patterning it. Further, the source bridge portion 16 may be formed in a step after the gate insulating film 30 and the gate electrode 35 are formed. In that case, after patterning the gate electrode 35, the gate insulating film 30 in the region where the source bridge portion 16 is formed is removed to expose the upper surfaces of the source region 12 and the well region 20, and a semiconductor material or a ceramic material is formed in that portion. The source bridge portion 16 may be formed and covered with the interlayer insulating film 32.

  Also in the configuration of FIG. 22, the same effect as in the case of FIG. 19 is obtained. When the source bridge portion 16 is made of single crystal silicon carbide, a part of the source bridge portion 16 may cover the channel region as shown in FIGS. 23 and 24 (FIG. 23 shows a unit cell). FIG. 24 shows a B1-B2 cross section thereof). Thereby, a high-quality MOS interface made of single-crystal silicon carbide without ion implantation damage is formed on the channel region.

  As in the second embodiment, the source region 12 is divided into a plurality of parts and connected by the source bridge portion 16 formed in a process different from the source region 12, thereby obtaining the same effect as in the first embodiment. It is done. That is, in the temperature range during rated operation, the source bridge portion 16 has a low sheet resistance, thereby suppressing an increase in on-resistance. On the other hand, when a large current is generated due to a short circuit or the like, the source bridging portion 16 generates heat to have a high sheet resistance, and the on-resistance is increased to suppress overcurrent. In addition, when a large current is generated, an effective gate voltage is lowered due to a voltage drop generated in the source bridging portion 16, and the overcurrent is further suppressed. As a result, it is possible to extend the time until the device is destroyed, and the short circuit resistance is improved.

  In the present embodiment, two source regions 12 are formed. However, three or more source regions 12 may be formed. In that case, each of the three or more source regions 12 is partially connected by the source bridge portion 16. The source region 12 and the source bridge portion 16 are connected in series between the source ohmic electrode 40 and the channel region so that the source bridge portion 16 serves as a current path.

<Embodiment 3>
25 to 27 are diagrams showing a configuration of a unit cell of the silicon carbide MOSFET according to the third embodiment. FIG. 25 is a plan view of the unit cell, FIG. 26 is a cross-sectional view of the half unit cell that does not include the source constriction portion 15 (A1-A2 cross section in FIG. 25), and FIG. It is sectional drawing (B1-B2 cross section of FIG. 25) of the half unit cell of the part containing this.

  As shown in FIGS. 25 to 27, in the third embodiment, the source constriction 15 of the source region 12 extends to the source ohmic electrode 40. In FIG. 25, the well contact region 25 is divided by the source constriction portion 15. However, the well contact region 25 may be integrally formed without being divided.

  According to the present embodiment, the source constriction portion 15 is lengthened and the resistance of the source constriction portion 15 is increased without increasing the area of the unit cell (without increasing the pitch of the plurality of unit cells). Can do. In this case, the on-resistance during rated operation increases, but it is more effective if the short-circuit withstand capability must be increased by increasing the effect of increasing the on-resistance and reducing the effective gate voltage when a large current is generated. Is.

  The third embodiment can also be applied to the second embodiment. In other words, the source bridge portion 16 formed in a separate process from the source region 12 may be extended to the source ohmic electrode 40. In this case, the source bridge portion 16 connects between the source ohmic electrode 40 and the source region 12.

<Embodiment 4>
In the first to third embodiments, an example of a planar MOSFET has been described, but the present invention can also be applied to a trench MOSFET. FIG. 28 and FIG. 29 are diagrams showing a configuration example when the source constriction portion 15 of the first embodiment is provided in a trench type MOSFET. FIG. 28 is a cross-sectional view of a half unit cell in a portion not including the source constriction portion 15, and FIG. 29 is a cross-sectional view of a half unit cell in a portion including the source constriction portion 15.

  As shown in FIGS. 28 and 29, in the trench MOSFET, a trench penetrating the source region 12 and the well region 20 is formed in the drift layer 2, and a gate insulating film 30 and a gate electrode 35 are formed in the trench. A portion of the well region 20 exposed on the side wall of the trench becomes a channel region. In the example of FIGS. 28 and 29, the source constriction 15 is formed on the upper surface portion of the drift layer 2.

  30 and 31 are diagrams showing another configuration example when the source constriction portion 15 of the first embodiment is provided in a trench MOSFET. 30 is a cross-sectional view of a half unit cell in a portion not including the source constriction portion 15, and FIG. 31 is a cross-sectional view of a half unit cell in a portion including the source constriction portion 15. In the example of FIGS. 30 and 31, the source constriction 15 is formed in the inner wall portion of the trench.

  Here, an example in which the source constriction portion 15 of the first embodiment is provided in a trench type MOSFET has been shown, but the source bridge portion 16 of the second embodiment may be applied. That is, in the configuration of FIGS. 28 to 31, the source bridge portion 16 formed in a process different from the source region 12 may be provided instead of the source constriction portion 15. The third embodiment may be applied to extend the source constriction portion 15 or the source bridge portion 16 to the source ohmic electrode 40.

  Although the vertical MOSFETs have been described in the first to third embodiments, the present invention can also be applied to a lateral MOSFET, for example, a RESURF (REduced SURface Field) structure MOSFET.

<Embodiment 5>
FIG. 32 is a plan view showing a configuration of a unit cell of the silicon carbide MOSFET according to the fifth embodiment.

  In the MOSFET of the first embodiment, only one source constriction 15 is formed in the current path of the shortest continuous distance from the source ohmic electrode 40 through the source region 12 to the channel of the silicon carbide MOSFET. In the MOSFET of the fifth embodiment, a plurality of source confinement portions 15 are formed in series in the current path of the shortest continuous distance from the source ohmic electrode 40 through the source region 12 to the channel of the silicon carbide MOSFET. Since other points are the same as those of the first embodiment, detailed description thereof is omitted.

  In the unit cell shown in FIG. 32, the well region 20 is formed so as to make a round with the source constriction 15 left in the inside and outside of the source region 12 outside the source ohmic electrode 40. Here, the inner source constriction 15 near the source ohmic electrode 40 is provided at the corner, and the outer source constriction 15 near the channel region is formed near the center of the side.

  Thus, the silicon carbide MOSFET of the present embodiment can increase the number of heat generation points by providing a plurality of source constriction portions 15 in series in the current path, and an excessive current flows during a short circuit or the like. When this occurs, heat generation due to current confinement in the source constriction portion 15 and increase in resistance due to this can be increased. Therefore, the short circuit tolerance can be further improved.

  Further, as shown in FIG. 32, the current constriction 15 is shifted on the current path so that the positions thereof are not aligned linearly, thereby extending the current path from the source ohmic electrode 40 to the source region 12. can do. With such an arrangement, the heat generation due to the current confinement in the source confinement portion 15 when an excessive current flows and the effect of increasing the resistance due to this heat generation become more significant, and the short-circuit resistance can be further improved.

  The arrangement of the well region 20 in the source region 12 may be another arrangement. For example, FIG. 33 is a schematic top view of a unit cell showing an example thereof. In the unit cell of FIG. 33, unlike the unit cell of FIG. 32, the inner source constriction 15 near the source ohmic electrode 40 is provided near the center of the side, and the outer source constriction 15 near the channel region is formed at the corner. doing.

  As described above, the position and the number of the source constriction portions 15 are not limited to those shown in FIGS. 32 and 33, but can be assumed to be various, but preferably, the positions are point-symmetric with respect to the center of the unit cell. It is desirable to provide the source constriction portion 15 at the point that the current distribution and the heat generation distribution are leveled, and the increase in the heat generation distribution due to the current imbalance and the resulting element degradation can be reduced.

  Even if the unit cell is a comb cell, a plurality of source confinement portions 15 are connected in series in the shortest continuous current path from the source ohmic electrode 40 through the source region 12 to the channel of the silicon carbide MOSFET. If it is formed, the same effect is obtained.

  Note that the source constriction portion 15 in the present embodiment may be read as the source bridging portion 16 described in the second embodiment.

<Embodiment 6>
FIG. 34 shows a cross-sectional configuration of the half unit cell of the silicon carbide MOSFET according to the sixth embodiment.

  In the MOSFET of the first embodiment, the current is confined by forming the well region 20 between the source regions 12. However, in the MOSFET of the sixth embodiment, the first region of the source region 12 is used instead of the well region 20. By providing a second conductivity type back-injection region 28 formed by implanting a second conductivity type impurity ion having an impurity concentration of one conductivity type or more in the source region 12, a current blocking region is formed to confine the current. ing. Since other points are the same as those of the first embodiment, detailed description thereof is omitted.

  The repetitive implantation region 28 is formed by implanting a second conductivity type impurity deeper than the source region 12 into a corresponding portion using a resist patterned by photolithography before forming the gate insulating film 30 as a mask. That is, after the step of FIG. 13, the source region 12 is formed without providing the source constriction portion 15, and then the back injection region 28 (current blocking region) is formed in a desired region. Aluminum or boron is suitable as the impurity, but a rare gas element such as Ar may be used for the purpose of making the back-injection region 28 semi-insulating. Further, the ion implantation for forming the implantation implantation region 28 may be performed simultaneously with the formation of the well contact region 25. In this case, the repetitive implantation region 28 can be formed without increasing the number of implantation masks.

  According to the MOSFET of the present embodiment, the second conductivity type (p type) repetitive implantation region 28 is formed in the depth region in which the first conductivity type (n type) source region 12 is formed. As a result, the resistance of the current path from the source ohmic electrode 40 through the source region 12 to the channel of the silicon carbide MOSFET can be increased.

  By doing so, since the impurity concentration of the well region 20 and the repetitive implantation region 28 can be controlled independently, the current concentration effect on the source constriction 15 is enhanced without greatly affecting the characteristics of the MOSFET, and a large current Short circuit withstand capability can be increased by increasing resistance during current flow.

  FIG. 35 is a diagram showing a cross-sectional configuration of a half unit cell of a modified example of the silicon carbide MOSFET according to the sixth embodiment. In order to confine the current, a current blocking region may be formed by providing an etching region 50 in the source region 12 as in the MOSFET of FIG. Providing the etching region 50 deeper than the source region 12 in the source region 12 can also narrow the current. Note that the resistance of the current path can also be changed by changing the depth of the etching region 50.

  Note that the source constriction portion 15 in the present embodiment may also be read as the source bridging portion 16 described in the second embodiment.

  In the above description, silicon carbide MOSFET is shown as an example of the semiconductor element to which the present invention is applied. However, the material of the semiconductor element may be other than silicon carbide, and the semiconductor element may be other than MOSFET. As elements other than the MOFET to which the present invention is applied, there are, for example, a JFET having a structure not using a gate insulating film, and an IGBT having a structure in which the conductivity type of the semiconductor substrate 1 is changed to the second conductivity type.

  In the IGBT, the source region 12 is an “emitter region”, the well region 20 is a “base region”, and the semiconductor substrate 1 is a “collector region”. Since the emitter resistance can be increased by providing a high-resistance constriction or bridge in the emitter region (source region), the current gain in the parasitic transistor including the emitter region, the base region, and the drift layer is reduced. As a result, it is possible to prevent latch-up caused by the operation of the IGBT parasitic thyristor.

  Note that the effects obtained from the structure of the semiconductor device described in any of Embodiments 1 to 6 can be obtained in the same manner even if formed by other manufacturing methods as long as the structure is provided.

  Further, within the scope of the invention, the present invention can be freely combined with each other, or can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 drift layer, 5 chip | tip, 7 active area | region, 11 JFET area | region, 12 source area | region, 15 source | sauce constriction part, 16 source bridge | crosslinking part, 20 well area | region, 25 well contact area | region, 28 strike back injection area | region, 30 gate insulation Film, 32 interlayer insulating film, 35 gate electrode, 40 source ohmic electrode, 41 source pad, 42 backside ohmic electrode, 43 drain electrode, 44 gate wiring, 45 gate pad, 50 etching region.

Claims (21)

A semiconductor substrate;
A first conductivity type drift layer formed on the semiconductor substrate;
A second conductivity type well region formed in a surface layer portion of the drift layer;
A source region of a first conductivity type formed in the well region and partially narrowed in plan view;
A gate insulating film formed on the drift layer;
A gate electrode formed on the gate insulating film and extending above the well region and the source region;
A channel region which is a portion below the gate electrode in the well region;
A semiconductor element including a source electrode connected to the source region;
A source constriction portion, which is a constricted portion of the source region, is provided apart from the channel region and the source electrode , and an insulating film is formed on the source constriction portion. A featured semiconductor device. 2. The semiconductor device according to claim 1, wherein the source constriction portion of the source region has the same first conductivity type impurity concentration distribution as other portions of the source region. 3. The semiconductor device according to claim 1, wherein a plurality of the source constriction portions are provided and are respectively arranged at positions that are point-symmetric with respect to the center of the unit cell of the semiconductor element. The unit cell of the semiconductor element is a comb cell,
3. The semiconductor device according to claim 1, wherein a plurality of the source constriction portions are provided, and the closer to the source electrode, the narrower the width. The unit cell of the semiconductor element is a comb cell,
5. The semiconductor device according to claim 1, wherein a plurality of the source constriction portions are provided, and a length closer to the source electrode is formed with a larger length. 6. . The semiconductor device according to claim 1, wherein the source constriction portion is disposed at a position not covered with the gate electrode. 7. The semiconductor according to claim 1, wherein a plurality of the source constriction portions are formed in series in a continuous path from the source electrode through the source region to the channel region. apparatus. The said source confinement part is formed by providing the area | region which interrupts | blocks an electric current by inject | pouring a 2nd conductivity type impurity or a noble gas element into the said source region. Semiconductor device. 8. The semiconductor device according to claim 1, wherein the source constriction part is formed by providing a region for blocking current by partially etching the source region. 9. A semiconductor substrate;
A first conductivity type drift layer formed on the semiconductor substrate;
A second conductivity type well region formed in a surface layer portion of the drift layer;
A plurality of first conductivity type source regions formed in the well region;
A source bridge portion of a first conductivity type that partially bridges between the plurality of source regions;
A gate insulating film formed on the drift layer;
A gate electrode formed on the gate insulating film and extending above the well region and the source region;
A channel region which is a portion below the gate electrode in the well region;
A semiconductor element including a source electrode connected to the source region;
The plurality of source regions and the source bridge portion are connected in series between the source electrode and the channel region ,
The source bridge portion is separated from the channel region and the source electrode, and an insulating film is formed on the source bridge portion.
Semiconductor device comprising a call. The semiconductor device according to claim 10, wherein an impurity concentration of the first conductivity type in the source bridge portion is smaller than an impurity concentration of the first conductivity type in the source region. 12. The semiconductor device according to claim 10, wherein a plurality of the source bridging portions are provided and are arranged at positions that are point-symmetric with respect to the center of the unit cell of the semiconductor element. The unit cell of the semiconductor element is a comb cell,
The semiconductor device according to claim 10, wherein a plurality of the source bridging portions are provided, and the closer to the source electrode, the narrower the width. The unit cell of the semiconductor element is a comb cell,
14. The semiconductor device according to claim 10, wherein a plurality of the source bridging portions are provided, and the source bridge portion is formed to have a larger length as it is closer to the source electrode. . The semiconductor device according to claim 10, wherein the source bridge portion is disposed at a position not covered with the gate electrode. The semiconductor device according to any one of claims 10 to 15, wherein the source bridge portion is a first conductivity type single crystal silicon carbide. The semiconductor device according to claim 16, wherein the source bridge portion extends to the channel region. 18. The semiconductor according to claim 10, wherein a plurality of the source bridge portions are formed in series in a continuous path from the source electrode through the source region to the channel region. apparatus. The said source bridge | crosslinking part is formed by providing the area | region which interrupts | blocks an electric current by inject | pouring a 2nd conductivity type impurity or a noble gas element into the said source | sauce area | region. Semiconductor device. The semiconductor device according to any one of claims 10 to 18, wherein the source bridge portion is formed by providing a region for blocking current by partially etching the source region. The semiconductor device according to any one of claims 1 to 20, wherein the semiconductor substrate is formed of silicon carbide.

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