JP5907097B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Examples of semiconductor devices used in the field of power electronics include MOSFETs (Metal-Oxide Semiconductor Field Transistors) and IGBTs (Insulated Gate Bipolar Transistors), which are field effect transistors of metal / insulator / semiconductor junctions. The device is required to have high reliability from the viewpoint of application to power electronics.

  For example, when an inductive load or a resistive load is operated by applying a MOSFET to an inverter circuit or the like, a load short circuit such as an arm short circuit occurs, and a high voltage that is a power supply voltage is applied to the drain electrode of the MOSFET in an on state. Is applied, a large current flows through the MOSFET. In this state, a drain current several times to several tens of times the rated current is induced in the MOSFET, and if the device does not have an appropriate protection function, the MOSFET element is destroyed.

  In order to prevent this, there is a method in which an excessive drain current (overcurrent) is detected before device breakdown occurs, and an off signal is input to the gate electrode accordingly to cut off the drain current. In this case, the MOSFET element is required to have robustness that does not cause destruction of the element over a period of time from the occurrence of a load short circuit or the like until an overcurrent is detected and the off signal is input to the gate electrode. That is, as one of the high reliability of the semiconductor device, it is strongly desired that the short circuit tolerance is excellent. The short-circuit withstand capability is substantially defined by the time required from the occurrence of a short-circuit until the device is destroyed, and the fact that the short-circuit withstand capability is excellent means that the time until breakdown is long.

  In order to improve the short-circuit withstand capability, the emitter layer (corresponding to the source region of the MOSFET) serving as the IGBT on-current path has a high-resistance emitter layer (high-resistance region) and a low-resistance emitter layer (low-resistance region). A method is disclosed in which an emitter electrode (corresponding to a source electrode of a MOSFET) and a channel region (corresponding to a well region of a MOSFET) are alternately arranged so as to be connected in parallel with each other (for example, a patent) Reference 1). According to this conventional configuration, when a load short circuit occurs, a voltage drop due to an electron current flowing through the high resistance region of the emitter layer increases, and the saturation current value decreases, so that the short circuit tolerance is improved.

JP 2003-332577 A

  When an excessive voltage is applied to the semiconductor device such as when a load is short-circuited, the semiconductor device generates heat due to the overcurrent. Therefore, in order to improve the short-circuit tolerance, it is desired to increase the on-resistance at high temperature and reduce the overcurrent. In the conventional structure, after a second conductivity type impurity is implanted into the first conductivity type drift layer to form a well region (channel region), the first conductivity type impurity is introduced into the second conductivity type well region. The conductivity type is inverted by implantation, and a source region (emitter layer) of the first conductivity type is formed. Since the well region needs to be formed deeper than the source region, the energy during implantation also increases. For this reason, impurities are implanted into the source region with high energy when the well region is formed, but many implantation defects are generated in the region implanted with high energy. In a region where there are many injection defects, the temperature dependence of the mobility of conductive carriers is small. That is, if the source resistance is increased in order to increase the on-resistance at a high temperature, the source resistance at room temperature also increases, resulting in a problem that the on-resistance of the element during the on-operation increases.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device that improves short-circuit resistance and suppresses an increase in on-resistance near the element operating temperature. .

A semiconductor device according to the present invention includes a semiconductor substrate, a first conductivity type drift layer formed on the semiconductor substrate, a second conductivity type first well region formed in a surface layer portion of the drift layer, and a drift layer A first conductivity type well gap region adjacent to the first well region, and a second conductivity type second well region formed adjacent to the well gap region in the surface layer portion of the drift layer. A first conductivity type source resistance control region provided in the well gap region, and a first conductive layer formed continuously from a part of the surface layer part of the first well region to a part of the surface layer part of the well gap region. conductive source contact region and a second well region a source extension region of the first conductivity type formed continuously from a portion of the surface portion to a part of the surface layer of the well gap region, source extension A channel region formed in a second well region located between the region and the drift layer, a gate electrode provided above the second well region and the source extension region via a gate insulating film, and a source contact And a source electrode connected to the region .

  According to the present invention, since the source resistance control region is provided in the first conductivity type well gap region, high energy injection of the second conductivity type is not performed in the source resistance control region. Can be suppressed. Therefore, the temperature dependence of the mobility of conduction carriers in the source resistance control region is larger than that in the case where the source resistance control region is formed in the well region. Even if the resistance is increased, the source resistance at the operating temperature can be reduced as compared with the case where the source resistance control region is formed in the well region, so that it is possible to suppress an increase in on-resistance while improving the short-circuit resistance. .

3 is a top view schematically showing a configuration when the semiconductor device according to the first embodiment is a silicon carbide MOSFET. FIG. FIG. 3 is a cross sectional view showing a half unit cell of silicon carbide MOSFET according to the first embodiment. 1 is a schematic top view showing a planar structure of a unit cell of silicon carbide MOSFET according to a first embodiment when viewed from the top. 3 is a top view schematically showing a surface layer portion of a drift layer of a unit cell in silicon carbide MOSFET according to Embodiment 1. FIG. In the half unit cell of silicon carbide MOSFET which concerns on Embodiment 1, it is sectional drawing which shows the manufacturing method until 2nd well area | region formation. It is a figure which shows the calculation result of the drain current-drain voltage characteristic with respect to the well gap area | region length of the silicon carbide MOSFET which concerns on Embodiment 1. FIG. FIG. 10 is a cross sectional view showing the manufacturing method until formation of a third well region, in the half unit cell of silicon carbide MOSFET according to the first embodiment. FIG. 11 is a cross sectional view showing another manufacturing method until formation of a third well region in the half unit cell of silicon carbide MOSFET according to the first embodiment. FIG. 11 is a cross sectional view showing still another manufacturing method until formation of a third well region in the half unit cell of silicon carbide MOSFET according to the first embodiment. FIG. 5 is a cross sectional view showing a method for forming the source contact region and the source extension region in the half unit cell of the silicon carbide MOSFET according to the first embodiment. In silicon carbide MOSFET which concerns on Embodiment 1, it is a schematic diagram explaining the temperature dependence of the carrier mobility when there are many injection defects and there are few. 6 is a schematic diagram for explaining a short circuit current waveform of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a top view in which four unit cells are arranged in order to show a manufacturing method until formation of a source resistance control region of silicon carbide MOSFET according to the first embodiment. In the half unit cell of silicon carbide MOSFET which concerns on Embodiment 1, it is sectional drawing for demonstrating the manufacturing method until 1st well contact region formation. FIG. 6 is a top view in which four unit cells are arranged for explaining a manufacturing method up to formation of a first well contact region in the silicon carbide MOSFET according to the first embodiment. FIG. 10 is a top view in which four unit cells are arranged for explaining another manufacturing method until formation of a first well contact region in the silicon carbide MOSFET according to the first embodiment. FIG. 4 is a top view in which four unit cells are arranged to explain a manufacturing method up to formation of the first well contact region when the third well region also serves as the second well contact region in the silicon carbide MOSFET according to the first embodiment. is there. In the half unit cell of silicon carbide MOSFET which concerns on Embodiment 1, it is sectional drawing for demonstrating the manufacturing method until the current control area | region 14 formation. FIG. 10 is a cross sectional view for illustrating a modification of current control region 14 in the half unit cell of silicon carbide MOSFET according to the first embodiment. It is sectional drawing of a half unit cell for demonstrating to completion in the manufacturing method of the silicon carbide MOSFET which concerns on Embodiment 1. FIG. It is a schematic diagram for demonstrating the temperature dependence of the mobility of the conduction carrier of the silicon carbide MOSFET which concerns on Embodiment 1. FIG. In the half unit cell of silicon carbide MOSFET which concerns on Embodiment 1, it is sectional drawing which shows the modification of a 2nd well contact area | region. In the half unit cell of the silicon carbide MOSFET which concerns on Embodiment 1, it is sectional drawing for demonstrating formation of a 2nd well area | region among the manufacturing methods of the modification of the well area | region 20. FIG. In the half unit cell of the silicon carbide MOSFET which concerns on Embodiment 1, it is sectional drawing for demonstrating formation of a 1st well area | region among the manufacturing methods of the modification of the well area | region 20. FIG. In the top view which has arrange | positioned four unit cells of the silicon carbide MOSFET which concerns on Embodiment 1, it is a figure for showing the manufacturing method of the modification of the well area | region 20. FIG. FIG. 6 is a cross sectional view showing a modified example of well region 20 in the half unit cell of silicon carbide MOSFET according to the first embodiment. FIG. 6 is a cross sectional view showing a half unit cell for illustrating a manufacturing method in the case where a fourth well region is formed in silicon carbide MOSFET according to the first embodiment. FIG. 6 is a cross sectional view showing a half unit cell when a fourth well region is formed in the silicon carbide MOSFET according to the first embodiment. FIG. 6 is a cross sectional view showing a half unit cell of a silicon carbide MOSFET according to a second embodiment.

Embodiment 1 FIG.
FIG. 1 is a top view schematically showing a configuration when the semiconductor device according to the first embodiment is a silicon carbide MOSFET. In the present embodiment, a silicon carbide MOSFET that is a semiconductor element is referred to as a semiconductor device in a narrow sense. For example, a semiconductor element, a freewheel diode that is connected in antiparallel to the semiconductor element, and the semiconductor element A semiconductor device such as an inverter module or a power module in which a control circuit that applies a voltage to the gate electrode is mounted on a lead frame and integrally sealed is included in the semiconductor device in a broad sense.

  In this embodiment, a silicon carbide MOSFET is used as the semiconductor element. However, a semiconductor other than silicon carbide may be used, and an IGBT or a JFET (Junction Field Effect Transistor) other than the MOSFET may be used.

  In FIG. 1, a source pad 41, a gate wiring 44, and a gate pad 45, which are source electrodes, are formed on the outermost surface of the silicon carbide MOSFET. The gate wiring 44 is connected to the gate pad 45 and is formed so as to surround the source pad 41. The gate pad 45 is disposed near the center of one side of the gate wiring 44.

  In FIG. 1, an area surrounded by a dotted line is an active area 7, and a plurality of unit cells shown in FIG. 2 are arranged in parallel. In FIG. 1, the outside of active region 7 is termination region 8, and the silicon carbide MOSFET in the present embodiment is formed of active region 7 shown in FIG. 1 and termination region 8 outside active region 7.

  A gate electrode 35 (described in FIG. 2) of each unit cell is connected to the gate pad 45 through a gate wiring 44 and applied to the gate pad 45 from an external control circuit (not shown). The gate voltage is applied to the gate electrode 35 of each unit cell. Similarly, the source region 41 of each unit cell (described with reference to FIG. 2) is connected to the source pad 41.

  In an actual product of a semiconductor device, each electrode for a temperature sensor and a current sensor for operating an external protection circuit is often disposed on a semiconductor element such as a silicon carbide MOSFET. Since the relation with this embodiment is weak, it is omitted in this embodiment.

  The layout of the gate pad 45, the gate wiring 44, and the source pad 41 is not limited to that shown in FIG. Their shape, number, etc., vary widely depending on the product. The presence / absence of electrodes for the temperature sensor and the current sensor and the layout of each electrode do not significantly affect the effect of this embodiment, and may be arbitrary.

  Since the feature of the present embodiment is the active region 7, the termination region 8 may have any structure, and the active region 7 will be described below.

  FIG. 2 is a cross-sectional view showing the right half of one unit cell arranged in active region 7 of silicon carbide MOSFET which is the semiconductor device in the present embodiment. That is, FIG. 2 is a cross-sectional view of the half unit cell, and a cross-sectional view of FIG.

  As shown in FIG. 2, the half unit cell of the silicon carbide MOSFET includes a semiconductor substrate 1 made of silicon carbide of the first conductivity type, and a first conductivity type drift layer 2 (carbonized carbon) epitaxially grown on the surface thereof. And an epitaxial substrate made of a silicon semiconductor layer. A drain electrode 43 is formed on the back surface side of the semiconductor substrate 1 via a back surface ohmic electrode 42 that is in ohmic contact with the semiconductor substrate 1.

  In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

  In FIG. 2, the second conductivity type first well region 20 a and the second conductivity type second well region 20 b are arranged apart from each other in the surface layer portion of the drift layer 2. In FIG. 2, a region surrounded by a one-dot chain line is a well gap region 15b sandwiched between the first well region 20a and the second well region 20b. The well gap region 15b is of the first conductivity type and is connected to the drift layer 2 of the first conductivity type without passing through the second conductivity type region.

  A first well contact region 25a of the second conductivity type is provided in the surface layer portion of the first well region 20a. Further, adjacent to the first well contact region 25a, a source contact region 12a of the first conductivity type is provided in the surface layer portion of the first well region 20a. The first well region 20a is formed up to a part of the surface layer portion of the well gap region 15b. That is, the source contact region 12a is continuously formed from a part of the surface layer part of the first well region 20a to a part of the surface layer part of the well gap region 15b.

  On the other hand, a source extension region 12b of the first conductivity type is selectively formed in the surface layer portion of the second well region 20b. The second well region 20b is formed up to a part of the surface layer portion of the well gap region 15b. That is, the source extension region 12b is continuously formed from a part of the surface layer part of the second well region 20b to a part of the surface layer part of the well gap region 15b.

  A source resistance control region 15a of the first conductivity type exists between the source extension region 12b and the source contact region 12a. The source resistance control region 15a is provided in the surface layer portion of the well gap region 15b, which is a separation region between the first well region 20a and the second well region 20b. In FIG. 2, the source resistance control region 15a is a region surrounded by a dotted line.

  In FIG. 2, the source resistance control region 15a and the source contact region 12a are adjacent to each other, and the source resistance control region 15a and the source extension region 12b are adjacent to each other.

  That is, the first conductivity type source region 12 of the silicon carbide MOSFET in the present embodiment is composed of at least three regions of a source contact region 12a, a source resistance control region 15a, and a source extension region 12b.

  In addition, the second conductivity type well region 20 of the silicon carbide MOSFET in the present embodiment is composed of a first well region 20a and a second well region 20b.

  The portion of the second well region 20b between the source extension region 12b and the JFET region 11 is directly under the gate insulating film 30, and is a region where a MOS channel is formed when the silicon carbide MOSFET is turned on. Called an area. In FIG. 2, a JFET region 11 between the second well regions 20b of adjacent unit cells is a region surrounded by a two-dot chain line.

  In the present embodiment, the current control region 14 is formed by increasing the impurity concentration of the first conductivity type below the JFET region 11 and a part of the second well region 20b.

  The current control region 14 is a region in which the JFET region 11 between the second well regions 20b of adjacent unit cells and the impurity concentration of the first conductivity type therebelow are increased.

  As shown in FIG. 2, the second well region 20b and the first conductivity type current control region 14 are adjacent to each other, but may not be adjacent to each other. The current control region 14 has an effect of reducing the resistance (on-resistance) when the silicon carbide MOSFET is turned on, but the region smaller than the current control region 14 shown in FIG. However, the effect of reducing the on-resistance can be obtained. Needless to say, it may be larger than the region shown in FIG.

  As shown in FIG. 2, a gate insulating film 30 is provided on the surfaces of the source contact region 12a, the source extension region 12b, the source resistance control region 15a, and the JFET region 11.

  Furthermore, the gate electrode 35 extends across the source extension region 12b, the second well region 20b (MOS channel region), and the JFET region 11 via the gate insulating film 30. Of the three regions constituting the source region 12 shown in FIG. 2, the source extension region 12 b forms a MOS structure together with the gate insulating film 30 and the gate electrode 35.

  A source ohmic electrode 40a that is in ohmic contact with the source contact region 25a and the first well contact region 25a is formed on the surface of a part of the source contact region 12a and the first well contact region 25a. The source ohmic electrode 40a is connected to a source pad 41 provided on the surface of the interlayer insulating film 32 through a source contact hole of the interlayer insulating film 32 formed so as to cover the gate electrode 35 (not shown). .

  The first well contact region 25a penetrates the source contact region 12a and reaches the first well region 20a, and electrically connects the source pad 41 and the first well region 20a.

  FIG. 3 is a schematic top view showing a planar structure of the unit cell as viewed from above. In FIG. 3, the source pad 41, the interlayer insulating film 32, the gate electrode 35, and the gate insulating film 30 are omitted.

  FIG. 4 is a top schematic view schematically showing a planar structure of the surface layer portion of the drift layer 2 of the unit cell as viewed from above. In FIG. 4, the source region 12, the first well contact region 25a, and the second well contact region 25b formed in the surface layer portion of the drift layer 2 are omitted.

  A plurality of unit cells shown in FIG. 3 are formed in a lattice pattern in the active region 7 of FIG.

  As shown in FIG. 4, the second well region 20b is formed around the first well region 20a via the first conductivity type well gap region 15b in a top view. The second conductivity type second well region 20b is connected to each other by the second conductivity type second well region 20b of the adjacent unit cell and the second conductivity type third well region 20c.

  In the present embodiment, third well regions 20 are arranged at four corners of a square unit cell, and the second well regions 20b of adjacent unit cells are connected to each other. That is, the plurality of third well regions 20c of the second conductivity type are selectively formed in the unit cell.

  In the adjacent unit cell, the region where the third well region 20c between the second well regions 20b is not formed is the JFET region 11 described above.

  In the present embodiment, the current control region 14 having the first conductivity type impurity concentration higher than the impurity concentration of the drift layer 2 is formed in the JFET region 11, but even if the current control region 14 is not formed. good. That is, the first conductivity type impurity concentration of the JFET region 11 may be the same as the first conductivity type impurity concentration of the drift layer 2.

  Although not shown in FIGS. 3 and 4, the source region 12 is formed in the surface layer portion of the well region 20 as described in FIG. 2. The source resistance control region 15a is formed so as to surround the outside of the source contact region 12a formed in the surface layer portion of the first well region 20a in a top view.

  Further, the source extension region 12b formed in the surface layer portion of the second well region 20b is formed so as to surround the outside of the source resistance control region 15a in a top view. When viewed from above, the source extension region 12b is the outermost peripheral portion of the source region 12, and is adjacent to the MOS channel region of the second well region 20b.

  The source resistance control region 15a is arranged in the surface layer portion of the well gap region 15b shown in FIG. That is, the source resistance control region 15a is not directly ion-implanted with the second conductivity type impurity forming the first well region 20a and the second well region 20b.

  Note that the source resistance control region 15 a preferably has the same first conductivity type impurity concentration as the drift layer 2. That is, the source resistance control region 15a is preferably formed as a region sandwiched between the source extension region 12 and the source contact region 12a in the well gap region 15b without the ion implantation of the drift layer 2.

  The source resistance control region 15a has a lower impurity concentration of the first conductivity type than the source contact region 12a.

  The impurity concentration of the first conductivity type in each of the source contact region 12a and the source extension region 12b may be approximately the same. As will be described later, the source contact region 12a and the source extension region 12b can be formed at the same time, and in this case, both have the same impurity distribution.

  Alternatively, the impurity concentration of the first conductivity type in the source extension region 12b may be lower than the impurity concentration of the first conductivity type in the source contact region 12a.

  Also, below the source resistance control region 15a is a well gap region 15b sandwiched between the first well region 20a and the second well region 20b, and the first conductivity type well gap region 15b has the second conductivity type. It is connected to the drift layer 2 of the first conductivity type without going through the mold region.

  As shown by a region surrounded by a one-dotted line in FIG. 3, a second conductivity type second well contact region 25b is formed inside the third well region 20c. The second well contact region 25b electrically connects the source pad 41 and the third well region 20c via a well ohmic electrode 40b provided on the surface thereof.

  As described with reference to FIGS. 2 and 3, the source pad 41 is connected to the source contact region 12a and is connected to the first well region 20a via the first well contact region 25a and the second well contact region 25b. It is electrically connected to the third well region 20c.

  The first well region 20a, the second well region 20b, and the third well region 20c can be formed at the same time. In this case, they have the same impurity concentration distribution.

  As described in FIG. 2, the gate electrode 35 is covered with the interlayer insulating film 32, and the source pad 41 and the gate wiring 44 are formed thereon. Therefore, in the interlayer insulating film 32, a source contact for connecting the first well contact region 25a and the second well contact region 25b to the source pad 41 in addition to the source contact hole for connecting the source pad 41 to the source contact region 12a. A hole (not shown) and a gate contact hole (not shown) for connecting the gate wiring 44 to the gate electrode 35 are formed.

  A dotted line shown in the source contact region 12a in FIG. 3 indicates a region (source contact hole) where the source ohmic electrode 40a for connecting the source pad 41 to the unit cell is formed. The source ohmic electrode 40a is in contact with the source contact region 12a and the first well contact region 25a.

  In the present embodiment, the source ohmic electrode 40a is in contact with the source contact region 12a, and the outer periphery of the source contact region 12a is arranged as the source resistance control region 15a and the outer periphery thereof is arranged as the source extension region 12b as shown in FIG. Thus, the source contact region 12a, the source resistance control region 15a, and the source extension region 12b are connected in series between the source ohmic electrode 40a and the MOS channel region of the second well region 20b.

  Since the source contact region 12a has a high impurity concentration of the first conductivity type, ohmic contact with low contact resistance can be realized with the ohmic electrode 40a.

  In the cross-sectional view of FIG. 2, when the silicon carbide MOSFET is turned on or when the load is short-circuited, the drain current (on-current) flowing from the drain electrode 43 into the drift layer 2 is the surface portion (surface layer) of the JFET region 11 and the second well region 20b. A path extending from the source ohmic electrode 40a to the source pad 41 through the source extension region 12b, the source resistance control region 15a, and the source contact region 12a.

  In each unit cell shown in FIG. 3, the source resistance control region 15a has a uniform length (current path length) in the direction in which the on-current flows, that is, in the direction from the source extension region 12b to the source contact region 12a in a top view. Formed to be.

  That is, in FIG. 3, the length of the source resistance control region 15a between the source extension region 12b and the source contact region 12a is formed to be constant.

  Therefore, as shown in FIG. 3, each corner portion of the outer periphery of the source contact region 12a (the inner periphery of the source resistance control region 15a) and the inner periphery of the source extension region 12b (the outer periphery of the source resistance control region 15a) has a round shape. Thus, the center of outer peripheral radius of curvature of the source contact region 12a and the center of inner peripheral radius of curvature of the source extension region 12b are the same.

  As described above, when the length of the source resistance control region 15a is made uniform in the unit cell, variation in the source resistance in the unit cell can be suppressed. As a result, when an excessive current such as a short-circuit current is instantaneously applied, the current can be prevented from concentrating on a specific portion, and the reliability of the semiconductor device can be improved.

  Here, it is desirable that the length of the source resistance control region 15a in the unit cell is uniform, but an error may occur in terms of process accuracy. However, even if an error of about 10% occurs, the above effect can be obtained.

  In FIG. 3, the outer peripheral corner portion of the source extension region 12b is a right angle, but is rounded, and the center of curvature radius is the center of the outer periphery radius of curvature of the source contact region 12a and the inner periphery of the radius of curvature of the source extension region 12b. May be the same.

  In this case, the parasitic resistance of the source extension region 12b is made uniform in the unit cell. For this reason, an effect of suppressing variation in source resistance in the unit cell can be obtained. As a result, when an excessive current such as a short-circuit current is instantaneously applied, the current can be prevented from concentrating on a specific portion, and the reliability of the semiconductor device can be improved.

  Further, the outer peripheral corner portion of the second well region 20b is also a right angle in FIG. 3, but is rounded, and the center of curvature radius is the center of the outer periphery radius of curvature of the source contact region 12a and the center of the inner periphery radius of curvature of the source extension region 12b. May be the same. In this case, since the MOS channel length is made uniform, the MOS channel resistance is made uniform, variation in element characteristics and current distribution is suppressed, a more reliable unit cell structure is obtained, and the reliability of the semiconductor device is further increased. be able to.

  Note that the outer peripheral radius of curvature of the source contact region 12a and the inner peripheral radius of curvature of the source extension region 12b may be the same, and the respective centers of curvature radius may be different. In this case, the length of the source resistance control region 15a in the corner portion is larger than the length in the straight portion. Since the resistance of the source resistance control region 15a at a high temperature such as a short circuit is particularly high in the corner portion, the short circuit current mainly flows in a straight portion other than the corner portion. That is, an effect of suppressing element deterioration due to current concentration at the corner can be obtained.

  3 and 4 show a unit cell having a square planar structure, the unit cell may have any shape, for example, a hexagon, an octagon, or a circle.

  Further, the silicon carbide MOSFET may not have a cell structure composed of a plurality of unit cells, and may have a general comb-shaped structure. The comb structure is easy to form, but the on-resistance of the element is relatively high because the MOS channel width density is lower than that of the cell structure.

  Next, a method for manufacturing the semiconductor device (silicon carbide MOSFET) according to the first embodiment will be described.

  FIG. 5 is a cross-sectional view showing a manufacturing method until formation of well region 20 in the half unit cell of the silicon carbide MOSFET according to the present embodiment. In FIG. 5, first, a semiconductor substrate 1 made of first conductivity type silicon carbide is prepared. In addition to silicon carbide, silicon or another wide band gap semiconductor having a larger band gap than silicon may be used for the semiconductor substrate 1. Examples of wide band gap semiconductors include gallium nitride, aluminum nitride, and diamond in addition to silicon carbide.

  The plane orientation of the semiconductor substrate 1 may be arbitrary. For example, the surface vertical direction may be inclined by 8 ° or less with respect to the c-axis direction, or may not be inclined. The thickness of the semiconductor substrate 1 may be arbitrary, for example, about 350 μm or about 100 μm.

Subsequently, the first conductivity type drift layer 2 is formed on the semiconductor substrate 1 by epitaxial crystal growth. The impurity concentration of the first conductivity type of the drift layer 2 is about 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and the thickness is ³ μm to 200 μm.

  The drift layer 2 may not be formed directly on the semiconductor substrate 1 and may be formed via a buffer layer.

  The impurity concentration distribution of the first conductivity type of the drift layer 2 is desirably constant in the thickness direction, but may not be constant, for example, the impurity concentration may be intentionally lowered near the surface. In that case, the electric field generated in the gate insulating film 30 when a reverse bias is applied to the MOSFET element is reduced, the reliability of the element is improved, and the threshold voltage of the element can be set high.

  The impurity concentration of the first conductivity type in the surface layer portion of the drift layer 2 defines the impurity concentration of the first conductivity type in the source resistance control region 15a. For this reason, when the impurity concentration of the first conductivity type in the surface layer portion of the drift layer 2 is lowered, as will be described later, an increase in resistance of the source resistance control region 15a is expected particularly at a high temperature, which can contribute to an improvement in short-circuit resistance.

  Next, as shown in FIG. 5, for example, a photoresist or a silicon oxide film is patterned by photolithography to form a first implantation mask 100a and a second implantation mask 100b. The first implantation mask 100a and the second implantation mask 100b may be formed simultaneously by a single photolithography process.

  Then, the first well region 20a and the second well region 20b are formed by selective ion implantation of the second conductivity type impurities using the first implantation mask 100a and the second 100b. The arrows in FIG. 5 indicate the direction in which implanted ions are implanted.

  The first implantation mask 100a defines the length of the well gap region 15b in the top view by the width in the sectional view, and the second implantation mask 100b has the width of the JFET region 11 in the width in the sectional view. Defines the length in top view.

  The widths of the first implantation mask 100a and the second implantation mask 100b may be the same or different.

  First implantation mask 100a is preferably wide enough to prevent leakage current from flowing through well gap region 15b when a reverse bias is applied to silicon carbide MOSFET.

  That is, when a reverse bias is applied to an element that is a silicon carbide MOSFET, the well gap region 15b is blocked by a depletion layer extending from the first well region 20a and the second well region 20b, and breakdown voltage deterioration due to punch-through does not occur. Thus, it is necessary to determine the length of the well gap region 15b and the impurity concentration of the first conductivity type.

  Therefore, it is desirable that the width of the first implantation mask 100a is uniform within the unit cell, that is, has a round shape at the corner portion of the unit cell, for example, as shown by the length in a top view of FIG. Moreover, the width | variety should just exist in the range of 0.1-5 micrometers, More preferably, it is in the range of 0.1-3 micrometers.

  Even if the width of the first implantation mask 100a is within the above range, the implanted ions diffuse not only in the implantation direction but also in the lateral direction. That is, the implanted ions also enter under the first implantation mask 100a. As a result, the length of the well gap region 15 viewed from the top view may be 0.01 to 1 μm at the narrowest position in the depth direction. The length of the well gap region 15b defines the length of the source resistance control region 15a.

  In FIG. 6, when the first well region 20a and the second well region 20b are formed simultaneously, the drain current-drain voltage characteristics of the MOSFET element with respect to the well gap region length when the implanted ions are Al and the implantation energy is 700 keV. The calculation result of is shown.

  It can be seen that by reducing the well gap region length, the device breakdown voltage is increased, and by reducing the well gap region length to 0.05 μm or less, an element breakdown voltage exceeding 900 V can be obtained. As shown in FIG. 6, a high breakdown voltage of 1.3 kV is obtained when the well gap region length is 0.02 μm.

  In particular, the thermal diffusion coefficient of impurities in silicon carbide is much smaller than the thermal diffusion coefficient of impurities in silicon conventionally used for power devices. Therefore, even by high-temperature heat treatment such as activation annealing, redistribution of implanted impurities due to thermal diffusion hardly occurs, and the distribution during implantation is almost maintained. Accordingly, the desired length of the well gap region 15b can be obtained by controlling the width of the first implantation mask 100a.

  That is, a desired length of the well gap region 15b can be obtained by controlling the width of the first implantation mask 100a. If the desired length of the well gap region 15b is obtained, the length of the source resistance control region 15b formed inside the well gap region 15b can be easily controlled to a desired value. If the desired length of the source resistance control region 15b can be obtained, the increase amount of the source resistance can be set to a desired value, so that the increase amount of the source resistance by the source resistance control region 15b can be easily controlled.

  Further, it is desirable that the first implantation mask 100a and the second implantation mask 100b are nearly perpendicular without forming a taper at their end faces. By implanting impurity ions into the implantation mask having such a shape from the vertical direction, the first implantation mask 100a and the second implantation mask 100b are formed in a region deeper than the region on the surface side of the drift layer 2. Thus, an impurity distribution (for example, FIG. 5) can be obtained in which the length of the well gap region 15b is narrower.

  With such a shape, the effect of suppressing breakdown voltage degradation due to punch-through in the well gap region 15b is particularly great.

The depths of the bottoms of the first well region 20a and the second well region 20b need to be set so as not to exceed the bottom of the drift layer 2, for example, about 0.2 μm to 2.0 μm. Further, the maximum value of the second conductivity type impurity concentration in the first well region 20a and the second well region 20b exceeds the value of the first conductivity type impurity concentration of the drift layer 2, for example, 1 × 10 ¹⁵ cm ^−3. It is set within a range of ˜1 × 10 ¹⁹ cm ⁻³ .

  At the time of ion implantation, the semiconductor substrate 1 is preferably heated at 100 to 800 ° C., but may not be heated. In addition, as an impurity (dopant) to be ion-implanted, nitrogen or phosphorus is preferable as an n-type impurity, and aluminum or boron is preferable as a p-type impurity.

  FIG. 7 is a top view showing a manufacturing method up to formation of third well region 20c in which four unit cells are arranged in silicon carbide MOSFET according to the present embodiment. In FIG. 7, for example, a photoresist or a silicon oxide film is patterned by photolithography and a mask for implantation is formed, and a third well region 20c is formed by selective ion implantation of a second conductivity type impurity.

  As shown in FIG. 7, the third well region 20c is disposed so as to include the apex of the adjacent second well region 20b in a top view, and is furthest from the adjacent second well region 20b in the direction of the JFET region 11. It arrange | positions so that the location in a position may also be included. That is, the third well region 20c is arranged at a point where four unit cells are connected, and connects the four second well regions 20b.

  The depth of the bottom of the third well region 20c needs to be set so as not to exceed the bottom of the drift layer 2, for example, about 0.2 μm to 2.0 μm. That is, the bottom of the third well region 20 c is located in the drift layer 2.

The maximum impurity concentration of the second conductivity type in the third well region 20c exceeds the impurity concentration of the first conductivity type of the drift layer 2, and is, for example, 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . Set within range.

  The third well region 20c may have a uniform impurity concentration distribution in the depth direction, or a concentration distribution having a peak at the surface or a region deeper than the surface.

  The depth of the bottom of the third well region 20c may be shallow, the same depth, or deep with respect to the bottom surfaces of the first well region 20a and the second well region 20b.

  By forming it shallower than the first well region 20a and the second well region 20b, the effect of spreading the drain current at the end of the JFET region 11 can be easily obtained during the on-operation of the element, leading to a reduction in on-resistance.

  Furthermore, as shown in FIG. 8, the third well region 20c may be formed simultaneously with the first well region 20a and the second well region 20b.

  Further, as shown in FIG. 9, it may be formed simultaneously with the first well contact region 25a. In the case of FIG. 9, the third well region 20c may also serve as the second well contact region 25b. That is, in the case of FIG. 9, the step of merely forming the second well region 25b in the third well region 20c can be omitted.

  According to these methods, since it is not necessary to form an implantation mask only for forming the third well region 20c, the manufacturing cost of the element can be reduced.

  Subsequently, as shown in FIG. 10, a third implantation mask 100c is formed by patterning, for example, a photoresist or a silicon oxide film by photolithography and a first ion implantation of a first conductivity type impurity is performed. A source contact region 12a of one conductivity type and a source extension region 12b of the first conductivity type are formed. The arrows in FIG. 10 indicate the direction in which impurity ions are implanted.

  The source contact region 12a and the source extension region 12b are formed so as to protrude from the first well region 20a and the second well region 20b, respectively, so as to be connected to the well gap region 15b. By being formed in this manner, the source region 12 does not include the second conductivity type region, and is configured only by the first conductivity type region.

  In FIG. 10, a region surrounded by a dotted line is a first conductivity type source resistance control region 15a formed between the source contact region 12a and the source extension region 12b. The first conductivity type source resistance control region 15 a existing in the well gap region 15 b has the impurity concentration of the drift layer 2.

  The source resistance control region 15a is located in the well gap region 15b in which the second conductivity type (p-type) high energy injection for forming the well region 20 is not performed. The source resistance control region 15a has the same impurity concentration as the drift layer 2 and is not implanted with a first conductivity type (n-type) ion for forming the source contact region 12a. Therefore, the same high-quality crystallinity as that of the drift layer 2 in which no injection defects are generated is maintained.

  Here, the source resistance control region 15a is provided to increase the resistance (source resistance) of the source region 12 to reduce the overcurrent at the time of short circuit and to improve the short circuit tolerance.

  However, if the resistance of the entire source region 12 is increased, the source resistance becomes excessively large, which increases the conduction loss during the rated on operation, which is not preferable.

  Further, when the impurity concentration of the first conductivity type in the source region 12 is substantially uniform in the lateral direction as in the conventional MOSFET element, increasing the source resistance reduces the impurity concentration of the entire source region 12. Become. In this case, the contact resistance between the source region 12 and the source pad 41 (source ohmic electrode) increases, and the element loss further increases.

  In the present embodiment, the source ohmic electrode 40a connected to the source pad 41 contacts the low resistance source contact region 12a and does not contact the high resistance source resistance control region 15a. Therefore, the contact resistance between the ohmic electrode 40 and the source region 12 is kept low. Therefore, the source resistance can be designed so that the saturation current is reduced while suppressing an excessive increase in the on-resistance.

  In the present embodiment, only the partial region of the source region 12 is used as the source resistance control region 15a, and the above effect can be obtained by increasing the source resistance. However, even if the increase is caused by a part of the source region 12, an increase in the source resistance directly leads to an increase in the on-resistance, which is not desirable from the viewpoint of reducing the loss of the MOSFET element. That is, there is a trade-off relationship between the increase in the on-resistance and the improvement in the short-circuit resistance due to the source resistance control region 15a.

  Here, the on-resistance becomes a problem at a temperature at which the MOSFET element operates, and it is desirable that the source resistance of the source region 12 at the operating temperature at the on-time is as small as possible. On the other hand, regarding the short-circuit tolerance, since the temperature is higher than the operating temperature due to heat generation due to overcurrent at the time of short-circuit, it is desirable that the source resistance at a high temperature is large from the viewpoint of short-circuit tolerance.

  The present inventors have confirmed that when the element is short-circuited, it reaches 1000 K immediately before the destruction due to heat generation (Joule heat) due to a high drain current.

  That is, in order to improve the trade-off relationship, it is desirable that the source resistance of the source region 12 is low at the operating temperature of the element, such as from room temperature to around 500 K, and the source resistance increases as the operating temperature becomes higher. That is, source resistance characteristics with high temperature sensitivity and high temperature sensitivity are desired.

  FIG. 11 shows the temperature dependence of the mobility of conductive carriers. In FIG. 11, the solid line indicates the characteristics when there are few implantation defects, and the dotted line indicates the characteristics when there are many implantation defects. Here, the impurity concentration is constant. The higher the mobility, the lower the resistivity, that is, the lower the resistance of the source resistance control region 15a.

  Here, the scattering mechanism involved in the mobility of conductive carriers includes scattering of ionized impurities and lattice scattering. Among these, scattering of ionized impurities is dominant due to temperature dependence at a temperature lower than near room temperature, and lattice scattering is dominant due to temperature dependence at a temperature higher than near room temperature. In any case, since scattering increases as the temperature increases, the mobility of conductive carriers decreases as the temperature increases.

  When ion implantation is performed, implantation defects such as traps are generated in the crystal. A trap formed at an energy level of a certain depth captures a conduction carrier, so that an effective concentration of the conduction carrier contributing to conduction is reduced and mobility is lowered. The conduction carriers trapped in the trap are emitted from the trap and contribute to conduction when energy larger than the energy level of the trap is obtained, that is, when the temperature rises to a certain temperature. That is, when there are many injection defects, the mobility is reduced compared to the case where there are few injection defects because the conduction carriers are trapped in the trap that is the injection defect on the low temperature side. Because it contributes, it approaches the mobility when there are few implantation defects.

  When the energy of ion implantation is large, that is, more implantation defects are generated in a region where ion implantation with high energy is performed. For this reason, more carriers are trapped in the trap, and the degree of mobility decrease at a low temperature is large.

  In FIG. 11, it can be said that the greater the slope of the tangent of the curve, the greater the temperature dependence of the mobility. As can be seen from FIG. 11, the higher the temperature, the smaller the mobility, but the smaller the number of implantation defects, the larger the slope of the tangent line and the greater the temperature dependence of the mobility. In particular, it can be seen that the temperature dependence varies greatly depending on the amount of implantation defects, from a region lower than room temperature to a certain high temperature.

  That is, the smaller the number of ion implantation defects, the higher the resistance at room temperature and the higher the temperature sensitivity. That is, when resistance increase at high temperature is required, if the temperature sensitivity of the resistance is high, the source resistance at high temperature can be increased without increasing the source resistance at room temperature. Therefore, the time until the temperature rises to about 1000 K can be extended, and the short circuit resistance can be greatly improved.

  FIG. 12 is a schematic diagram for explaining a short-circuit current waveform of a semiconductor device using this embodiment. In FIG. 12, when this embodiment is used, a solid line when there are few implantation defects is shown, and a dotted line when there are many implantation defects is shown as a comparative example.

  The energy that can be tolerated until the device breaks down (short-circuit energy) is considered to be substantially determined by the physical properties of the semiconductor, so it is considered that the energy is not substantially dependent on the amount of implanted defects and is almost the same. Here, the short-circuit energy is given by the time integral value of the short-circuit current until breakdown. That is, the short-circuit energy, which is the time integral value of the short-circuit current until the breakdown of the solid line and the dotted line in FIG.

  In FIG. 12, the peak of the short-circuit current before the element breaks is larger on the solid line than on the broken line. The peak of the short circuit current appears relatively early due to a short circuit. Therefore, the element temperature in the region where the short-circuit current peak appears is almost the same as the operating temperature, regardless of whether there are many injection defects or not. When the number of injection defects is small at such a temperature, the peak of the short-circuit current is larger than when there are many injection defects, indicating that the source resistance of the element is small near the operating temperature. That is, when there are few injection | pouring defects, it shows that the mobility of an electron is large.

  When the peak of the short-circuit current passes, the short-circuit current decreases, which indicates that the electron mobility decreases because the temperature of the element increases due to the short-circuit current. The temperature of the element rises rapidly from around the peak of the short-circuit current, and reaches about 1000K when the element breaks down. Here, the reduction rate of the short circuit current is larger in the solid line than in the broken line. This is because the temperature sensitivity of mobility is high when the number of injection defects is small, and the source resistance increases as the temperature of the element increases.

  In FIG. 12, the short-circuit energy, which is the time integral of the short-circuit current, does not depend on the amount of injection defects, as described above. Therefore, the mobility, that is, the case where there are many injection defects with low temperature sensitivity of the source resistance is first. Destroy. As the short-circuit tolerance, it is desired that the time until destruction is long, so it can be said that it is preferable that the number of implantation defects is small.

  Thus, since the resistance of the source resistance control region 15a in this embodiment has a large temperature dependency, a large source resistance at about 1000K such as during a short circuit is suppressed while suppressing a large increase in on-resistance at an actual operating temperature of about 400K. (For example, when the temperature is proportional to the power of 2.7, the resistance at 1000 K is 28 times the resistance at room temperature). That is, the on-resistance at room temperature can be lowered to obtain the same or better short-circuit withstand capability as compared with the source resistance control region 15a having a small temperature dependency, which is a case where there are many injection defects. . In other words, according to the present embodiment, an element exhibiting a low on-resistance characteristic at the time of an on-operation while realizing a better short-circuit withstand capability as compared with the conventional case in which the source resistance control region 15a is formed in the well region 20. Can be realized.

  In the present embodiment, the source resistance control region 15a is not affected by the implantation of impurity ions of the first conductivity type or the second conductivity type, and therefore maintains high quality crystallinity free from implantation defects. ing. Therefore, in order to function as a region where the temperature sensitivity of the resistor is high, an increase in the on-resistance at room temperature is suppressed, and the short-circuit withstand capability of the MOSFET element is improved.

  In FIG. 10, the bottom depths of the source contact region 12a and the source extension region 12b are set so as not to exceed the bottom depths of the first well region 20a and the second well region 20b.

In addition, the first conductivity type impurity concentration of the source contact region 12a and the source extension region 12b exceeds the second conductivity type impurity concentration of the first well region 20a and the second well region 20b, respectively. For example, the maximum impurity concentration is set to about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

  FIG. 13 is a top view showing a manufacturing method up to formation of source resistance control region 15a in which four unit cells are arranged in silicon carbide MOSFET according to the present embodiment.

  As shown in the top view of FIG. 13, the source resistance control region 15a defined by the arrangement of the source contact region 12a and the source extension region 12b is formed so as to maintain a certain length in the well gap region 15b. Since the length is constant, the resistance distribution of the source resistance control region 15a is uniform, the current distribution flowing through the element is uniformed, and the temperature distribution due to heat generation when a large current is applied such as during a short circuit is also uniformed. Thus, an element with high reliability can be obtained.

The length L _N0 of the source resistance control region 15a shown in FIG. 10 may be 0.1 to 4 μm, more preferably 0.1 to 1 μm.

When the source length _{L NO} resistor control area 15a is too long, the impurity concentration of the source resistance control region 15a is due to the low impurity concentration than the source contact region 12a, the on-resistance of the MOSFET device increases.

Further, in order to increase the L _NO, it is necessary to increase the length of the well gap region 15b, thereby the withstand voltage is lowered by the punch-through as described above with too long a length of the well gap region 15b .

On the other hand, if _LNO is shortened, the effect of improving the short-circuit resistance is reduced.

Therefore, L _N0 is preferably in the range of 0.1 to 4 μm.

  FIG. 14 is a cross-sectional view for describing the manufacturing method up to the formation of first well contact region 25a in the half unit cell of the silicon carbide MOSFET according to the present embodiment.

  FIG. 15 is a top view showing a manufacturing method up to formation of first well contact region 25a in which four unit cells are arranged in silicon carbide MOSFET according to the present embodiment.

  Further, FIG. 16 is a top view showing another manufacturing method up to the formation of first well contact region 25a in which four unit cells are arranged in silicon carbide MOSFET according to the present embodiment. FIG. 16 is a top view showing the manufacturing method up to the formation of the first well contact region 25a when the second well region 20b and the third well region 20c are simultaneously formed by ion implantation, as in FIG.

  As shown in FIGS. 14, 15 and 16, in order to obtain a good connection between the first well region 20a and the third well region 20c and the source pad 41 described later, the first well region 20a and the third well A first well contact region 25a and a second well contact region 25b having a second conductivity type impurity concentration higher than that of the region 20c are formed by selective ion implantation.

  This ion implantation is desirably performed at a temperature at which the semiconductor substrate 1 is 150 ° C. or higher. By doing so, it is possible to form the first well contact region 25a and the second well contact region 25b that have low sheet resistance and realize low contact resistance.

As shown in FIG. 14, the first well contact region 25a penetrates the source contact region 12a and is formed so that the bottom reaches the first well region 20a. In addition, the second conductivity type impurity concentration of the first well contact region 25a exceeds the second conductivity type impurity concentration of the first well region 20a. For example, the maximum impurity concentration is 1 × 10 ¹⁹ cm ⁻³ to. It is set to about 1 × 10 ²¹ cm ⁻³ .

The second well contact region 25b is formed so as to reach the third well region 20c (not shown), and the second conductivity type impurity concentration of the second well contact region 25b is the same as that of the third well region 20c. For example, the maximum impurity concentration is set to about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

  FIG. 17 is a top view showing the manufacturing method up to the formation of the first well contact region 25a when the third well region 20c also serves as the second well contact region 25b as shown in FIG. In the case of FIG. 17, the conditions of the depth and impurity concentration of the second well contact region 25b are not limited to those described above, and the depth of the second well contact region 25b is equal to the depth of the third well region 20c. The impurity concentration of the region 25b is equal to the impurity concentration of the third well region 20c.

  In FIGS. 15, 16 and 17, it goes without saying that the first well contact region 25a and the second well contact region 25b may be formed at the same time. Reduction is possible, and cost can be reduced.

  FIG. 18 is a cross-sectional view for illustrating the manufacturing method until formation of current control region 14 in the half unit cell of the silicon carbide MOSFET according to the present embodiment. As shown in FIG. 18, in order to reduce the resistance in the JFET region 11, ion implantation of the first conductivity type impurity is performed in the JFET region 11 using the fourth implantation mask 100 d, thereby A control region 14 is formed.

  Although the current control region 14 is formed in the present embodiment, it may not be formed.

  FIG. 19 is a cross sectional view for illustrating a modification of current control region 14 in the half unit cell of silicon carbide MOSFET according to the present embodiment. The current control region 14 may be formed at least in the JFET region 11, but as shown in FIG. 19, it is deeper than the second well region 20b and further includes a part of the lower surface of the second well region 20b. It is more preferable that it is formed. In this case, the spreading resistance spreading from the JFET region 11 to the drift layer 2 can be reduced.

  On the other hand, the current control region 14 need not be formed in the region on the surface side in the JFET region 11. By doing in this way, the electric field applied to the gate insulating film 30 can be reduced, and the element excellent in reliability can be obtained.

  That is, when the current control region 14 is formed, it may be formed in the entire JFET region 11 or only in a region deeper than the surface. Further, it may be formed in a part below the second well region 20b.

  Even if it is formed only in the region on the surface side of the JFET region 11, a certain effect for reducing the on-resistance can be obtained.

  Further, as shown in FIG. 19, the current control region 14 may extend laterally so as to include the well gap region 15b. In this case, the first conductivity type high concentration layer 16 having a higher concentration than the first conductivity type impurity concentration of the drift layer 2 is formed on the entire surface of the active region 7 or the entire surface of the active region 7 and the termination region 8. The high-concentration layer 16 provided in a part of them, that is, the lower portion of the JFET region 11 and the second well region 20b becomes the current control region 14.

  The high concentration layer 16 may be formed by epitaxial growth. That is, when epitaxial growth of the drift layer 2 is performed, the impurity concentration of the first conductivity type is made higher than that of the drift layer 2 to form the high concentration layer 16. By doing so, the impurity concentration of the JFET region 11 can be made higher than that of the drift layer 2, and the on-resistance of the element can be reduced by reducing the resistance and spreading resistance of the JFET region 11. On the other hand, an injection defect does not occur in the well gap region 15b, and a good short-circuit tolerance that is an effect of the present embodiment can be obtained.

  When epitaxially growing the high concentration layer 16, the impurity concentration of the first conductivity type in only a part of the high concentration layer 16 may be higher than the impurity concentration of the drift layer 2. That is, the high concentration layer 16 may be provided with a concentration distribution.

  For example, the first conductivity type impurity concentration in a region deep from the surface of the high concentration layer 16, that is, a region in contact with the drift layer 2, may be increased and the concentration on the surface side may be decreased. In such a case, since the impurity concentration of the region on the surface side of the JFET region 11 can be lowered, the electric field applied to the gate oxide film 30 is reduced, and the region deeper than the surface is made high to increase the resistance of the JFET region 11. Therefore, the effect of reducing the on-resistance can be obtained. Furthermore, since the impurity concentration of the source resistance control region 15a in the well gap region 15b is low, the source resistance increases, and the effect of improving the short-circuit resistance is greater than increasing the impurity concentration of the entire well gap region 15b.

  When the structure of FIG. 19 is formed by epitaxial growth, the high concentration layer 16 is formed before the source contact region 12a and the source extension region 20b are formed in FIG.

  In the high concentration layer 16 region, the impurity concentration of the region having the highest impurity concentration of the first conductivity type is lower than the impurity concentration of the source contact region 12a. Since the source resistance control region 15a is located in the high concentration layer 16, the impurity concentration of the source resistance control region 15a can be made smaller than that of the source contact region 12a.

  19, when the impurity concentration on the surface side of the high concentration layer 16 is made higher than the impurity concentration of the drift layer 2, the impurity concentration of the source resistance control region 15a is higher than in the case of FIG. Become. Therefore, although the temperature sensitivity for improving the short-circuit tolerance of the source resistance control region 15a is deteriorated, the deterioration degree of the temperature sensitivity is reduced by forming the high concentration layer 16 by epitaxial growth. That is, when the impurity concentration is increased, the mobility is decreased and the temperature sensitivity is deteriorated due to the influence of scattering by ionized impurities on the lower temperature side than the vicinity of room temperature. However, when the MOSFET element is on, in addition to the resistance reduction effect of the JFET region 11, the resistance reduction effect of the source resistance control region 15 a is also obtained, so the on-resistance reduction effect is great.

  As described above, if the concentration distribution is provided in the high concentration layer 16 so that only a region deeper than the surface has a high concentration and the concentration on the surface side where the source resistance control region 15a is formed is reduced, the resistance of the JFET region 11 is reduced. An effect and an effect of suppressing an increase in the applied electric field of the gate oxide film 30 are obtained.

  As shown in FIG. 19, the high concentration layer 16 may be formed deeper than the first well region 20a and the second well region 20b, or may be formed shallower. When formed deeply, the effect of reducing the spreading resistance of the JFET region 11 is great. When forming shallowly, it can also form by ion implantation instead of epitaxial growth.

  When the high-concentration layer 16 of FIG. 19 is formed shallower than the first well region 20a and the second well region 20b by ion implantation, the well gap region 15b is also ion-implanted. That is, ion implantation is also performed on the source resistance control region 15a. Therefore, implantation defects due to ion implantation also occur in the source resistance control region 15a and the temperature sensitivity of the source resistance deteriorates. However, since the implantation is shallower than the first well region 20a and the second well region 20b, the high concentration layer 16 Is lower than the implantation energy of the first well region 20a and the second well region 20b. When the implantation energy is low, the number of implantation defects generated is small, and the deterioration of the temperature sensitivity of the source resistance is small.

  That is, the source resistance control region 15a is formed in the high-concentration layer 16 subjected to ion implantation with a lower implantation energy than in the well region 20 subjected to ion implantation with a higher implantation energy as in the prior art. Since the amount of implantation defects in the source resistance control region 15a is small, the effect of improving the short-circuit resistance can be obtained.

Here, the influence of the length (L _N0 ) of the source resistance control region 15a, the length of the well gap 15b, and the impurity concentration of the high concentration layer 16 on the breakdown voltage will be described.

  The off-breakdown voltage of the element, that is, the avalanche breakdown voltage, depends on the respective electric fields in the second conductivity type first well region 20a, second well region 20b, third well region 20c, and termination region 8, and the gate oxide film 30 in the MOS structure. It is determined by the electric field.

These electric fields are affected by the respective impurity concentrations, their concentration distributions, the JFET length (the width of the JFET region 11), and the length (L _N0 ) of the source resistance control region 15a.

  In order to improve the avalanche resistance, which is one of the indicators of the critical characteristics of the semiconductor element, it is important to suppress the breakdown of the gate insulating film 30 due to the avalanche current, so the gate insulating film 30 is formed on the surface. It is more preferable that an avalanche current does not flow in the second well region 20b and the third well region 20c having the MOS structure.

Therefore, the source resistance control is performed so that the electric field value of the region becomes higher than the electric field value of the other region so that the avalanche breakdown occurs between the first well region 20a and the drift layer 2 (or the high concentration layer 16). The length of the region 15a (L _N0 ), the length of the well gap 15b, and the impurity concentration of the high concentration layer 16 may be determined.

  After all the ion implantation processes in FIG. 14, FIG. 18, or FIG. 19 are completed, a heat treatment for electrically activating the impurities implanted into the drift layer 2 is performed. This heat treatment is preferably performed in an inert gas atmosphere such as argon or nitrogen or in a vacuum at a temperature of 1500 ° C. to 2200 ° C. for a time of 0.5 minutes to 60 minutes.

  In this heat treatment, the surface of the drift layer 2 is covered with a film made of carbon, or the surface of the drift layer 2, the back surface of the semiconductor substrate 1, and the end faces of the semiconductor substrate 1 and the drift layer 2 are made of carbon. You may go in the state covered with. Thereby, it is possible to prevent the surface of the drift layer 2 from being roughened by etching due to a reaction with residual moisture or residual oxygen in the apparatus during the heat treatment.

  FIG. 20 is a cross-sectional view of the half unit cell for explaining the completion of the silicon carbide MOSFET manufacturing method according to the present embodiment. In FIG. 20, first, a gate insulating film 30 made of, for example, a silicon oxide film is formed on the surface of the drift layer 2. Examples of the method for forming the gate insulating film 30 include a thermal oxidation method and a deposition method.

In addition, after a silicon oxide film is formed by a thermal oxidation method or a deposition method, a heat treatment in a nitriding oxide gas (NO, N ₂ O, etc.) atmosphere or an ammonia atmosphere, or a heat treatment in an inert gas (argon, etc.) atmosphere is performed. May be. According to the heat treatment in the nitriding gas atmosphere, a high-quality MOS interface having a low interface state density can be formed by nitrogen pileup and passivation effect on the MOS interface.

  Then, polycrystalline silicon or polycrystalline silicon carbide is deposited on the gate insulating film 30 by a CVD method, and patterning is performed by photolithography and etching to form the gate electrode 35.

  The polycrystalline silicon or polycrystalline silicon carbide used for the gate electrode 35 preferably contains phosphorus, boron, aluminum, or the like and has an n-type or p-type low sheet resistance. Phosphorus, boron, or aluminum contained in polycrystalline silicon or polycrystalline silicon carbide may be taken in during the film formation, or may be subjected to activation heat treatment by ion implantation after the film formation. Furthermore, the material of the gate electrode 35 may be a metal, an intermetallic compound, or a multilayer film thereof.

  Next, an interlayer insulating film 32 is formed on the drift layer 2 by a CVD method or the like. Then, a contact hole (source contact hole) for connecting the source pad 41 to the source contact region 12a, the first well contact region 25a, and the second well contact region 25b is formed in the interlayer insulating film 32 by, for example, dry etching. Form.

  Further, a contact hole (gate contact hole) for connecting the gate wiring 44 to the gate electrode 35 may be formed at the same time. Thereby, the process steps are simplified and the manufacturing cost can be reduced.

  Subsequently, a source ohmic electrode 40a and a well ohmic electrode 40b (not shown in FIG. 20 but shown in FIG. 3) are formed on the surface of the drift layer 2 exposed at the bottom of the source contact hole. The source ohmic electrode 40a realizes ohmic contact with the source contact region 12a and the first well contact region 25a. The well ohmic electrode 40b realizes ohmic contact with the second well contact region 25b.

  As a method of forming the source ohmic electrode 40a and the well ohmic electrode 40b, first, a metal film containing nickel as a main component is formed on the entire surface of the drift layer 2 including the inside of the source contact hole. Next, the source ohmic electrode 40a and the well ohmic electrode 40b are reacted with the source contact region 12a, the first well contact region 25a, and the second well contact region 25b of the drift layer 2 made of silicon carbide by heat treatment at 600 to 1100 ° C. A silicide film is formed. Thereafter, an unreacted metal film remaining on the interlayer insulating film 32 is removed by wet etching using nitric acid, sulfuric acid, hydrochloric acid, or a mixed solution thereof with hydrogen peroxide, or the like.

  After removing the metal film remaining on the interlayer insulating film 32, the heat treatment may be performed again. In this case, an ohmic contact with a lower contact resistance is formed by performing the heat treatment at a higher temperature than the previous heat treatment.

  If a gate contact hole is formed in the previous step, an ohmic contact with silicide is also formed at the bottom of the gate contact hole. If the gate contact hole is not formed in the previous step, the gate contact hole to be filled later by the gate wiring 44 is formed by photolithography and etching.

  The source ohmic electrode 40a and the well contact region 40b are formed at the same time, but the whole may be made of the same intermetallic compound, and the portion connected to the p-type region and the portion connected to the n-type region are It may consist of separate intermetallic compounds suitable for each.

  It is important for reducing the on-resistance of the MOSFET element that the source ohmic electrode 40a has a sufficiently low ohmic contact resistance with respect to the source contact region 12a of the first conductivity type.

  On the other hand, the source ohmic electrode 40a has a sufficiently low ohmic contact resistance with respect to the second conductivity type first well contact region 25a, and the well ohmic electrode 40b has a sufficiently low ohmic contact resistance with respect to the second well contact region 25b. This is preferable from the viewpoints of fixing the source potential (ground) of the well contact region 25a and the second well contact region 25b, improving the forward characteristics of the body diode built in the MOSFET, and realizing low switching loss.

  In the source ohmic electrode 40a and the well ohmic electrode 40b, by separately forming a portion connected to the p-type region and a portion connected to the n-type region, it is possible to more effectively reduce both the contact resistance to the n-type region and the p-type region. realizable. This can be realized by performing patterning of the metal film for forming the silicide film by using photolithography.

  By forming the second well contact region 25b and the well ohmic electrode 40b, the second well region 20b is electrically connected to the source pad 41 described later. By doing so, since the second well region 20b having the MOS channel region is fixed at the source potential, fluctuations in the threshold voltage of the element are suppressed, and a high electric field is applied when a reverse bias is applied to the element. By eliminating the region, an element having high reliability against a high electric field can be obtained.

  Further, in the process of forming the source ohmic electrode 40 a and the well ohmic electrode 40 b on the surface of the drift layer 2, a silicide film to be the back ohmic electrode 42 is formed on the back surface of the semiconductor substrate 1 by the same method. The ohmic electrode 42 is in ohmic contact with the back surface of the semiconductor substrate 1 and realizes a good electrical connection between the drain electrode 43 to be formed thereafter and the semiconductor substrate 1.

  Subsequently, a predetermined metal film is formed by sputtering or vapor deposition, and patterned to form a source pad 41, a gate wiring 44, and a gate pad 45 on the interlayer insulating film 32.

  As the metal film, Al, Ag, Cu, Ti, Ni, Mo, W, Ta, nitrides thereof, a laminated film thereof, or an alloy film thereof can be considered. Further, by forming a drain electrode 43 by forming a metal film such as Ti, Ni, Ag, or Au on the back surface ohmic electrode 42 formed on the back surface of the semiconductor substrate 1, the right half of the unit cell is shown in FIG. A silicon carbide MOSFET having a structure indicated by is completed.

  The surface of the silicon carbide MOSFET manufactured as shown in FIG. 20 may be covered with a protective film (not shown) such as a silicon nitride film or polyimide. This protective film has openings on the gate pad 45 and the source pad 41 so that the gate pad 45 and the source pad 41 can be connected to an external control circuit.

  According to the present embodiment, by increasing the source resistance of the source region 12 by the source resistance control region 15a, it is possible to lengthen the time until element destruction at the time of a short circuit, so that the effect of improving the short-circuit tolerance can be obtained.

  Further, in the present embodiment, since the second conductivity type high energy implantation for forming the well region 20 in the source resistance control region 15a is not performed, no implantation defect occurs. Impurities are not directly ion-implanted in the source resistance control region 15a in the present embodiment, and at most by lateral scattering of the first conductivity type impurities in the ion implantation for forming the source contact region 12a and the source extension region 12b. A very small amount is slightly infiltrated.

  In the source resistance control region 15a, there is no damage (or very little) to the semiconductor crystal due to direct implantation (or very little), and at most, a very small amount is slightly infiltrated by lateral scattering. While a layer having the same temperature sensitivity as the drift layer 2 is obtained, the robustness as a crystal against high current stress or thermal stress when an overcurrent such as a short circuit is applied is maintained, and the reliability is improved. A high element can be realized.

  That is, the temperature sensitivity of the source resistance is higher than that of the source resistance control region 15a. Therefore, it is possible to increase the effect of improving the short-circuit tolerance while suppressing an increase in the on-resistance at the operating temperature at the on-time.

  Furthermore, in the present embodiment, since the second conductivity type high energy injection for forming the well region 20 is not performed in the source resistance control region 15a, the first conductivity for forming the source resistance control region 15a is not performed. There is no need to perform mold injection (reverse injection). Therefore, since an injection defect does not occur, the temperature sensitivity of the resistance in the source resistance control region 15a is high, so that the effect of improving the short-circuit tolerance can be increased while suppressing an increase in the on-resistance at the operating temperature at the on time. .

  In the present embodiment, even if the first conductivity type implantation is performed in the source resistance control region 15a in the well gap region 15b, not only the inversion implantation is required, but also the impurity concentration from the source contact region 12a. The injection amount is relatively small. Therefore, in comparison with the case where reverse implantation is performed in the region where the second conductivity type for forming the well region 20 is implanted, the first conductivity type implantation is performed in the source resistance control region 15a in the present embodiment. Even if the impurity concentration of the source resistance control region 15a is made higher than the impurity concentration of the drift layer 2, the effect of the present embodiment is reduced if the implantation energy of the first conductivity type is smaller than the implantation energy of the well region 20. You can get a little.

  In addition, since the second conductivity type high energy implantation for forming the well region 20 is not performed in the source resistance control region 15a, the first conductivity type implantation (inversion implantation for forming the source resistance control region 15a) is performed. ) Is not necessary. Therefore, it is possible to easily form the source resistance control region 15a having an impurity concentration as small as that of the drift layer 2.

  Here, the mobility of conduction carriers (electrons or holes) in the source resistance control region 15a decreases as the temperature increases, and the source resistance increases as the temperature increases. Since the source resistance control region 15a has a lower impurity concentration of the first conductivity type than the source contact region 12a, it is known that the rate of increase in resistance at a high temperature is higher than those.

  FIG. 21 schematically shows the temperature dependence of the mobility of conductive carriers. In FIG. 21, the solid line indicates that the impurity concentration is low, and the dotted line indicates that the impurity concentration is high.

  As described with reference to FIG. 11, the temperature-dependent scattering mechanism of conduction carrier mobility includes ionized impurity scattering and lattice scattering. As a parameter affecting the temperature dependence of mobility, the impurity concentration is further increased. Can be given. As described above, scattering of ionized impurities is dominant due to temperature dependence at low temperatures. Here, when the impurity concentration is high, scattering of ionized impurities increases, so that the mobility at a low temperature decreases as shown in FIG.

  Although lattice scattering becomes dominant at high temperatures, lattice scattering itself does not depend on the impurity concentration. However, impurities such as donors and acceptors that have not released conductive carriers at low temperatures obtain thermal energy that is equal to or higher than the activation energy at high temperatures and release conductive carriers. If the impurity concentration is high, the concentration of conductive carriers emitted at a high temperature increases. The emitted conduction carrier contributes to conduction and thus has high mobility. Therefore, when the impurity concentration is high, the decrease in mobility at high temperatures is small, that is, the temperature dependence of mobility is small.

  The feature that the temperature dependence of the mobility varies depending on the impurity concentration becomes more significant as the activation energy of impurities such as donors and acceptors increases. In other words, at a low temperature at which lattice scattering becomes dominant, it has a large activation energy such that many conduction carriers are not emitted, and the higher the concentration of carriers not emitted at that temperature, the higher this characteristic. Becomes prominent. This is because more carriers are released at higher temperatures.

  In the wide band gap semiconductor such as silicon carbide, the activation energy of the donor and acceptor is large, and thus the above-mentioned feature appears remarkably. That is, in a wide band gap semiconductor such as silicon carbide, the temperature dependence of mobility as shown in FIG. 21 varies greatly depending on the impurity concentration.

According to the experiments by the present inventors, the resistance of the silicon carbide layer having an n-type impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ increases in proportion to about 0.6 of the temperature, while 5 × As a result, the resistance of the silicon carbide layer having an n-type impurity concentration of about 10 ¹⁵ cm ⁻³ increased in proportion to the power of about 2.7.

  That is, the former is an impurity concentration assuming the source extension region 12b and the source contact region 12a, and the latter is an impurity concentration assuming the source resistance control region 15a and the drift layer 2. In silicon carbide semiconductors, since the activation energy of donors and acceptors is large, the concentration of electrons (holes) increases with temperature. Therefore, it is considered that the temperature dependence of resistance decreases as the concentration of donors (acceptors) increases.

  In this embodiment, since there are few implantation defects in the source resistance control region 15a, the temperature dependency of the resistance is large, and the source resistance control region 15a has the first conductivity type similar to that of the drift layer 2. Since it has an impurity concentration, the temperature dependence of the resistance of the source resistance control region 15a is even greater.

  Therefore, the resistance of the source resistance control region 15a increases as the temperature rises, and the effective gate voltage applied to the MOS channel region gradually decreases to reduce the drain current. Therefore, the time until the temperature rises to about 1000 K at the time of short circuit can be extended, and the short circuit tolerance can be greatly improved.

  That is, in this embodiment, the source resistance control region 15a having higher resistance temperature sensitivity can be obtained by reducing the impurity concentration of the source resistance control region 15a.

By the way, as an effective technique for reducing the impurity concentration of the first conductivity type, it is conceivable to inject and compensate (invert implantation) the second conductivity type impurity. However, for example, the impurity concentration of the first conductivity type and that of the second conductivity type are different from the impurity concentration of the first conductivity type of about 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ assumed as the drift layer 2. It is extremely difficult to achieve a low impurity concentration that effectively exhibits the first conductivity type by implantation from the viewpoint of the activation rate of the implanted species, the distribution in the depth direction, and the implantation control of a very dense dose.

  On the other hand, in the present embodiment, by using an epitaxial layer (region) by epitaxial growth as it is as the source resistance control region 15a, the impurity concentration of the first conductivity type in the source contact region 12a can be set sufficiently lower.

  In this embodiment, the concentration of the source contact region 12a and the source extension region 12b is the same, but they may be different. Further, the impurity concentration of the source extension region 12b and the source resistance control region 15a may be the same.

  According to the present embodiment, the first channel lower than the source contact region 12a in the path from the MOS channel region formed on the surface of the second well region 20b to the source region 12, the source ohmic electrode 40a, and the source pad 41. Since the source resistance control region 15a having a conductivity type impurity concentration (impurity concentration comparable to that of the drift layer 2) is inserted in series, an effective source resistance enough to affect the on-resistance of the element can be realized. it can.

  That is, according to the semiconductor device according to the present embodiment, the source region 12 has the source contact region 12a in contact with the ohmic electrode 40a connected to the source pad 41, the source extension region 12b adjacent to the MOS channel region, Since the source resistance control region 15a is connected in series, the saturation current can be controlled by the resistance corresponding to the sheet resistance of the source resistance control region 15a. Since the source resistance control region 15a is formed of a part of the drift layer surface where impurities are not directly ion-implanted, the resistance increase in a high-temperature heat generation environment such as when a load is short-circuited increases, and an effective gate The short circuit withstand capability is improved by decreasing the voltage and decreasing the saturation current.

  That is, the drain saturation current that affects the short-circuit tolerance is proportional to the square of the gate-source voltage applied to the MOS channel, but if there is a significant source resistance as in the present invention, an effective gate / The source-to-source voltage is reduced by the product of the source resistance and the drain current. Therefore, if the source resistance is increased, the saturation current is reduced and the short-circuit resistance can be improved.

  In the present embodiment, the source resistance control region 15a is provided in series in the source region 12 between the source ohmic electrode 40a and the MOS channel region. That is, the source contact region 12a, the source resistance control region 15a, and the source extension region 12b are connected in series to the current path. For example, the source contact region 12a and the source resistance control region 15a are connected to the current path. May be connected in parallel.

  In the present embodiment, as shown in FIGS. 2 and 3, in order to provide the source resistance control region 15a in series, the well gap region 15b is provided continuously around the first well region 20a, and the first region is formed around the first well region 20a. A 2-well region 20b is disposed. That is, the first well region 20a and the second well region 20b are separated via the well gap region 15b. In order to provide the source resistance control regions 15a in parallel, the well gap region 15b is intermittently provided around the second well region 20a in the top view, the inside of the well gap region 15b serves as the source resistance control region 15a, and the well gap The portion where the region 15b is intermittent may be the first well region 20a or the second well region 20b. That is, a region adjacent to the first well region 20a and the second well region 20b in the top view is provided.

  In the case of such a configuration, a region where the well gap region 15b is intermittent when viewed from above is, for example, the source contact region 12a. That is, a region where the source contact region 12a and the source extension region 12b are adjacent to each other without the source resistance control region 15a is generated. Since the on-state current preferentially flows in a region where the source resistance is reduced without passing through the source resistance control region 15a, an increase in on-resistance is suppressed, and the short-circuit current is reduced by the voltage effect of the source resistance control region 15a during a short circuit. As a result, the effect of improving the short-circuit resistance can be obtained.

  Although the temperature sensitivity of the resistance in the source resistance control region 15a is high and the effect of the present embodiment for improving the short-circuit tolerance is obtained by this region, a short-circuit current also flows in the source contact region 12a at the time of a short-circuit. The effect of this embodiment is reduced by the amount of short circuit current concentrated on 12a.

  In addition, since the first well region 20a and the third well region 20c are electrically connected to the source pad 41, they are fixed at the source potential (ground), respectively. The influence can be suppressed.

In the present embodiment, the impurity concentration of the first conductivity type in the source resistance control region 15a is smaller than the maximum impurity concentration of the first conductivity type in the source contact region 12a by at least three orders of magnitude (1/1000 or less). )doing. More specifically, the impurity concentration of the first conductivity type in the source resistance control region 15a is 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . As a result, the increase in resistance of the source resistance control region 15a in a high-temperature heat generation environment such as when a load is short-circuited increases, whereby the effective gate voltage decreases and the saturation current decreases, thereby improving the short-circuit tolerance.

  In the present embodiment, the source resistance control region 15a has a uniform distance (length) in the direction from the source extension region 12b to the source contact region 12a in the unit cell. More specifically, the range was 0.1 to 1 μm. Thereby, the current distribution in the unit cell and the heat generation distribution when the load is short-circuited become uniform, and the reliability against element destruction accompanied by heat generation such as when the load is short-circuited is improved.

  Further, if the current control region 14 or the high concentration layer 16 having a higher impurity concentration of the first conductivity type than the drift layer 2 is formed in the JFET region 11, the JFET resistance in the JFET region 11 is reduced while obtaining the above effect. , The on-resistance can be reduced.

  FIG. 22 is a cross-sectional view showing a modification of second well contact region 25a in the half unit cell of the silicon carbide MOSFET according to the present embodiment. As shown in FIG. 22, the first well contact region 25a may be formed deeper than the first well region 20a. This can be formed by forming the first well contact region 25a and the second well contact region 25b in separate steps.

  Further, FIG. 23 and FIG. 24 are cross-sectional views showing modifications of the well region 20 in the half unit cell of the silicon carbide MOSFET according to the present embodiment, and the second well region 20b is formed as shown in FIG. Thereafter, the first well region 20a is formed as shown in FIG. As described above, the second well region 20b and the first well region 20a can be formed by separate steps. Either the second well region 20b or the first well region 20a may be formed first. In FIG. 23, ion implantation of the second well region 20b is performed using the fifth implantation mask 100e and the second implantation mask 100b. In FIG. 24, ion implantation of the first well region 20a is performed using the sixth implantation mask 100f. In FIGS. 23 and 24, arrows indicate directions in which ion implantation is performed.

  At this time, the first well region 20a may be deeper than the second well region 20b as shown in FIG. Alternatively, the impurity concentration of the first well region 20a may be higher than the impurity concentration of the second well region 20b.

  FIG. 25 is a top view showing a manufacturing method of a modified example of well region 20 in the half unit cell of silicon carbide MOSFET according to the present embodiment. In order to obtain the well region 20 structure as shown in FIG. 24, after forming the second well region 20b in FIG. 25A, the first well region 20a is formed in FIG. In (c), the third well region 20c is formed. The order of formation may be any.

  FIG. 26 is a cross sectional view showing a case where first well region 20a is deeper than second well region 20b in the half unit cell of the silicon carbide MOSFET according to the present embodiment. If the method described in FIGS. 23, 24 and 25 is used, a silicon carbide MOSFET having the structure of FIG. 26 is obtained.

  FIG. 27 is a cross-sectional view showing a half unit cell for describing a manufacturing method in the case where fourth well region 20d is formed in silicon carbide MOSFET according to the present embodiment. FIG. 28 is a cross-sectional view showing a half unit cell when the fourth well region 20d is formed in the silicon carbide MOSFET according to the present embodiment.

  The arrows in FIG. 27 indicate the direction of ion implantation for forming the fourth well region 20d. As shown in FIG. 27, after forming the first well region 20a and the second well region 20b, ion implantation of the second conductivity type impurity using the fifth implantation mask 100g is performed more than the first well region 20a. A deep fourth well region 20d can also be formed. If the fourth well region 20d is formed as shown in FIG. 27, the silicon carbide MOSFET having the structure shown in FIG. 28 can be manufactured.

  The first well contact region 25a is formed deeper than the first well region 20a, the first well region 20a is formed deeper than the second well region 20b and the third well region 20c, and the first well region 20a By forming the fourth well region 20d deeper in the inside, the pn junction electric field at the end portion of the first well region 20a is made larger than the end portions of the second well region 20b and the third well region 20c. In addition, since an avalanche current can be supplied to the first well region 20a and the first well contact region 25a that do not have the MOS channel region, the avalanche resistance of the element can be improved.

  In addition, if the second conductivity type impurity concentration distributions in the depth direction in the first well region 20a, the second well region 20b, and the third well region 20c are the same, they can be simultaneously produced by one ion implantation. Therefore, the manufacturing cost can be reduced.

  In addition, by reducing the length of the well gap region 15b within a range of 0.01 to 1 μm, or by making the width narrower on the semiconductor substrate 1 side than on the surface side, it is possible to suppress the breakdown voltage degradation of the element. it can.

  In the present embodiment, in the structure in which the well gap region 15b is provided, the source contact region 12a, the source resistance control region 15a, the well gap region 15b, the drift layer 2, and the semiconductor substrate 1 are all of the first conductivity type. A free-wheeling diode is formed between the ohmic electrode 40a and the back surface ohmic electrode 42.

  When an inductive load such as a motor is driven by an inverter, a large surge current is generated when the current is interrupted during switching, etc., but this is passed through a free-wheeling diode connected in parallel to the load and in the opposite direction to the input / output direction. Therefore, surge current can be prevented from flowing to the load side, and damage to the equipment can be prevented.

  Generally, an SBD (Schottky Barrier Diode) serving as a free-wheeling diode is arranged as an external element of a switching element such as a MOSFET. In the case of a MOSFET, a built-in pn diode can be used as the free-wheeling diode. . By using the built-in diode, an external SBD is not required, so that the module can be reduced in size and cost.

  Compared with the case where an external SBD is used, the built-in free-wheeling diode can be used in this embodiment, so that the module can be reduced in size and cost.

  Also, when an external SBD or built-in pn diode is used, the rise voltage is almost determined by the physical function difference between the semiconductor and the Schottky metal in the former, and the built-in voltage of the semiconductor in the latter. There is a limit to doing it. On the other hand, since the built-in freewheeling diode of this embodiment is a diode with a unipolar operation that does not have a Schottky junction, the doping concentration of the semiconductor layer constituting the freewheeling diode and the depletion layer from the pn junction existing in the vicinity of the freewheeling diode The rise voltage can be made smaller by design, and an effect of reducing the switching loss is expected.

  In addition, when a forward current (bipolar current) is passed through a SiC pn diode, crystal defects (stacking defects) may be caused by energy released in the recombination process of electrons and holes. Since the stacking fault functions as a high resistance layer in electrical conduction, the pn diode characteristics and the on-characteristics of the MOSFET are deteriorated and the module loss is increased. Therefore, high-quality crystals that do not contain dislocations that are the starting point for stacking fault generation are essential.

  In the present embodiment, the generation of stacking faults due to the bipolar current flowing through the pn junction can be suppressed by allowing the unipolar current to flow through the well gap region 15b during the reflux operation.

  In the first embodiment, the silicon carbide MOSFET has been described as an example of the semiconductor device according to the present embodiment. However, the present invention is also applicable to an IGBT having a structure in which the conductivity type of the semiconductor substrate 1 is changed to the second conductivity type. Is possible.

  In the IGBT using this embodiment, the source region 12 is an “emitter region”, the well region 20 is a “base region”, and the semiconductor substrate 1 is a “collector region”. By providing a high resistance resistance control region (source resistance control region 15a) in the emitter region (source region 12), the emitter resistance can be increased, so that the emitter region (source region 12), base region (well) The current gain in the parasitic transistor composed of the region 20) and the drift layer 2 can be reduced, and as a result, the effect of preventing the latch-up caused by the operation of the IGBT parasitic thyristor can be obtained.

  In the first embodiment, the vertical silicon carbide MOSFET has been described as an example of the semiconductor device according to the present embodiment. However, a horizontal MOSFET having a RESURF (REduced SURface Field) structure, for example, may be used. .

  Note that the effects obtained from the structure of the semiconductor device described in this embodiment can be obtained in the same manner even if the semiconductor device is formed by another manufacturing method as long as the structure is provided.

  Further, in the present embodiment, each embodiment can be appropriately modified or omitted within the scope of the invention.

Embodiment 2. FIG.
FIG. 29 is a cross sectional view schematically showing a right half of a unit cell of a silicon carbide MOSFET which is a semiconductor device according to the second embodiment. In the semiconductor device in the present embodiment, field oxide film 31 is formed immediately above source resistance control region 15a, and nitrogen piles up at the MOS interface between source resistance control region 15a and field oxide film 31. It is characterized by not. The rest is the same as in the first embodiment. According to the present embodiment, nitrogen doping on the surface of the source resistance control region 15a can be suppressed, and the source resistance control region 15a maintaining the temperature dependence of the mobility of the source region 12 can be formed.

In the silicon carbide MOSFET which is the semiconductor device shown in the first embodiment, as shown in FIG. 2, a gate insulating film 30 is formed immediately above the source resistance control region 15a. In forming the gate insulating film 30, after the gate insulating film 30 made of silicon oxide is formed by wet oxidation, dry oxidation, deposition, or the like, heat treatment is performed in an NO or N ₂ O atmosphere in order to reduce the interface state. It is known.

According to the method of performing the heat treatment in the NO or N ₂ O atmosphere, it is known that nitrogen is diffused and piled up to the MOS interface at a high concentration in the MOS structure composed of silicon carbide and the gate insulating film 30. It is known that some diffuse to the extreme surface of silicon carbide. This is because the gate insulating film 30 is thin, so that nitrogen reaches the surface of silicon carbide through the gate insulating film 30 during the heat treatment.

  The nitrogen diffusion layer on the extreme surface may have a higher surface area density than the drift layer 2, that is, the temperature dependence of the conductive carriers may be reduced. This is not preferable because the effect of the present invention is reduced.

  In the present second embodiment, as shown in FIG. 29, the gate insulating film 30 is not formed immediately above the source resistance control region 15a, and the field oxide film 31 thicker than the gate insulating film 30 is controlled in the source resistance. It is formed by patterning immediately above the region 15a.

By doing in this way, in the region where the thick field oxide film 31 is formed, even if the heat treatment in the NO or N ₂ O atmosphere for forming the gate insulating film 30 is performed, nitrogen is added to the field oxide film 31. It is difficult to diffuse from the surface through the field oxide film 31 to the surface of the source resistance control region 15a. Therefore, nitrogen doping on the surface of the source resistance control region 15a can be suppressed, and the source resistance control region 15a can be formed in which the temperature dependence of mobility is kept high.

  In the second embodiment of the present invention, portions different from the first embodiment of the present invention are described, and descriptions of the same or corresponding portions are omitted.

  1 semiconductor substrate, 2 drift layer, 7 active region, 8 termination region, 10 unit cell, 11 JFET region, 12 source region, 12a source contact region, 12b source extension region, 14 current control region, 15a source resistance control region, 15b Well gap region, 16 high concentration layer, 20 well region, 20a first well region, 20b second well region, 20c third well region, 20d fourth well region, 25a first well contact region, 25b second well contact region 30 gate insulating film, 31 field oxide film, 32 interlayer insulating film, 35 gate electrode, 40a source ohmic electrode, 40b well ohmic electrode, 41 source pad, 42 back ohmic electrode, 43 drain electrode, 44 gate wiring, 45 Gate pad, 100a first implantation mask, 100b second implantation mask, 100c third implantation mask, 100d fourth implantation mask, 100e fifth implantation mask, 100f sixth implantation mask, 100g seventh implantation mask.

Claims (14)

A semiconductor substrate;
A first conductivity type drift layer formed on the semiconductor substrate;
A first well region of a second conductivity type formed in a surface layer portion of the drift layer;
A well gap region of a first conductivity type provided in a surface layer portion of the drift layer and adjacent to the first well region;
A second well region of a second conductivity type formed adjacent to the well gap region in a surface layer portion of the drift layer;
A source resistance control region of a first conductivity type provided in the well gap region;
A source contact region of a first conductivity type continuously formed from a part of a surface layer part of the first well region to a part of a surface layer part of the well gap region;
A first extension type source extension region continuously formed from a part of a surface layer part of the second well region to a part of a surface layer part of the well gap region;
A MOS channel region formed in the second well region located between the source extension region and the drift layer;
A gate electrode provided above the second well region and the source extension region via a gate insulating film;
A source electrode connected to the source contact region;
A semiconductor device comprising:   The source resistance control region has a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the source contact region.
  The semiconductor device according to claim 1.   The first well region is spaced apart from the second well region via the well gap region in a top view.
  The semiconductor device according to claim 1 or 2.   The length of the source resistance control region is uniform when viewed from above.
  The semiconductor device according to claim 3.   The source resistance control region has a length in the range of 0.1 to 1 μm in a top view.
  The semiconductor device according to claim 3, wherein:   The source resistance control region has a first conductivity type impurity concentration equal to a first conductivity type impurity concentration of the well gap region.
  The semiconductor device according to claim 1, wherein:   The drift layer has an impurity concentration distribution in the depth direction.
  The semiconductor device according to claim 1, wherein:   The source resistance control region has a field oxide film having a thickness larger than that of the gate insulating film on the surface.
  The semiconductor device according to claim 1, wherein:   The first well region has a second conductivity type impurity concentration equal to a second conductivity type impurity concentration of the second well region.
  The semiconductor device according to claim 1, wherein:   The drift layer includes a plurality of unit cells having the first well region, the well gap region, the second well region, the source resistance control region, the source contact region, the source extension region, and the gate insulating film. Prepared
  The semiconductor device according to claim 1, wherein:   A JFET region is provided between the second well regions of the adjacent unit cells and has a high current control region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the drift layer.
  The semiconductor device according to claim 10.   The source electrode is electrically connected to the first well region and the second well region.
  The semiconductor device according to claim 1, wherein:   A third well region of a second conductivity type formed in a surface layer portion of the drift layer, connecting the second well regions in the adjacent unit cells and electrically connected to the source electrode;
  The semiconductor device according to claim 1, wherein:   The semiconductor substrate is made of silicon carbide.
  The semiconductor device according to claim 1, wherein:

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