JP4494739B2 - Bipolar transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a bipolar transistor that can be used as a high-power transistor for high frequency and a manufacturing method thereof.

  A III-V compound semiconductor made of gallium arsenide (GaAs) or indium phosphide (InP) can be used as a semi-insulating substrate, and has an electron mobility and an electron saturation speed as compared with silicon (Si) -based semiconductor materials. It has advantages such as excellent electrical characteristics such as that, and the ability to design a semiconductor device having a desired energy band structure using a heterojunction.

  In particular, a heterojunction bipolar transistor (HBT) using a III-V compound semiconductor having a band gap larger than that of the base layer in the emitter layer can operate with a single power source and has high power added efficiency. Since it has the feature of excellent linearity of power amplification, it is widely used as a high-power transistor for mobile phones and the like.

  As conventional HBTs, AlGaAs / GaAs HBTs using p-type GaAs for the base layer and n-type aluminum gallium arsenide (AlGaAs) for the emitter layer, and p-type GaAs for the base layer and the emitter layer An InGaP / GaAs HBT using n-type indium gallium phosphide (InGaP) is known.

  FIG. 10A shows a cross-sectional configuration of a conventional InGaP / GaAs HBT. As shown in FIG. 10A, on a substrate 101 made of GaAs, a collector contact layer 102 made of high-concentration n-type GaAs, a collector layer 103 made of low-concentration n-type GaAa, and a base layer made of p-type GaAs. 104, an emitter layer 105 made of n-type InGaP and an emitter contact layer 106 made up of a plurality of n-type emitter layers are sequentially stacked.

  An emitter electrode 107 is formed on the emitter contact layer 106. The emitter layer 105 is formed in a mesa shape on the base layer 104, and a base electrode 108 is formed outside the emitter layer 105 on the base layer 104. A collector electrode 109 is formed outside the collector layer 103 on the collector contact layer 102.

  In the conventional HBT, InGaP having a band gap larger than that of the base layer 104 is used for the emitter layer 105, so that reverse injection of holes from the base layer 104 to the emitter layer 105 can be suppressed. This makes it possible to achieve both a reduction in the thickness of the base layer 104 and an increase in the concentration of the p-type impurity, thereby shortening the electron transit time of the base layer 104 and reducing the base resistance, thereby enabling high-speed operation. A conventional HBT can be used as a high-power device.

  Here, in the conventional HBT, the mesa-type emitter layer 105 is provided below the emitter contact layer 106 and connected to the emitter region 105a, which is a region that actually functions as an emitter. And a surface protection region 105b. The base layer 104 is divided into an intrinsic base region 104a that actually functions as a base, and an external base region 104b that connects the base electrode 108 and the intrinsic base region 104a at the lower portion of the emitter region 105a.

  The surface protection region 105b has a function of preventing electrons injected from the emitter electrode 107 through the emitter contact layer 106 into the emitter region 105a from recombining with holes on the surface of the external base region 104b.

FIG. 10B is an enlarged view of the emitter layer 105 and its peripheral portion of FIG. As shown in FIG. 10B, a positive direct current DC is input to the base electrode 108 together with the high-frequency input signal RF _IN to increase the RF power of the input signal. In this case, the base layer 104, are added p-type impurity of high concentration, acts as a resistance component with respect to direct current DC and the high frequency input signal RF _IN.

  By the way, when the conventional HBT is used as a high output transistor, the HBT shown in FIG. 10A is used as one unit cell, and about 10 to 100 HBTs are connected in parallel. However, there may be a difference in the degree of temperature rise in a plurality of HBTs due to variations in operating conditions. In this case, since the on-voltage between the emitter and the base of the HBT having a high temperature decreases, the emitter current increases and the temperature further increases, so that the operation of the high-power transistor device is thermally unstable. It becomes.

  In order to solve such a problem, a configuration in which a resistance element called ballast resistor is provided at the base input terminal of each HBT is known.

FIG. 11 shows a circuit configuration of a conventional high-power transistor device in which a ballast resistor is provided in each HBT. As shown in FIG. 11, a direct current DC is input to the base terminals of a plurality of bipolar transistors Q _{1 to} Q _n connected in parallel to each other through ballast resistors R _{1 to} R _n , and input capacitance An input signal RF _IN is input via C _{1 to} C _n .

With such a configuration, when a current is to be concentrated on _one bipolar transistor Q ₁ , a voltage drop occurs due to the ballast resistor R _1, so that the voltage applied to the base layer is reduced and the current concentration is alleviated. The Further, since the input signal RF _IN is input to the base electrode via the input capacitors C _{1 to} C _n , the high frequency characteristics due to the ballast resistors R _{1 to} R _n are not deteriorated.

The high-power transistor device of FIG. 11 is obtained by forming bipolar transistors Q _{1 to} Q _n with the same configuration as the HBT of FIG. In this case, each of the ballast resistors R _{1 to} R _n is formed using a thin film made of a metal or a semiconductor material in a portion different from the HBT element formation region on the substrate, and a capacitive insulating film made of silicon nitride (SiN) or the like The input capacitors C _{1 to} C _n are formed using a conductive film made of metal.
JP-A-8-279561 US Pat. No. 5,608,353 US Pat. No. 5,629,648

However, according to the conventional HBT, since the distance between the base electrode 108 and the emitter electrode 107 is increased by providing the surface protection region 105b, the base resistance is increased. Therefore, the current reduction of the input signal RF _IN of the high frequency input from the base electrode 108 is increased, high-frequency characteristics of the HBT is deteriorated.

Further, when the input capacitors C _{1 to} C _n , the ballast resistors, and R _{1 to} R _n are provided in the bipolar transistors Q _{1 to} Q _{n as} in the conventional high output transistor device, the input capacitance is added to the HBT formation region. Since it is necessary to secure the formation region and the ballast resistor formation region, the chip area increases and the chip cost increases. In particular, when silicon nitride is used for the capacitive insulating film, a rectangular area having a side of 10 μm or more is required for each HBT in order to secure a capacitance value required as an input capacitance. Increases significantly. Further, since it is necessary to form the ballast resistor and the input capacitance after forming the HBT element, the manufacturing cost increases.

  An object of the present invention is to solve the conventional problems and to obtain a bipolar transistor having good thermal stability and high frequency characteristics without increasing the chip area and the manufacturing cost.

  In order to achieve the above object, the present invention has a configuration in which a capacitive film is provided in a portion between the base layer and the base electrode.

  Specifically, the bipolar transistor according to the present invention includes a first semiconductor layer having an intrinsic base region and an external base region, a portion formed on the first semiconductor layer, and a portion located on the intrinsic base region being an emitter. A second semiconductor layer serving as a region or a collector region; a capacitor film formed on the external base region in the first semiconductor layer; and a portion on the first semiconductor layer on the capacitor film. A base electrode is formed and the other part is connected to the external base region.

  According to the bipolar transistor of the present invention, the high-frequency input signal input to the base electrode reaches the intrinsic base region through the capacitance film, so that the high-frequency characteristics of the input signal are not deteriorated by the resistance of the external base region. . Further, since the capacitor element can be provided in the formation region of the bipolar transistor, the capacitor element can be provided without increasing the chip area. Furthermore, since the direct current input to the base electrode reaches the intrinsic base region through the external base region, the resistance to the direct current can be set so as to increase. Stability can be improved.

  In the bipolar transistor of the present invention, the capacitor film is preferably made of the same semiconductor material as that of the second semiconductor layer.

  In this way, since no special dielectric material is used for the capacitor film, a bipolar transistor can be manufactured at low cost.

  In the bipolar transistor of the present invention, it is preferable that the capacitor film is provided so that the end portion on the second semiconductor layer side is in contact with the side surface of the second semiconductor layer.

  In this case, since the capacitor film can be used as a surface protection region for preventing recombination of electrons and holes on the surface of the external base region, the current gain of the bipolar transistor can be improved.

  In the bipolar transistor of the present invention, it is preferable that a high resistance region having a resistance value higher than that of the intrinsic base region is provided in the external base region.

  In this way, the resistance value of the path through which the direct current input to the base electrode passes through the external base region becomes high, so that a sufficient resistance value as a ballast resistor can be secured, and the thermal stability of the bipolar transistor is improved. It can certainly improve.

  In the bipolar transistor of the present invention, the capacitor film is provided on a region of the external base region spaced from the end opposite to the intrinsic base region, and the base electrode is formed on the external base region and the capacitor film. The capacitor film is preferably provided so as to straddle the end of the capacitor film opposite to the second semiconductor layer.

  In this way, since the portion of the base electrode that is relatively far from the intrinsic base region is connected to the external base region, the distance of the path through which the direct current input to the base electrode passes through the external base region increases. Therefore, it is possible to reliably improve the thermal stability by increasing the resistance value as the ballast resistor.

  In the bipolar transistor of the present invention, the base electrode preferably comprises a first base electrode formed on the capacitor film and a second base electrode connected to the external base region of the first semiconductor layer. .

  In this way, since the direct current is not input to the base electrode through the side surface of the capacitive film, the leakage current amount of the direct current can be reduced.

  In the bipolar transistor of the present invention, the second base electrode is preferably made of a metal material whose resistance value increases as the temperature rises.

  If it does in this way, since the value of the ballast resistance to direct current becomes large with temperature rise, thermal stability will improve further.

  In the bipolar transistor of the present invention, the capacitor film is provided on a region of the external base region that is spaced from the end opposite to the intrinsic base region, and the second base electrode is disposed on the side of the capacitor film. It is preferable to be provided on a portion far from the intrinsic base region.

  In the bipolar transistor of the present invention, the capacitor film is formed on the first semiconductor layer so as to include the end of the external base region opposite to the intrinsic base region, and the first base electrode. And the second base electrode is provided on the capacitor film so that the second base electrode is located in a portion farther from the intrinsic base region than the first base electrode. The first semiconductor layer is preferably connected to the first semiconductor layer.

  In the bipolar transistor of the present invention, the second semiconductor layer is preferably made of a semiconductor material having a band gap larger than that of the first semiconductor layer.

  In the bipolar transistor of the present invention, it is preferable that the first semiconductor layer is made of a first conductivity type semiconductor material, and the capacitor film is made of a second conductivity type semiconductor material.

  The bipolar transistor manufacturing method according to the present invention includes a first step of sequentially forming a first semiconductor layer and a second semiconductor layer on a substrate, and a first step of forming an emitter region or a collector region from the second semiconductor layer. A second step of partitioning the region and the second region to be a capacitor film; and on the first semiconductor layer, one portion is connected to the first semiconductor layer and the other portion is And a third step of forming a base electrode so as to include the second region.

  According to the bipolar transistor manufacturing method of the present invention, a part of the base electrode is connected to the first semiconductor layer and the other part is connected to the capacitor film, so that the high-frequency input signal input to the base electrode is the capacitor film. It can be configured to reach the intrinsic base region through the DC current input to the base electrode and through the external base region to reach the intrinsic base region, so that high frequency characteristics and thermal stability A bipolar transistor with good characteristics can be realized. Further, since the capacitor film is formed from the second semiconductor layer for forming the emitter region or the collector region, it is possible to form the capacitor element in the bipolar transistor formation region without using a special dielectric material. it can.

  In the method for manufacturing a bipolar transistor of the present invention, the second step includes a step of forming a mask pattern covering the first region and the second region, and a second step until the first semiconductor layer is exposed using the mask pattern. And etching the semiconductor layer.

  In this case, since the capacitor film can be formed simultaneously with the formation of the emitter region or the collector region from the second semiconductor layer, the capacitor element can be formed in the formation region of the bipolar transistor without adding a special process. it can.

  In the bipolar transistor manufacturing method of the present invention, in the second step, it is preferable to form a mask pattern so that the first region and the second region are in contact with each other.

  In this way, the capacitor film can be formed as a surface protection region for preventing recombination of electrons and holes on the surface of the external base region, so that the current gain of the bipolar transistor can be improved.

  The bipolar transistor manufacturing method of the present invention preferably further includes a step of performing ion implantation on the exposed surface of the first semiconductor layer using a mask pattern after the second step.

  In this case, since the ion implantation region of the first semiconductor layer can be formed as a high resistance region, a sufficient resistance value as a ballast resistor can be ensured, and the thermal stability of the bipolar transistor is reliably improved. Can do.

  In the bipolar transistor manufacturing method of the present invention, it is preferable that the base electrode is formed so as to include the exposed surface of the first semiconductor layer and the second region of the two semiconductor layers in the third step.

  In this way, it is possible to reliably form a base electrode in which one part is connected to the first semiconductor layer and the other part is connected to the capacitor film.

  In the method for manufacturing a bipolar transistor of the present invention, in the third step, a step of forming a first base electrode connected to the first semiconductor layer, and a second base electrode on the second semiconductor layer are formed. Preferably including the step of forming.

  In the method for manufacturing a bipolar transistor of the present invention, it is preferable to use a metal material whose resistance value increases as the temperature rises as the material constituting the second base electrode.

  In the method for manufacturing a bipolar transistor of the present invention, the second step includes a step of forming a mask pattern covering the first region and the second region, and a second step until the first semiconductor layer is exposed using the mask pattern. Etching the semiconductor layer, and in the third step, a first base electrode is formed on the second region of the second semiconductor layer, and on the exposed surface of the first semiconductor layer. It is preferable to form a second base electrode.

  The bipolar transistor manufacturing method of the present invention includes a step of forming a first base electrode using a first metal material on a second region, and a step of forming a first base electrode on the second region than the first base electrode. Forming a second base electrode using a second metal material so as to be located in a portion far from the first region; selectively diffusing the second metal material to form the second base electrode and the second base electrode; It is preferable to include a step of connecting one semiconductor layer.

  In the bipolar transistor manufacturing method of the present invention, in the first step, a material having a band gap larger than that of the first semiconductor layer is preferably used as the material constituting the second semiconductor layer.

According to the bipolar transistor and the manufacturing method thereof of the present invention, the high frequency input signal input to the base electrode reaches the intrinsic base region through the capacitive film, and the direct current input to the base electrode passes through the external base region. Therefore, a bipolar transistor with good high frequency characteristics and thermal stability can be realized. Further, since the capacitive element can be provided in the formation region of the bipolar transistor, the capacitive element can be provided without increasing the chip area.

(First embodiment)
A bipolar transistor according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A shows a cross section of a bipolar transistor according to the first embodiment of the present invention. As shown in FIG. 1A, for example, on a substrate 11 made of gallium arsenide (GaAs), a collector contact layer 12 made of n-type GaAs, a collector layer 13 made of n-type GaAs, and a p-type A base layer (first semiconductor layer) 14 made of GaAs, an emitter layer (second semiconductor layer) 15 made of n-type indium gallium phosphide (InGaP), and an n-type indium gallium arsenide (InGaAs). The emitter contact layers 16 are sequentially formed.

  Here, in the base layer 14, the lower part of the emitter layer 15 becomes an intrinsic base region 14 a that actually functions as a base, and the region on the side of the intrinsic base region 14 a is an external base region 14 b that does not function as a base. Become.

  The emitter layer 15 and the emitter contact layer 16 are formed in a mesa shape on the base layer 14, and an emitter electrode 17 made of tungsten silicide (WSi) is formed on the emitter contact layer 16.

  In addition, on the external base region 14b in the base layer 14, a capacitor film 18 made of n-type InGaP and a laminated film (Ti / Pt / A base electrode 19 made of Au) is provided. Here, the capacitor film 18 is provided on a region of the external base region 14b near the intrinsic base region 14a, and the base electrode 19 is formed on the external base region 14b and the capacitor film 18, and on the emitter layer 15 of the capacitor film 18. It is provided so as to straddle the opposite end.

  The collector layer 13 and the base layer 14 are provided so that the end portions thereof are located inside the collector contact layer 12, and the collector electrode 20 made of a metal material is disposed on the end portions of the collector contact layer 12. Is formed.

  The specific composition, impurity concentration, and film thickness of each semiconductor layer described above are shown in [Table 1].

As shown in [Table 1], n-type GaAs having an n-type impurity concentration of about 5 × 10 ¹⁸ cm ⁻³ and a film thickness of about 500 nm is used for the collector contact layer 12. An n-type GaAs having an n-type impurity concentration of about 3 × 10 ¹⁶ cm ⁻³ and a film thickness of about 700 nm is used, and the base layer 14 has a p-type impurity concentration of about 4 × 10 ¹⁹ cm ⁻³ and P-type GaAs with a film thickness of about 70 nm is used, and In _0.5 Ga _0.5 P with an n-type impurity concentration of about 3 × 10 ¹⁷ cm ⁻³ and a film thickness of about 50 nm is used for the emitter layer 15. The emitter contact layer 16 includes an n-type GaAs layer having an n-type impurity concentration of about 3 × 10 ¹⁸ cm ⁻³ and a film thickness of about 100 nm, and a film thickness of about 50 nm. The n-type In concentration is changed from 3 × 10 ¹⁸ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ and the indium (In) composition value X is changed from 0 to 0.5. A laminated film in which an _X Ga _1-X As layer and an n-type In _0.5 Ga _0.5 As layer having an n-type impurity concentration of 2 × 10 ¹⁹ cm ⁻³ and a film thickness of about 50 nm are sequentially laminated is used. .

Similarly to the emitter layer 15, the capacitor film 18 is made of In _0.5 Ga _0.5 P having an n-type impurity concentration of about 3 × 10 ¹⁷ cm ⁻³ and a film thickness of about 50 nm. (Dimension in the direction from the emitter layer 15 toward the outside) is about 1 μm.

  The bipolar transistor of the first embodiment is characterized in that a capacitive film 18 is provided between the base layer 14 and the base electrode 19. Since the p-type impurity having a very high concentration compared to the n-type impurity concentration of the capacitor film 18 is added to the base layer 14, the capacitor film 18 is almost completely depleted. It can be used as a dielectric between the base electrode 19 and the base layer 14.

  The characteristics of the bipolar transistor of the first embodiment will be specifically described below with reference to FIG.

  FIG. 1B is an enlarged view of the peripheral portion of the base electrode 19 in the bipolar transistor shown in FIG.

As shown in FIG. 1 (b), the base electrode 19, an input signal RF _IN of the high-frequency and direct current DC is inputted, it is inputted from the external base region 14b in the intrinsic base region 14a. At this time, the direct current DC and the input signal RF _IN input to the base electrode 19 are directly input from the base electrode 19 to the external base region 14b and then below the capacitive film 18 until reaching the intrinsic base region 14a. A first path that reaches the intrinsic base region 14a through the side, and a second path that reaches the intrinsic base region 14a after being input from the base electrode 19 through the capacitive film 18 to the external base region 14b. Divided. In the first path, the external base region 14b functions as a resistance element, and in the second path, the base electrode 19, the capacitor film 18, and the external base region 14b serve as an upper electrode, a dielectric film, and a lower electrode, respectively. It functions as a capacitor element.

Thus, since the capacitive film 18 is provided between the base layer 14 and the base electrode 19 on the side close to the emitter layer 15, a capacitive element connected in parallel to the base resistance can be realized. Thus, the input signal RF _IN of the high-frequency input to the base electrode 19 so reaching the intrinsic base region 14a through the capacitive element, the power loss due to the base resistance is reduced. Further, even if the amount of direct current DC increases, the voltage drops due to the resistance of the external base region 14b, so that the temperature increase of the intrinsic base region 14a can be suppressed.

Specifically, in the case where the same semiconductor material as the emitter layer 15 is used for the capacitor film 18 and the capacitor film 18 is formed to have a film thickness of about 50 nm and a plane area of about 80 μm ² , The capacitance is about 0.18 pF. In this case, if about 100 heterobipolar transistors of the first embodiment are connected in parallel and used for a high-power device for high-frequency signals, the input capacitance is about 18 pF, so that the high-frequency characteristics are not deteriorated. The input capacity of the output device can be secured.

For example, when the frequency of the input signal RF _IN is in the range of 800 kHz to 2 GHz, if the capacitive film 18 has a film thickness of about 50 nm to 300 nm and a width dimension of about 1 to 4 μm, the high frequency characteristics of the input signal RF _IN deteriorate. It is possible to secure a sufficient input capacity so as not to do so.

  Further, by adjusting the width dimension of the capacitive film 18, it is possible to appropriately set the resistance value by adjusting the distance of the path passing directly from the base electrode 19 through the external base region 14 b. Therefore, the thermal stability of the bipolar transistor can be improved by using the base resistor as the ballast resistor.

  In the first embodiment, a capacitor element is realized as a pn junction capacitor by using n-type InGaP as a constituent material of the capacitor film 18. However, the present invention is not limited to such a configuration, and a dielectric such as silicon nitride is used. Materials may be used. However, since the emitter film 15 and the capacitor film 18 can be formed simultaneously by using the same semiconductor material as the emitter layer 15 for the capacitor film 18, the manufacturing cost of the bipolar transistor can be reduced.

  In the first embodiment, the emitter-up bipolar transistor in which the emitter layer is provided on the base layer has been described. However, the emitter layer is provided below the base layer, and the collector layer is provided above the base layer. It may be formed as a collector-up type bipolar transistor provided.

  Further, the composition and film pressure of each semiconductor layer constituting the bipolar transistor of the first embodiment do not need to be set as shown in [Table 1], and may be appropriately set so as to be suitable for transistor operation. That's fine.

  In the first embodiment, an InGaP / GaAs bipolar transistor using GaAs for the base layer 14 and InGaP for the emitter layer 15 has been described. However, the materials of the base layer 14 and the emitter layer 15 are changed. A bipolar transistor such as AlGaAs / GaAs, InAlAs / InGaAs, or InP / InGaAs may be used.

  In addition, although a laminated film in which titanium, platinum, and gold are sequentially laminated is used as a material constituting the base electrode 19, it is not limited to such a configuration. For example, tungsten silicide (WSi) or molybdenum (Mo) may be used for the lowermost layer of the base electrode 19, and titanium, platinum, and gold may be sequentially stacked thereon. In this way, the thermal reaction between the base electrode 19 and the capacitive film 18 can be suppressed.

(Manufacturing method of the first embodiment)
A bipolar transistor manufacturing method according to the first embodiment of the present invention will be described below with reference to the drawings.

  2 (a) to 2 (d) and FIGS. 3 (a) to 3 (c) show cross-sectional structures in order of steps of the manufacturing method of the bipolar transistor according to the first embodiment of the present invention.

  First, as shown in FIG. 2A, a collector contact layer 22 made of GaAs doped with n-type impurities and a low-concentration n-type impurity were added on a substrate 21 made of GaAs by epitaxial growth. A collector layer forming layer 23 made of GaAs, a base layer forming layer (first semiconductor layer) 24 made of GaAs doped with high-concentration p-type impurities, and an emitter made of n-type InGaP doped with n-type impurities A layer forming layer (second semiconductor layer) 25 and an emitter contact layer forming layer 26 made of InGaAs containing an n-type impurity and having an indium composition sequentially increased from 0 to 0.5 are sequentially formed. Thereafter, an emitter electrode forming layer 27 made of WSi is formed on the emitter contact layer forming layer 26 by sputtering.

  Here, the composition and film thickness of each semiconductor layer to be epitaxially grown are the same as those of each semiconductor layer shown in [Table 1].

  Next, as shown in FIG. 2B, a first resist pattern 28 that covers the emitter electrode formation region is formed on the emitter electrode formation layer 27 by lithography. Thereafter, the emitter electrode formation layer 27 is etched by the reactive ion etching (RIE) method using the first resist pattern 28 until the emitter contact layer formation layer 26 is exposed. Thereby, an emitter electrode 27A is formed from the emitter electrode formation layer 27.

  Next, as shown in FIG. 2C, the emitter contact layer is exposed until the emitter layer formation layer 25 is exposed by wet etching or dry etching using the first resist pattern 28 and the emitter electrode 27A as a mask. The formation layer 26 is etched. Thereby, the emitter contact layer 26A is formed from the emitter contact layer forming layer 26. Here, in the etching process for the emitter contact layer forming layer 26, side etching occurs, so the emitter contact layer 26A is formed in a region inside the emitter electrode 27A.

  Next, as shown in FIG. 2D, after removing the first resist pattern 28, the first mask portion 29a covering the emitter electrode 27A and the emitter in the emitter layer forming layer 25 are formed by lithography. A second resist pattern 29 having a second mask portion 29b covering a predetermined region spaced apart from the electrode 27A is formed. Thereafter, the emitter layer forming layer 25 is etched by a dry etching method using the second resist pattern 29 until the base layer forming layer 24 is exposed. As a result, the emitter layer 25A is formed from the portion located below the first mask portion 29a in the emitter layer forming layer 25, and the capacitor film 25B is formed from the portion located below the second mask portion 29b. To do.

  Next, as shown in FIG. 3A, after the second resist pattern 29 is removed, the base layer formation layer 24 and the base layer formation layer 24 are formed on the base layer formation layer 24 by the lithography method. A third resist pattern 30 having an opening 30a that opens the capacitor film 25B on the upper surface of the first resist pattern 30 is formed. Subsequently, Ti, Pt, and Au are sequentially stacked on the entire surface of the third resist pattern 30 so as to include the top of the opening by using an electron beam evaporation method or the like. .

  Next, as shown in FIG. 3B, the third resist pattern 30 is removed with an organic solvent or the like. Thereby, the base electrode 31 </ b> A is formed from the metal film 31.

  Thereafter, as shown in FIG. 3C, the base layer forming layer 24 and the collector layer forming layer 23 are sequentially patterned until the collector contact layer 22 is exposed, thereby forming the base layer 24A from the base layer forming layer 24. Then, the collector layer 23A is formed from the collector layer forming layer 23. Subsequently, the collector electrode 32 is formed on the exposed surface of the collector contact layer 22 using lithography and electron beam evaporation. Thereafter, the base electrode 31A and the collector electrode 32 are alloyed by performing a heat treatment at a temperature of about 400 ° C. Thereby, the bipolar transistor of the first embodiment shown in FIG. 1A is completed.

  According to the bipolar transistor manufacturing method of the first embodiment, the capacitor film 25B is formed on the base layer forming layer 24, and then the base electrode 31A is formed, so that it functions as a capacitor element in the bipolar transistor formation region. Since a portion can be provided, an input capacitance for a high-frequency input signal that increases the chip area can be secured.

  In particular, since the emitter layer 25A and the capacitor film 25B are formed from the emitter layer forming layer 25, the capacitor film 25B can be formed without using a special dielectric material, so that the capacitor element can be formed at low cost.

  In the first embodiment, the emitter layer 25A and the capacitor film 25B are formed from the emitter layer formation layer 25. However, the present invention is not limited to this configuration. For example, the emitter layer 25A is formed from the emitter layer formation layer 25. After that, the capacitor film 25B may be formed using another dielectric material. Even in this case, it is possible to provide a capacitor region in the base input terminal without increasing the chip area.

(Second Embodiment)
Hereinafter, a bipolar transistor according to a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 4 shows a cross-sectional configuration of a bipolar transistor according to the second exemplary embodiment of the present invention. In FIG. 4, the same members as those of the bipolar transistor of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 4, a collector contact layer 12, a collector layer 13, and a base layer 14 having an intrinsic base region 14a and an external base region 14b are sequentially formed on the substrate 11. On the base layer 14, an emitter layer 41 having an emitter region 41a above the intrinsic base region 14a and having a surface protection region 41b on the external base region 14b is provided. On the emitter region 41 a in the emitter layer 41, an emitter contact layer 16, an emitter electrode 17, and an upper emitter electrode 42 made of a laminated film (Ti / Pt / Au) in which titanium, platinum, and gold are sequentially laminated are sequentially formed. Is formed.

  Further, a base electrode 19 made of Ti / Pt / Au is provided on the external base region 14 b of the base layer 14 so as to straddle the end of the emitter layer 41 and include on the emitter layer 41. A collector electrode 20 is provided on the collector contact layer 12.

  The composition and film thickness of each semiconductor layer in the second embodiment are the same as the composition and film thickness of each semiconductor layer in the first embodiment shown in [Table 1].

  According to the bipolar transistor of the second embodiment, since the surface protection region 41b is provided, electrons injected from the emitter electrode 17 are recombined with holes in the external base region 14b outside the emitter region 41a. Therefore, the current gain of the bipolar transistor can be improved as compared with the first embodiment.

  In addition, since the p-type impurity having a very high concentration compared to the n-type impurity concentration of the emitter layer 41 is added to the base layer 14, the surface protection region 41b is depleted over almost the entire depth direction. Accordingly, the surface protection region 41b functions as a dielectric film of the capacitive element, like the capacitive film 18 of the first embodiment.

  In the second embodiment, the upper emitter electrode 42 is provided on the emitter electrode 17, but the upper emitter electrode 42 may be omitted.

  In the second embodiment, the emitter layer 41 having the emitter region 41a and the surface protection region 41b is provided. However, as in the first embodiment, the emitter layer and the capacitor film are provided, The capacitor film may be used as the surface protection region by disposing the end portion on the emitter layer side so as to be in contact with the emitter layer.

(Manufacturing method of the second embodiment)
A bipolar transistor manufacturing method according to the second embodiment of the present invention will be described below with reference to the drawings.

  FIG. 5A to FIG. 5D show cross-sectional configurations in the order of steps in the method for manufacturing a bipolar transistor according to the second embodiment of the present invention. 5A to 5D, the same members as those in the method for manufacturing the bipolar transistor according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. Note that the process shown in FIG. 5A corresponds to the process of FIG. 2D of the first embodiment.

  First, similarly to the steps shown in FIGS. 2A to 2C, a collector contact layer 22, a collector layer forming layer 23, a base layer forming layer 24, an emitter layer forming layer 25, After the emitter contact layer forming layer 26 and the emitter electrode forming layer 27 are sequentially stacked, the emitter electrode 27A is formed from the emitter electrode forming layer 27 by etching using the first resist pattern 28, and then the emitter contact layer forming layer is formed. 26, an emitter contact layer 26A is formed.

  Next, as shown in FIG. 5A, a second resist pattern 51 is formed on the emitter layer formation layer 25 by a lithography method so as to cover a predetermined region including the top of the emitter electrode 27A. Thereafter, the emitter layer forming layer 25 is etched by dry etching using the second resist pattern 51 until the base layer forming layer 24 is exposed. Thus, an emitter layer 25C having an emitter region and a surface protection region is formed from the emitter layer forming layer 25.

  Next, as shown in FIG. 5B, after the second resist pattern 51 is removed, the top of the emitter electrode 27A and the top of the emitter layer 25C are formed on the base layer forming layer 24 by lithography. A third resist pattern 52 is formed so as to open a predetermined region including it. Subsequently, a metal film 31 made of Ti, Pt, and Au is formed on the third resist pattern 52 over the entire surface including the top of the opening by using an electron beam evaporation method or the like.

  Next, as shown in FIG. 5C, the third resist pattern 52 is removed with an organic solvent or the like. Thus, the base electrode 31B and the upper emitter electrode 31C are formed from the metal film 31.

  Next, as shown in FIG. 5D, the base layer forming layer 24 and the collector layer forming layer 23 are sequentially patterned until the collector contact layer 22 is exposed, thereby forming the base layer 24A from the base layer forming layer 24. At the same time, a collector layer 23 A is formed from the collector layer forming layer 23. Subsequently, the collector electrode 32 is formed on the exposed surface of the collector contact layer 22 using lithography and electron beam evaporation.

  Through the above steps, the bipolar transistor of the second embodiment shown in FIG. 2 is completed.

  According to the bipolar transistor manufacturing method of the second embodiment, the emitter layer 25C having an emitter region and a surface protection region is formed, and a part of the surface protection region is used as a capacitor film. The base electrode 31B can be formed in a self-aligned manner with respect to the emitter electrode 27A. That is, in the second embodiment, it is not necessary to align the emitter electrode when forming the base electrode 31B, so that the base electrode 31B can be formed easily and reliably.

(Third embodiment)
Hereinafter, a bipolar transistor according to a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 6 shows a cross-sectional configuration of a bipolar transistor according to the third exemplary embodiment of the present invention. In FIG. 6, the same members as those of the bipolar transistor of the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 6, the bipolar transistor of the third embodiment is provided with a high resistance region 61 in which boron ions (B ⁺ ) are implanted outside the emitter layer 15 in the collector layer 13 and the base layer 14. This is different from the second embodiment.

According to the bipolar transistor of the third embodiment, since the portion of the base layer 14 that is in direct contact with the base electrode 19 is formed as the high resistance region 61, the direct current DC input from the base electrode 19 and Of the high frequency input signal RF _IN , the direct current component passes through the high resistance region 61 and reaches the intrinsic base region 14a. Accordingly, since the base resistance of the direct current component is increased as a ballast resistance, the thermal stability of the bipolar transistor can be reliably improved.

  In the third embodiment, ions implanted into the high resistance region 61 are not limited to boron ions, and ions of hydrogen, helium, oxygen, fluorine, and argon may be implanted.

  In the third embodiment, the depth of the high resistance region 61 is set to reach the collector layer 13 from the surface of the base layer 14, but is not limited to such a configuration. It is good also as a structure which inject | pours only into.

(Manufacturing method of the third embodiment)
A bipolar transistor manufacturing method according to the third embodiment of the present invention will be described below with reference to the drawings.

  FIG. 7A to FIG. 7D show a cross-sectional configuration of a bipolar transistor according to the third embodiment of the present invention. 7A to 7D, the same members as those of the bipolar transistor manufacturing method according to the first embodiment and the second embodiment are denoted by the same reference numerals, and the description thereof is omitted. Note that the process shown in FIG. 7A corresponds to the process of FIG. 5A of the second embodiment.

  First, similarly to the steps shown in FIGS. 2A to 2C, a collector contact layer 22, a collector layer forming layer 23, a base layer forming layer 24, an emitter layer forming layer 25, After the emitter contact layer forming layer 26 and the emitter electrode forming layer 27 are sequentially stacked, the emitter electrode 27A is formed from the emitter electrode forming layer 27 by etching using the first resist pattern 28, and then the emitter contact layer forming layer is formed. 26, an emitter contact layer 26A is formed.

  Next, as shown in FIG. 7A, a second resist pattern 51 is formed on the emitter layer formation layer 25 by a lithography method so as to cover a predetermined region including the top of the emitter electrode 27A. Thereafter, the emitter layer forming layer 25 is etched by dry etching using the second resist pattern 51 until the base layer forming layer 24 is exposed. Thus, an emitter layer 25C having an emitter region and a surface protection region is formed from the emitter layer forming layer 25.

Thereafter, ion implantation is performed on the exposed surface of the base layer forming layer 24 using the second resist pattern 51 as a mask. Two-stage boron ions (B ^{+) with an} implantation energy of about 30 keV and a dose of 3 × 10 ¹² cm ⁻² and an implantation energy of about 200 keV and a dosage of 5 × 10 ¹² cm ^−2. ) Injection. Thereby, the high resistance region 61 is formed in the base layer forming layer 24 and the collector layer forming layer 23.

  Next, as shown in FIG. 7B, after the second resist pattern 51 is removed by lithography, the emitter layer 27C and the emitter layer 25C are formed on the base layer formation layer 24 by lithography. A third resist pattern 52 is formed so as to open a predetermined region including the upper side of the upper side. Subsequently, a metal film 31 made of Ti, Pt, and Au is formed on the third resist pattern 52 over the entire surface including the top of the opening by using an electron beam evaporation method or the like.

  Next, as shown in FIG. 7C, the third resist pattern 52 is removed with an organic solvent or the like. Thus, the base electrode 31B and the upper emitter electrode 31C are formed from the metal film 31.

  Next, as shown in FIG. 7D, the base layer forming layer 24 and the collector layer forming layer 23 are sequentially patterned until the collector contact layer 22 is exposed, thereby forming the base layer 24A from the base layer forming layer 24. At the same time, a collector layer 23 A is formed from the collector layer forming layer 23. Subsequently, the collector electrode 32 is formed on the exposed surface of the collector contact layer 22 using lithography and electron beam evaporation.

  Through the above steps, the bipolar transistor of the third embodiment shown in FIG. 6 is completed.

  According to the bipolar transistor manufacturing method of the third embodiment, the second resist pattern 51, which is a mask pattern for forming the emitter layer 25C, can be used as a mask for ion implantation. The high resistance region 61 can be formed without using the mask.

  In the method of manufacturing the bipolar transistor of the third embodiment, the dimension in the depth direction of the high resistance region 61 can be set to an appropriate value by changing the ion implantation conditions.

(Fourth embodiment)
Hereinafter, a bipolar transistor according to a fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 8 shows a cross-sectional configuration of a bipolar transistor according to the fourth exemplary embodiment of the present invention. In FIG. 8, the same members as those of the bipolar transistor of the second embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the bipolar transistor of the second embodiment, the base electrode 19 is provided on the base layer 14 and the surface protection region 41b. However, in the bipolar transistor of the fourth embodiment, as shown in FIG. Two types of base electrodes are formed: a first base electrode 71 provided on the surface protection region 41 b and a second base electrode 72 provided on the base layer 14.

  In the bipolar transistor of the second embodiment, since the base electrode is provided in contact with the side surface of the surface protection region 41b, there is a possibility that the leakage current flows into the intrinsic base region 14a through the side surface of the surface protection region 41b. is there.

  On the other hand, according to the bipolar transistor of the fourth embodiment, the base electrode is separately provided on the upper side of the surface protection region 41b serving as the capacitive film and on the external base region 14b. The direct current does not leak to the base layer 14 from the side surface of 41b.

In particular, the configuration is such that the high frequency input signal RF _IN is input to the first base electrode 71 and the direct current DC is input to the second base electrode 72, so that the leakage current is reliably suppressed and the high frequency characteristics are improved. Improvement is possible.

  The bipolar transistor manufacturing method of the fourth embodiment can be realized by changing the shape of the third resist pattern 52 in the step of FIG. 5B of the bipolar transistor manufacturing method of the second embodiment.

  In the fourth embodiment, the configuration in which the first base electrode 71 is provided on the surface protection region 41b has been described. However, the first base electrode 71 is provided on the capacitor film 18 illustrated in FIG. It may be provided.

(One Modification of Fourth Embodiment)
A bipolar transistor according to a modification of the fourth embodiment of the present invention will be described below with reference to the drawings.

  FIG. 9 shows a cross-sectional configuration of a bipolar transistor according to a modification of the fourth embodiment of the present invention. In FIG. 9, the same members as those of the bipolar transistor of the fourth embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the bipolar transistor of the fourth embodiment, the emitter layer 41 is formed in a mesa shape on the base layer 14, and the second base electrode 72 is provided on the external base region 14 b of the base layer 14. In this modification, as shown in FIG. 9, an emitter layer 81 is provided over the entire surface of the base layer 14, and a laminated film (WSi / Ti / Pt) in which tungsten silicide, titanium, platinum, and gold are sequentially laminated. / Au) is provided on the emitter layer 81 in the vicinity of the emitter contact layer 16, and a laminated film (Pt / Ti / Pt / Au) in which platinum, titanium, platinum and gold are sequentially laminated. The second base electrode 83 is formed so as to penetrate the emitter layer 81 so as to be in contact with the external base region 14 b of the base layer 14.

  According to the bipolar transistor of this modification, since the emitter layer 81 is provided over the entire surface of the base layer 14, recombination of electrons and holes on the surface of the base layer 14 can be reliably prevented. The current gain can be improved.

  In the method of manufacturing the bipolar transistor according to this modification, in the step of forming the base electrode, the step of forming the first base electrode 82 and the step of forming the second base electrode 83 form separate masks. Is possible. Thereafter, after forming the collector electrode, a heat treatment is performed at a temperature of about 400 ° C., so that platinum constituting the lowermost layer of the second base electrode diffuses inside the emitter layer 81 and reaches the base layer. Therefore, the second base electrode 83 is connected to the base layer 14. Since the lowermost layer of the first base electrode 82 is made of tungsten silicide, it does not diffuse into the emitter layer 81 by heat treatment.

  In the fourth embodiment and one modification thereof, it is preferable to use a metal material whose resistance value has a positive correlation with temperature for the second base electrode of the fourth embodiment. As this metal material, for example, an alloy composed of copper and nickel (CuNi) or an alloy composed of nickel and chromium (NiCr) can be used. The base electrode can be formed as a single layer film using any one of these metal materials. Further, in order to improve the adhesion with the semiconductor material constituting the base layer and the like, a laminated film of Ti and CuNi (Ti / CuNi), Cr using titanium (Ti) or chromium (Cr) as an underlayer. Alternatively, it may be formed as a laminated film of CuNi (Cr / CuNi), a laminated film of Ti and NiCr (Ti / NiCr), or a laminated film of Cr and NiCr (Cr / NiCr). In this way, the resistance value of the path through which the direct current flows increases with an increase in temperature, so that the ballast resistance in the base electrode can be increased, so that the thermal stability can be further improved.

  The bipolar transistor and the manufacturing method thereof according to the present invention have a special effect that a bipolar transistor excellent in high frequency characteristics and thermal stability can be realized, and is useful as a high output device for high frequency.

FIG. 2A is a structural sectional view showing a bipolar transistor according to a first embodiment of the present invention, and FIG. 2B is an enlarged view of a part of the bipolar transistor shown in FIG. It is. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the bipolar transistor which concerns on the 1st Embodiment of this invention. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the bipolar transistor which concerns on the 1st Embodiment of this invention. It is a structure sectional view showing a bipolar transistor according to a second embodiment of the present invention. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the bipolar transistor which concerns on the 2nd Embodiment of this invention. It is a structure sectional view showing a bipolar transistor according to a third embodiment of the present invention. (A)-(c) is a structure sectional drawing of the order of a process which shows the manufacturing method of the bipolar transistor which concerns on the 3rd Embodiment of this invention. It is a structure sectional view showing a bipolar transistor concerning a 4th embodiment of the present invention. It is a structure sectional view showing the bipolar transistor concerning the modification of the 4th embodiment of the present invention. (A) is a cross-sectional view showing a conventional bipolar transistor, and (b) is an enlarged view of a part of the bipolar transistor shown in (a) and is superimposed on an equivalent circuit diagram. It is a circuit diagram which shows the high output transistor apparatus using the conventional bipolar transistor.

Explanation of symbols

11 Substrate 12 Collector contact layer 13 Collector layer 14 Base layer (first semiconductor layer)
14a Intrinsic base region 14b External base region 15 Emitter layer (second semiconductor layer)
16 Emitter contact layer 17 Emitter electrode 18 Capacitor film 19 Base electrode 20 Collector electrode 21 Substrate 22 Collector contact layer 23 Collector layer forming layer 23A Collector layer 24 Base layer forming layer (first semiconductor layer)
24A Base layer 25 Emitter layer forming layer (second semiconductor layer)
25A Emitter layer 25B Capacitor film 25C Emitter layer 26 Emitter contact layer formation layer 26A Emitter contact layer 27 Emitter electrode formation layer 27A Emitter electrode 28 First resist pattern 29 Second resist pattern 29a First mask portion (first region)
29b Second mask portion (second region)
30 Third resist pattern 31 Metal film 31A Base electrode 31B Base electrode 31C Upper emitter electrode 32 Collector electrode 41 Emitter layer 41a Emitter region 41b Surface protection region (capacitance film)
51 Second resist pattern 52 Third resist pattern 61 High resistance region 71 First base electrode 72 Second base electrode 81 Emitter layer 82 First base electrode 83 Second base electrode

Claims (11)

A first semiconductor layer having an intrinsic base region and an external base region;
A second semiconductor layer formed on the first semiconductor layer, the portion located on the intrinsic base region being an emitter region or a collector region;
A capacitive film formed on the external base region of the first semiconductor layer and spaced from the second semiconductor layer ;
A base electrode in which one part is formed on the capacitor film on the first semiconductor layer and the other part is connected to the external base region at a part farther from the intrinsic base region than the capacitor film. And a bipolar transistor. A first semiconductor layer having an intrinsic base region and an external base region;
A second semiconductor layer formed on the first semiconductor layer, the portion located on the intrinsic base region being an emitter region or a collector region;
A capacitive film formed on the external base region in the first semiconductor layer;
A base electrode in which one part is formed on the capacitor film on the first semiconductor layer and the other part is connected to the external base region at a part farther from the intrinsic base region than the capacitor film. And
Wherein the other of said external base region in the lower part, the features and to Luba Lee polar transistor that intrinsic base region high resistance region is higher resistance than is provided in the base electrode. The capacitor film bipolar transistor according to claim 1 or 2, characterized in that it consists of the same semiconductor material as the second semiconductor layer. The capacitive film is provided on a region spaced from an end of the external base region opposite to the intrinsic base region,
2. The base electrode is provided on the external base region and the capacitor film so as to straddle an end of the capacitor film opposite to the second semiconductor layer. bipolar transistor according to any one of 1-3. A first semiconductor layer having an intrinsic base region and an external base region;
A second semiconductor layer formed on the first semiconductor layer, the portion located on the intrinsic base region being an emitter region or a collector region;
A capacitive film formed on the external base region in the first semiconductor layer;
A first base electrode formed on the capacitor film;
A second base electrode connected to the external base region,
The first base electrode and the second base electrode are provided on the capacitance film so that the second base electrode is located in a portion farther from the intrinsic base region than the first base electrode. And
The metal material constituting the second base electrode diffuses into the capacitor film made of the same semiconductor material as that of the second semiconductor layer below the second base electrode. electrode, characteristics and to Luba Lee polar transistor that through the capacitive layer is connected to the first semiconductor layer. The bipolar transistor according to claim 5, wherein the second base electrode is provided at a distance from the first base electrode. 6. The capacitor film according to claim 5, wherein the capacitor film is formed on the first semiconductor layer so as to include an end portion of the external base region opposite to the intrinsic base region. 7. The bipolar transistor according to 6. Said second semiconductor layer, the bipolar transistor according to any one of claims 1-7, characterized in that it consists of the first semiconductor material having a band gap larger than the semiconductor layer. The first semiconductor layer is made of a semiconductor material of a first conductivity type,
The capacitor film bipolar transistor according to any one of claims 1-8, characterized in that it consists of a semiconductor material of a second conductivity type. A first step of sequentially forming a first semiconductor layer and a second semiconductor layer on a substrate;
A second step of partitioning a first region to be an emitter region or a collector region and a second region to be a capacitor film from the second semiconductor layer;
A third step of forming a base electrode on the first semiconductor layer so that a part thereof is connected to the first semiconductor layer and another part includes the second region; Prepared ,
The third step includes a step of forming a first base electrode connected to the first semiconductor layer, and a step of forming a second base electrode on the second semiconductor layer,
The third step includes
Forming the first base electrode on the second region using a first metal material;
Forming the second base electrode on the second region using a second metal material so that the second base material is positioned farther from the first region than the first base electrode;
And a step of selectively diffusing the second metal material to connect the second base electrode and the first semiconductor layer . 11. The method of manufacturing a bipolar transistor according to claim 10, wherein in the second step, the second region is partitioned so as to include up to an end portion of the first semiconductor layer.

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