JPH11274167A - Heterojunction bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the drop in current amplification factor during current application caused by the recombination between electrons and holes, in a heterojunction bipolar transistor. SOLUTION: An n-type GaAs collector layer 11 and a p-type GaAs base layer 14 are formed on a GaAs substrate 11, and an n-type AlGaAs passivation layer 15 is formed on a base layer 14. Emitter contact layers 17 and 18 with sectional area smaller than that of the passivation layer 15 are formed on the passivation layer 15. A base electrode 16 is formed on the base layer 14 and on the flank of the passivation layer 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor which suppresses a decrease in current amplification factor during energization.

[0002]

2. Description of the Related Art In recent years, reports have been made using a GaAs heterojunction bipolar transistor (HBT) as an element constituting an optical communication IC or a power amplifier for a portable telephone.

FIG. 19 shows a conventional heterojunction bipolar transistor. 190 is a substrate, 191 is a collector contact layer, 192 is a collector electrode, 193 is a collector layer, 194 is a base layer, 195 is a base electrode, 195 is a wide gap emitter layer, and 197 is an emitter electrode.

It is important to ensure the reliability of the GaAs-based HBT for practical use, but a degradation mode in which the DC current gain (β) decreases during energization has been reported. A decrease in the current amplification factor generally occurs at a portion in contact with the base layer 194 around the wide gap emitter layer 196, that is, at a portion where the pn junction is exposed, since surface recombination of electrons and holes is likely to occur. It is considered.

In order to suppress a decrease in the current amplification factor, FIG.
The following heterojunction bipolar transistor has been proposed. In this heterojunction bipolar transistor, the surface recombination of electrons and holes is suppressed by forming the wide gap emitter layer 201 having a larger cross-sectional area than the emitter contact layer 202. The wide gap emitter layer 201 formed for such a purpose is called a passivation layer.

However, when negative charges adhere to the surface of the passivation layer, as shown in FIG. 21, the band is bent, and the barrier to holes in the base decreases. In such a state, electrons trapped on the surface of the emitter mesa tend to recombine with holes, and the role of the passivation layer is no longer fulfilled.

[0007]

As described above, when negative charges adhere to the surface of the passivation layer, electrons trapped on the surface of the emitter mesa are apt to recombine with holes, and do not serve as a passivation layer. There has been a problem that the DC current gain is reduced.

An object of the present invention is to provide a heterojunction bipolar transistor capable of preventing recombination of electrons and holes and suppressing a decrease in DC current gain during energization.

[0009]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object.

(1) According to the present invention (claim 1), the first conductive type collector layer, the second conductive type base layer and the first conductive type emitter layer are laminated, and the emitter layer is in contact with the base layer. In a heterojunction bipolar transistor formed of a wide gap layer larger than the band gap of the base layer, a base electrode connected to the base layer is in contact with the wide gap emitter layer.

A preferred embodiment of the present invention will be described below.

A collector layer of the first conductivity type, a base layer of the second conductivity type, and an emitter layer of the first conductivity type are stacked, and a part of the emitter layer in contact with the base layer has a band gap larger than that of the base layer. It is formed of a large passivation layer, an etching stopper layer, and a wide gap emitter layer II that is larger than the band gap of the base layer. In a heterojunction bipolar transistor having a larger area, a part of a base electrode connected to the base layer is in contact with at least a passivation layer of the passivation layer and the etching stopper layer.

At least a part of the wide gap emitter layer II is set to a doping concentration necessary to form a ballast resistor.

(2) The present invention (claim 2) comprises a collector layer of the first conductivity type, a base layer including a semiconductor layer of the second conductivity type, and an emitter layer of the first conductivity type. In a heterojunction bipolar transistor having a band gap larger than that of the base layer, the base layer is formed below a wide gap base layer in contact with the emitter layer and a band gap smaller than the wide gap base layer. And a narrow narrow gap layer, and a base electrode penetrating the wide gap layer and connected to the narrow gap layer is formed.

The narrow gap base layer is made of p-type GaAs.
s, and the wide gap base layer is an i-type AlGa
As, and the emitter layer is formed of n-type InGaP.

[Operation] The present invention has the following operation and effects by the above configuration.

According to the present invention, recombination of electrons and holes on the surface of the wide gap emitter layer is prevented by absorbing mobile charges on the surface of the wide gap emitter layer formed of the wide gap material to the base or emitter side. However, it is possible to suppress a decrease in the current amplification factor during energization.

Further, a second conductivity type narrow gap base layer and an undoped wide gap base layer are sequentially laminated as a base layer on the contact layer, and a base electrode penetrating through the wide gap base and connected to the narrow gap base layer is provided. By forming, even if electrons are trapped on the surface of the emitter mesa, holes do not exist in the wide gap base layer. Therefore, recombination of electrons and holes is prevented, and a decrease in current amplification factor during energization is prevented. Can be.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a sectional view showing the structure of a heterojunction bipolar transistor according to a first embodiment of the present invention.

On a GaAs substrate 10, an n ⁺ type GaAs collector contact layer 11 having a thickness of 500 nm and a doping concentration of 6 × 10 ¹⁸ cm ⁻³ is formed. Collector electrode 13 is formed in a predetermined region on collector contact layer 11. On the collector contact layer, an n-type GaAs collector layer 12 having a collector electrode 13 and an opening in a peripheral region thereof is formed.

A 50 nm-thick doping concentration of 5 × 10 ¹⁹ c is formed in a predetermined region on the n-type GaAs collector layer 12.
An m- ³ p-type GaAs base layer 14 is formed. p
In a predetermined region on the base GaAs base layer 14, a film thickness of 50 nm
N-type Al _0.25 Ga with a doping concentration of 3 × 10 ¹⁷ cm ⁻³
_0.75 As passivation layer (wide gap layer) 15
Are formed. A base electrode 16 is formed on the base layer 14 and on the side of the passivation layer 15.

On the passivation layer 15, an n ⁺ -type GaAs emitter layer 17 and an n ⁺ -type InGaAs emitter contact layer 18 each having a smaller cross-sectional area than the passivation layer.
Are sequentially formed. An emitter electrode 19 made of TiW is formed on the InGaAs emitter contact layer 18 so as to have an eaves-like projecting portion. Note that the n-type AlGaAs passivation layer 15,
n ⁺ -type GaAs emitter contact layer 17 and n ⁺ -type I
The nGaAs emitter contact layer 18 forms the emitter layer.

Next, a manufacturing process of the heterojunction bipolar transistor shown in FIG. 1 will be described with reference to FIGS. First, as shown in FIG. 2A, a 500 nm-thick doping concentration of 5 × 10 5 is formed on a GaAs substrate 10.
¹⁸ cm ^-3 n ⁺ -type GaAs collector contact layer 11,
P-type GaAs base layer 14 having a thickness of 500nm doping concentration 5 × 10 ¹⁶ cm n-type GaAs collector layer 12 ^-3, thickness 50nm doping concentration 5 × 10 ¹⁹ cm ^-3, thickness 5
N-type Al with 0 nm doping concentration of 3 × 10 ¹⁷ cm ^-3
_{A 0.25} Ga _0.75 As wide gap emitter layer 21, an n-type GaAs emitter contact layer 17, and an InGaAs emitter contact layer 18 are sequentially epitaxially grown.

Next, TiW is formed on the entire surface by sputtering.
Is formed, a resist of an emitter pattern is formed on the TiW. Then, as shown in FIG. 2B, the TiW is patterned by RIE using the resist as a mask to form an emitter electrode 19.

Next, as shown in FIG. 3C, the GaAs / InGaAs emitter contact layers 17, 18 are etched using a citric acid-based etchant using the emitter electrode 19 as a mask. When a citric acid-based etchant is used, InGaAs and GaAs can be selectively etched with respect to AlGaAs, so that a spacing region can be formed below the emitter electrode 19 by over-etching.

Next, as shown in FIG. 3D, a resist is applied, the entire surface is exposed and developed, and a resist is formed in a spacing region between the emitter electrode 19 and the ends of the emitter contact layers 17 and 18. Embed 22.

Next, as shown in FIG. 4E, the AlGaAs wide gap emitter layer 21 is etched using the resist 22 as a mask to form an Al _0.25 Ga _0.75 As passivation layer 15 and the resist 22 is removed.

After a base pattern resist is formed, Pt, Ti, Pt and Au are sequentially deposited on the emitter electrode 19 to form a base electrode 16. At this time, the base electrode 16
Can be brought into contact with the Al _0.25 Ga _0.75 As passivation layer 15.

Next, as shown in FIG.
Base electrode 16 and GaAs base layer 1 at a heat treatment temperature of
After reacting 4, the base layer is mesa-separated using the base electrode 16 as a mask.

Then, by exposing the collector contact layer and forming a collector electrode made of Au / Pt / Ti / Ni / AuGe, the HBT shown in FIG. 1 is formed.

As shown in FIG. 5, the heterojunction bipolar transistor of this embodiment has a passivation layer
Positively charged particles on the surface can be sucked out to the emitter layer, and negatively charged particles can be sucked out to the base layer 14 via the base electrode 16 via the field plate on the surface of the passivation layer. As a result, surface recombination can be suppressed. it can.

However, when the base electrode 16 is in contact with the passivation layer 15 and a current flows between the emitter and the base through the passivation layer 15, the base leakage current increases. Therefore, Al _0.25 Ga _0.75
The As passivation layer 15 needs to be set to a thickness and a doping concentration that are completely depleted in the operating range of the device.

On the other hand, if the thickness of the passivation layer 15 is too small, the effect of confining holes is reduced, and the heterojunction bipolar transistor cannot function. FIG.
Shows the relationship between the thickness of the passivation layer and the ground emitter current amplification factor β (= I _c / I _b ).

In the heterojunction bipolar transistor of this embodiment, the ground emitter current amplification factor β decreases as the passivation layer becomes thinner. Further, it can be seen that even if the passivation layer is thick, the ground emitter current amplification factor β decreases due to an increase in base leakage current.

FIG. 6 shows that in the case of the heterojunction bipolar transistor of the present embodiment, it is desirable to set the thickness of the passivation layer to about 200 to 350 nm.

[Second Embodiment] As described in the previous embodiment, when the wide gap layer and the passivation layer are the same layer and the base electrode is brought into contact with the passivation layer, the thickness of the passivation layer is reduced. If it is performed too much, the effect of confining holes is reduced and the HBT does not function. Therefore, in this embodiment, an HBT in which the wide gap layer and the passivation layer are separated will be described.

FIG. 7 is a sectional view showing the structure of a heterojunction bipolar transistor according to the second embodiment of the present invention.

An n ⁺ -type GaAs collector contact layer 11 having a doping concentration of 5 × 10 ¹⁸ cm ^-3 and a thickness of 500 nm is formed on a GaAs substrate 10. Collector electrode 13 is formed in a predetermined region on collector contact layer 11. On the collector contact layer, an n-type GaAs collector layer 12 having a collector electrode 13 and an opening in a peripheral region thereof is formed.

Then, a predetermined region on the n-type GaAs collector layer 12 has a thickness of 50 nm and a doping concentration of 5 × 10 ¹⁹ c.
An m- ³ p-type GaAs base layer 14 is formed. An n-type In _0.5 Ga _0.5 P passivation layer 61 having a 30 nm thickness and a 3 × 10 ¹⁷ cm ⁻³ doping concentration is formed in a predetermined region on the base layer 14.
0 ¹⁷ cm ^-3 n-type GaAs etching stopper layers 62 are sequentially stacked. A base electrode 63 is formed on the base layer 14 and on the sides of the passivation layer 61 and the etching stopper layer 62.

An n-type In _0.5 G having a doping concentration of 3 × 10 ¹⁶ cm ^-3 is formed in a predetermined region on the etching stopper layer 62.
An a _0.5 P ballast resistance layer 64, an n ⁺ -type GaAs emitter contact layer 17, and an n ⁺ -type InGaAs emitter contact layer 18 are sequentially stacked.

Then, a WN having an eaves-shaped overhanging portion on the InGaAs emitter contact layer 18 is formed.
Film 65, W film 66, and Au / Pt / Ti / Pt electrode 67
Are sequentially laminated.

Next, the manufacturing process of the HBT shown in FIG. 7 will be described with reference to the process sectional views of FIGS.

First, as shown in FIG.
On the substrate 10, a film thickness of 500 nm and a doping concentration of 5 × 10
¹⁸ cm ^-3 n ⁺ -type GaAs collector contact layer 11,
5 × 10 ¹⁶ cm ⁻³ n-type GaAs collector layer 12 with a film thickness of 500 nm, p-type GaAs base layer 14 with a 50 nm film thickness of 5 × 10 ¹⁹ cm ⁻³ , thickness 3
N-type In _{0.5 with} 0 nm doping concentration of 3 × 10 ¹⁷ cm ⁻³
Ga _0.5 P passivation layer 61, 7.5-nm thick n-type GaAs etching stopper layer 62 with 3 × 10 ¹⁷ cm ⁻³ doping concentration, 50-nm thick doping concentration 3 × 1
0 ¹⁶ cm ^-3 n-type In _0.5 Ga _0.5 P wide gap emitter layer 64, n ⁺ -type GaAs emitter contact layer 1
7. An n ⁺ -type InGaAs emitter contact layer 18 is sequentially epitaxially grown.

Next, after a WN film 65 and a W film 66 are sequentially laminated on the InGaAs emitter contact layer 18 by a sputtering method, an emitter pattern resist is formed. Then, as shown in FIG. 8B, the W film 66 and the WN film 65 are patterned by reactive ion etching (RIE) using the resist as a mask. Below, W
The N / WN laminated film 65,
Write 66.

Next, as shown in FIG. 9C, W / W
GaAs / InGaAs using the N stacked films 65 and 66 as a mask
The emitter contact layers 17, 18 are etched with a phosphoric acid-based etchant. At the time of etching, a spacing region 81 is formed below the W / WN laminated films 65 and 66 by performing over-etching.

Next, as shown in FIG.
Using the s layer 17 as a mask, the InGaP wide gap emitter layer 64 is etched using a hydrochloric acid-based etchant. When InGaP is etched using the GaAs layer 17 as a mask, the etching is completed at the end face of the GaAs layer 17, and even if over-etching is performed, the InGaP layer 64 is removed.
No side etching occurs.

Next, as shown in FIG.
As in the embodiment, a resist 91 is selectively formed in the spacing region 81. Next, as shown in FIG. 10F, the thin GaAs etching stopper layer 62 is etched using the resist 91 as a mask.

After removing the resist 91, FIG.
As shown in (1), the InGaP passivation layer 61 is etched with a hydrochloric acid-based etchant using the GaAs etching stopper layer 62 as a mask. At this stage, InGaP
GaAs having a high surface state density on the passivation layer 61
Since the s layer 62 remains, it is better to remove it by etching as shown in FIG. 13, but it may be used as it is.
In this embodiment, the GaAs layer 62 is left as it is.

Next, as shown in FIG. 11H, a resist of a base pattern is formed, Pt, Ti, Pt and Au are sequentially deposited, and a base electrode 63 and Au / Pt / T are formed.
An i / Pt electrode 67 is formed. The base electrode 63 is also formed on the side of the passivation layer 61 and the etching stopper layer 62.

Next, as shown in FIG.
After the base electrode 63 and the GaAs base layer 14 are reacted at a heat treatment temperature of 0 ° C., the base layer 14 is mesa-separated using the base electrode 63 as a mask.

Thereafter, by exposing the collector contact layer 11 and forming a collector electrode, the HBT shown in FIG. 7 is formed.

According to the present embodiment, in addition to the effects of the first embodiment, the InGaP passivation layer and the InGaP
Since the wide gap emitter layer is separated from the wide gap emitter layer by the GaAs etching stopper layer, it functions as an HBT even if the passivation layer is thinned.

Further, since the doping concentration of the InGaP wide gap emitter layer is set as low as 3 × 10 ¹⁶ cm ⁻³ , the resistance is high and functions as a ballast resistance, so that thermal runaway can be suppressed. If a ballast resistor is not required, it is possible to set a high doping concentration.

FIG. 14 shows the thickness of the passivation layer of the HBT of the present embodiment and the current amplification factor β of the emitter installation.
(= I _c / I _b ).

In the heterojunction bipolar transistor of the present embodiment, unlike the first embodiment, β does not decrease even if the passivation layer is thinned, so that the thickness of the passivation layer can be reduced. The range of setting is widened.

[Third Embodiment] Next, an HBT according to a third embodiment will be described.

FIG. 15 is a sectional view showing the structure of a heterojunction bipolar transistor according to the third embodiment of the present invention.

An n ⁺ -type GaAs collector contact layer 11 having a doping concentration of 5 × 10 ¹⁸ cm ^-3 and a thickness of 500 nm is formed on a GaAs substrate 10. Collector electrode 13 is formed in a predetermined region on collector contact layer 11. N-type GaAs having an opening in the collector electrode 13 and its peripheral region on the collector contact layer 11
An s collector layer 12 is formed.

In a predetermined region on the n-type GaAs collector layer 12, a p-type GaAs base layer 140 (narrow gap layer) having a doping concentration of 5 × 10 ¹⁹ cm ⁻³ , an undoped Al _0.25 Ga _0.75 As base layer (thickness: 10 nm) Wide gap layers) 141 are sequentially stacked. p ^- penetrate the GaAs base layer 140, p-GaAs base layer and the ohmic contact has been the base electrode 142 is formed.

A 30 nm-thick doping concentration of 3 × 10 ¹⁷ cm ⁻³ is formed in a predetermined region on the i-AlGaAs base layer 141.
N type In _0.5 Ga _0.5 P emitter layer 143 with a thickness of 50
n-type In _0.5 G with a doping concentration of 3 × 10 ¹⁶ cm ⁻³ nm
a _0.5 P ballast resistance layer 144, GaAs emitter contact layer 17 and InGaAs emitter contact layer 1
8 are sequentially stacked.

Then, a WN having an eaves-like overhanging portion on the InGaAs emitter contact layer 18 is formed.
Film 65, W film 66 and Pt / Ti / Pt / Au electrode 14
5 are sequentially stacked.

Next, a manufacturing process of the heterojunction bipolar transistor will be described with reference to FIGS.

First, as shown in FIG.
On the s-substrate 10, a film thickness of 500 nm and a doping concentration of 5 × 1
0 ¹⁸ cm ^-3 n-type GaAs collector contact layer 11,
Film thickness 500 nm, doping concentration 5 × 10 ¹⁶ cm ⁻³ n-type G
aAs collector layer 12, film thickness 50 nm, doping concentration 5
× 10 ¹⁹ cm ⁻³ p-type GaAs base layer 140, thickness 1
0 nm undoped Al _0.25 Ga _0.75 As base layer 14
1. n having a thickness of 30 nm and a doping concentration of 3 × 10 ¹⁷ cm ⁻³
In _0.5 Ga _0.5 P emitter layer 143, thickness 50 nm
N-type In _0.5 Ga with a doping concentration of 3 × 10 ¹⁶ cm ⁻³
_0.5 P ballast resistance layer 144, GaAs emitter contact layer 17, and InGaAs emitter contact layer 18
Are sequentially epitaxially grown.

Next, as shown in FIG. 16B, similarly to the previous embodiment, after laminating the WN film 65 and the W film 66, they are processed into an emitter electrode shape. Then, using the W / WN films 65 and 66 as masks, the InGaAs / GaAs emitter contact layers 17 and 18 are etched with a phosphoric acid-based etchant. At this time, by performing over-etching, a spacing region is formed below the emitter metal. Then, the InGaP ballast resistance layer 144 and the InGaP emitter layer 143 are etched with a hydrochloric acid-based etchant to form a wide gap i-Al _0.25 Ga _0.75 As.
The base layer 141 is exposed.

Next, as shown in FIG. 17C, a resist of a base pattern is formed, and Pt, Ti, Pt and Au are sequentially deposited to form an Au / Pt / Ti / Pt electrode 14.
5 is formed.

Next, as shown in FIG.
By performing a heat treatment at 0 ° C., the Au / Pt / Ti / Pt electrode 1
Diffusion of Pt in the Pt layer formed at the bottom of
A base electrode 142 in ohmic contact with the aAs base layer 140 is formed. Note that Au / Pt / Ti / P
The thickness of the Pt layer formed at the lowermost layer of the t electrode 145 is i−
By making the thickness of the Al _0.25 Ga _0.75 As layer more than twice as large as 10 nm, the Pt layer diffuses into the GaAs base layer 14,
A base electrode 142 in ohmic contact with the base layer 140 is formed. This is because Pt and As form a thermally stable intermetallic compound, and when a reaction layer having a thickness of about twice the thickness of Pt is formed, the reaction layer does not spread any more.

After that, the base layer is mesa-separated using the base electrode as a mask. Thereafter, the collector contact layer is exposed, and the collector electrode AuGe / Ni / Ti / Pt / Au
Is deposited to form the heterojunction bipolar transistor shown in FIG.

According to the heterojunction bipolar transistor of this embodiment, the undoped and wide-gap AlGaAs base layer connected to the emitter layer serves as a heterobarrier, so that the holes are made of i-type AlGaAs as shown in FIG.
The surface defects of the s base layer 141 do not reach. Therefore, even if electrons are trapped on the surface of the base layer 141, recombination with holes is suppressed, so that a decrease in the electron amplification factor can be suppressed.

The present invention is not limited to the above embodiment, but can be implemented in various modifications without departing from the spirit of the invention.

[0071]

As described above, according to the present invention, by adhering the base electrode to the passivation layer formed on the base layer, the adhesion of charged particles on the surface of the passivation layer can be prevented, and electrons and holes can be prevented. Recombination can be suppressed.

Further, a second conductivity type narrow gap layer and an undoped wide gap layer are sequentially laminated as a base layer on the contact layer, and a base electrode penetrating through the wide gap and connecting to the narrow gap layer is formed. Recombination of electrons and holes can be prevented, and a decrease in current amplification factor during energization can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a heterojunction bipolar transistor according to a first embodiment.

FIG. 2 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 1;

FIG. 3 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 1;

FIG. 4 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 1;

FIG. 5 is a diagram illustrating the operation of the heterojunction bipolar transistor according to the first embodiment.

FIG. 6 is a diagram showing the dependency of a grounded emitter current amplification factor β of the heterojunction bipolar transistor of FIG. 1 on the thickness of a passivation layer.

FIG. 7 is a diagram showing a configuration of a heterojunction bipolar transistor according to a second embodiment.

FIG. 8 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 7;

FIG. 9 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 7;

FIG. 10 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 7;

FIG. 11 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 7;

FIG. 12 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 7;

FIG. 13 is a diagram illustrating another step of FIG.

FIG. 14 is a diagram showing the dependency of the grounded emitter current gain β of the heterojunction bipolar transistor of FIG. 7 on the thickness of the passivation layer.

FIG. 15 is a sectional view showing a configuration of a heterojunction bipolar transistor according to a third embodiment.

FIG. 16 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 15;

FIG. 17 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor of FIG. 15;

FIG. 18 is a diagram illustrating the operation of the heterojunction bipolar transistor according to the third embodiment.

FIG. 19 is a sectional view showing a configuration of a conventional heterojunction bipolar transistor.

FIG. 20 is a cross-sectional view showing a configuration of a conventional heterojunction bipolar transistor different from FIG. 19;

FIG. 21 illustrates a problem of the heterojunction bipolar transistor of FIG. 20;

[Explanation of symbols]

REFERENCE SIGNS LIST 10 GaAs substrate 11 n ⁺ -type GaAs collector contact layer 12 n-type GaAs collector layer 14 p-type GaAs base layer 15 n-type Al _0.25 Ga _0.75 As passivation layer (wide gap layer) 16 base electrode 17 n-type GaAs emitter layer 18 InGaAs emitter contact layer 19 emitter electrode 21 wide gap emitter layer 22 resist 61 InGaP passivation layer 62 GaAs etching stopper layer 63 base electrode 64 InGaP wide gap emitter layer 65 WN film 66 W film 67 Au / Pt / Ti / Pt electrode 81 Spacing region 91 Resist 140 p-type GaAs base layer (narrow gap base layer) 141 i-type AlGaAs base layer (wide gap base layer) 1 2 ... base electrode 143 ... n ⁺ -type InGaP emitter layer 144 ... n type InGaP ballast resistor layer 145 ... Au / Pt / Ti / Pt electrodes

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tetsuro Nozu 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research and Development Center Co., Ltd. (72) Inventor Kohei Morizuka Kochi Mukai Toshiba-cho, Kawasaki-shi, Kanagawa 1st place Toshiba R & D Center

Claims (2)

[Claims] A first conductive type collector layer, a second conductive type base layer, and a first conductive type emitter layer, wherein the emitter layer in contact with the base layer has a band gap of the base layer. A hetero-junction bipolar transistor formed of a larger wide-gap emitter layer, wherein a base electrode connected to the base layer is in contact with the wide-gap emitter layer. 2. A semiconductor device comprising a collector layer of a first conductivity type, a base layer including a semiconductor layer of a second conductivity type, and an emitter layer of a first conductivity type, wherein a band gap of the emitter layer is larger than that of the base layer. In the heterojunction bipolar transistor, the base layer includes a wide gap base layer in contact with the emitter layer, and a narrow gap layer formed below the wide gap base layer and having a narrower band gap than the wide gap layer. A heterojunction bipolar transistor, wherein a base electrode penetrating through a wide gap layer and connected to the narrow gap layer is formed.