JP2000082709A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent short-circuiting between base emitters due to contact of the base electrode and an n-type emitter layer. SOLUTION: An emitter electrode of two layer structures of the firstemitter electrode 61 and the second emitter electrode 62 having expanded pattern size in comparsion with the electrode 61 is used. By using the first emitter electrode 61 as a mask, formation of the n-type emitter layer 4 outside the first emitter elect rode 61 is prevented. By self-matching formation of the base electrode 8 for the second emitter electrode 6, the base electrode 8 can be formed outside the first emitter electrode 61. As a result, the base electrode and the n-type emitter layer are formed away from the base electrode and the n-type emitter layer, and the base electrode and the n-type emitter layer do not come in contact with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device including a heterojunction bipolar transistor.

[0002]

2. Description of the Related Art As one of semiconductor devices, there has been known a bipolar transistor using a semiconductor layer having a band gap larger than that of a base layer as an emitter layer, that is, a heterojunction bipolar transistor. The heterojunction bipolar transistor has an advantage that the CR time constant can be reduced or the base transit time can be shortened as compared with a normal bipolar transistor.

FIG. 9 is a process sectional view of a conventional method for manufacturing a heterojunction bipolar transistor. First, FIG.
(A), the on semi-insulating GaAs substrate 61, n ⁺ -type GaAs layer 62 serving as n ⁺ -type collector layer,
A p-type GaAs layer 63 serving as a p-type base layer, an n-type AlGaAs layer 64 serving as an n-type emitter layer, and an n ⁺ -type GaAs layer 65 serving as an n ⁺ -type contact layer are sequentially epitaxially grown.

[0004] Next, as shown in FIG. 9 (b), n ⁺ -type Ga
After a tungsten nitride film serving as the emitter electrode 66 is deposited on the As layer 65, the tungsten nitride film is processed using photolithography and etching to form the emitter electrode 66.

Next, as shown in FIG. 9C, the n ⁺ -type GaAs layer 6 is formed by wet etching using a phosphoric acid-based etchant using the emitter electrode 66 as a mask.
5. The n-type AlGaAs layer 64 is etched to form an n ⁺ -type contact layer 65 and an n-type emitter layer 66.

Next, after an insulating film (not shown) having a base opening formed by itself with respect to the emitter electrode 66 is formed on the entire surface, as shown in FIG.
7 is formed in self-alignment with the emitter electrode 66 by vacuum evaporation. At this time, the base electrode 67 is also formed on the emitter electrode 66.

Thereafter, the p-type GaAs layer 63 is patterned to form a p-type base layer, and the n ⁺ -type GaAs layer (n ⁺
A collector electrode (not shown) is formed on the (type collector layer) 62 to complete a heterojunction bipolar transistor.

[0008] However, this conventional method is not shown in FIG.
In the step (d), since the base electrode 67 is formed very close to the n-type AlGaAs layer (n-type base layer) 64, as shown in FIG. There is a possibility that the base and the emitter may come into contact with each other, and this contact causes a short circuit between the base and the emitter.

FIG. 10 is a process sectional view showing another conventional method of manufacturing a heterojunction bipolar transistor. This shows a method for manufacturing a heterojunction bipolar transistor having a ledge layer.

[0010] First, as shown in FIG. 10 (a), on a semi-insulating GaAs substrate 71, p-type a n ⁺ -type GaAs layer 72, p-type base layer of the n ⁺ -type collector layer GaA
s layer 73, n-type InGaP serving as n-type ledge layer (shelf layer)
Layer 74, n-type GaAs layer 7 serving as n-type first emitter layer
5. An n ⁺ -type InGaAs layer 76 serving as an n ⁺ -type second emitter layer is sequentially epitaxially grown.

[0011] Then, as shown in FIG. (A), n ⁺ -type In
A first emitter electrode 77 made of a tungsten nitride film and a second emitter electrode 78 made of a tungsten film are formed on the GaAs layer 76 by using photolithography and etching.

Next, as shown in FIG. 10B, the n-type GaAs layer 75 and the n ⁺ -type InGaAs layer 7 are formed by using the first emitter electrode 77 and the second emitter electrode 78 as a mask.
By wet-etching 6, an n-type first emitter layer 75 and an n ⁺ -type second emitter layer 76 are formed. At this time, a void 79 is formed on the side wall of the n-type first emitter layer 75 and the n ⁺ -type second emitter layer 76.

Next, as shown in FIG.
Is embedded in a resist layer 80. Next, as shown in FIG. 10D, using the resist layer 80 as a mask, n-type InGa
The n-type ledge layer 74 is formed by wet-etching the P layer 74. After that, the resist layer 80 is peeled off.

Next, after forming an insulating film (not shown) having a base opening formed on the first emitter electrode 77 and the second emitter electrode 78 over the entire surface, the insulating film shown in FIG.
As shown in (e), the base electrode 81 is formed in self-alignment with the first emitter electrode 77 and the second emitter electrode 78 by vacuum evaporation. At this time, the base electrode 81 is also formed on the second emitter electrode 78.

However, in this conventional method, FIG.
Since the base electrode 81 is formed very close to the n-type ledge layer 77 in the step (e), there is a possibility that the base electrode 81 comes into contact with the n-type ledge layer 77 as shown in FIG. There is a problem that this contact causes a short circuit between the emitter and the base.

[0016]

As described above, in the conventional heterojunction bipolar transistor, the contact between the base and the emitter is caused by the contact between the base electrode and the n-type emitter layer or the contact between the base electrode and the n-type ledge layer. There was a problem of short circuit.

The present invention has been made in view of the above circumstances, and an object thereof is to prevent a short circuit between a base and an emitter due to contact between a layer below an emitter electrode such as an emitter layer and a base electrode. It is an object of the present invention to provide a semiconductor device having a heterojunction bipolar transistor that can be prevented.

[0018]

Means for Solving the Problems [Structure] To achieve the above object, a semiconductor device according to the present invention (claim 1)
A first conductive type collector layer, a second conductive type base layer provided on the collector layer, and a first conductive type including a semiconductor layer provided on the base layer and having a larger band gap than the base layer. A first emitter electrode provided on the emitter layer, a second emitter electrode provided on the first emitter electrode, and having a pattern size enlarged with respect to the first emitter electrode; A base electrode provided on the base layer and formed in self-alignment with the second emitter electrode.

Here, it is preferable to use a tungsten nitride film having a nitrogen content of 5% or more and 40% or less as the first emitter electrode, and to use a tungsten film as the second emitter electrode.

The semiconductor device according to the present invention (claim 3) has a first conductivity type collector layer, a second conductivity type base layer provided on the collector layer, and a second conductivity type base layer provided on the base layer. A first conductive type ledge layer, a first conductive type emitter layer including a semiconductor layer provided on the ledge layer and having a larger band gap than the base layer, and provided on the emitter layer; An emitter electrode having a pattern size enlarged with respect to the ledge layer and the emitter layer,
A base electrode provided on the base layer and formed in a self-aligned manner with respect to the emitter electrode.

[Operation] In the case of the present invention (claims 1 and 2),
The layer below the first emitter electrode can be formed by wet etching using the first emitter electrode as a mask.
Therefore, a layer below the first emitter electrode can have a smaller pattern size than the first emitter electrode.

Therefore, as in the present invention, if the pattern size of the second emitter electrode is enlarged with respect to the first emitter electrode, the base electrode which does not come into contact with a layer below the first emitter electrode is formed as the first emitter electrode. Since the two emitter electrodes can be formed in a self-aligned manner, a short circuit between the base and the emitter can be prevented.

In an actual process, the second emitter electrode whose pattern size is enlarged with respect to the first emitter electrode is not formed, but the first emitter whose pattern size is reduced with respect to the second emitter electrode is formed. Form electrodes. Further, the pattern size of the second emitter electrode does not need to be uniformly enlarged over the entire pattern. For example, in the case of a rectangular pattern, the magnification may be different between the long side and the short side.

Further, when the pattern size of the emitter electrode is enlarged relative to the ledge layer as in the present invention (claim 3), the base electrode which does not contact the ledge layer is self-aligned with the emitter electrode. Therefore, short circuit between the base and the emitter can be prevented.

In the actual process, an emitter electrode having a reduced pattern size is formed on the emitter electrode instead of forming an emitter electrode having an enlarged pattern size on the ledge layer. Further, the pattern size of the emitter electrode does not need to be uniformly enlarged over the entire pattern.

[0026]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) First, the experimental results on which this embodiment is based will be described. As shown in FIG. 1, the present inventors examined the side etching amount of the tungsten nitride film when the laminated film of the tungsten nitride film / tungsten film was over-etched by RIE using a resist pattern as a mask.

As a result, it was found that the amount of side etching of the tungsten nitride film varies greatly depending on the nitrogen content of the tungsten nitride film. FIG. 2 shows the result of examining the relationship between the over-etching time and the side etching amount, which indicates this.

From the figure, it can be seen that the side etching amount increases in proportion to the over-etching time regardless of the nitrogen content, but the tungsten nitride film with a nitrogen content of less than 5% and the nitrided film with a nitrogen content of more than 40% It can be seen that the tungsten film has a sufficiently small increase in the amount of side etching as the overetching time elapses, as compared with a tungsten nitride film having a nitrogen content of 5% or more and 40% or less.

Therefore, in the case of a tungsten nitride film having a nitrogen content of less than 5% and a tungsten nitride film having a nitrogen content of more than 40%, a desired side etching amount necessary for short-circuit prevention is considered in consideration of a reduction in the film thickness of the resist pattern. That is, the side etching amount required for preventing short circuit between the base and the emitter does not reach 0.15 μm.

On the other hand, the nitrogen content is 5% or more and 40%
In the case of the following tungsten nitride film, the amount of side etching greatly increases with the elapse of the overetching time, and since the overetching time and the side etching amount are in a proportional relationship, the desired side etching is controlled by controlling the overetching time. The amount of etching can be easily obtained.

The relationship between the over-etching time and the side etching amount in FIG. 2 is as follows. A mixed gas of CF ₄ gas and oxygen gas is used as an etching gas, the flow rate of CF ₄ gas is 20 cc / min, and the flow rate of oxygen gas is 10 cc. / Mi
n, a pressure of 0.7 Pa, and an RF power of 200 W. The relationship between the overetching time, the side etching amount, and the nitrogen content described above can be seen under other etching conditions. Confirmed that there is no.

FIG. 3 is a sectional view of a heterojunction bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a process sectional view showing the method for manufacturing the same heterojunction bipolar transistor.

[0033] The heterojunction bipolar transistor, the second has an emitter electrode 6 ₂ of the pattern size with respect to the first emitter electrode ₆₁ is enlarged, further self-aligned manner with respect to the second emitter electrode 6 ₂ It has the formed base electrode 8. Also, the first emitter electrode 6
It is formed by a ₁ in the mask, and a n-type emitter layer 4 and the n ⁺ -type collector layer 5 that is not the first outside of the emitter electrode ₆₁ there. As a result, the base electrode 8 on the p-type base layer 3 is formed apart from the n-type emitter layer 4 and the n ⁺ -type contact layer 5, and a short circuit between the emitter and the base is prevented.

[0034] Such a structure, as the first, second emitter electrode 6 _1, 6 ₂ become conductive film, the nitrogen content 5-4
By using a stacked film of 0% tungsten nitride film / tungsten film, it can be easily formed as described below.

[0035] First, as shown in FIG. 4 (a), on a GaAs substrate 1 of semi-insulating, n as n ⁺ -type collector layer ⁺
-Type GaAs layer 2, p-type GaAs layer 3 serving as a p-type base layer, n-type AlGaAs layer 4 serving as an n-type emitter layer, n ⁺
An n ⁺ -type GaAs layer 5 serving as a type contact layer is sequentially epitaxially grown.

[0036] Then, as shown in FIG. 4 (b), n ⁺ -type Ga
The nitrogen content of the first emitter electrode on the As layer 5 is 5 to 5.
40% of the tungsten nitride film _61, after the tungsten film 6 ₂ serving as the second emitter electrode are sequentially deposited, forming a photoresist pattern 7 on the tungsten film 6 _2.

Next, as shown in FIG. 4C, using the photoresist pattern 7 as a mask, the tungsten nitride film 6 is formed.
₁ and a tungsten film 6 ₂ over-etched by RIE, to form the first emitter electrode ₆₁ and the second emitter electrode 6 _2. After that, the photoresist pattern 7
Is peeled off. The photoresist pattern 7 may be peeled off after the next step of FIG. 4D.

The first emitter electrode ₆₁ in the width (lateral dimension in the drawing) becomes narrower than that of the second emitter electrode 6 ₂ (reduced), the first emitter electrode ₆₁ and the second emitter electrode 6 Formed inside ₂ By over-etching time 3 minutes, the amount of side etching of the tungsten nitride film ₆₁ becomes the desired about 0.15 [mu] m.

The width of the first emitter electrode 61 may be smaller than or equal to that of the conventional _one . However, the contact area between the first emitter electrode ₆₁ and the n ⁺ -type GaAs layer (contact layer) 5 is the same.

[0040] Next, as shown in FIG. 4 (d), using the first emitter electrode ₆₁ as a mask, by wet etching using an etchant of phosphoric acid, n ⁺ -type GaAs layer 5, n-type AlGaAs layer 4 Is etched to form an n ⁺ -type contact layer 5 and an n-type emitter layer 4.

[0041] In this case, n ⁺ -type contact layer 5, n-type wide emitter layer 6 (lateral dimension in the drawing) is defined by the first emitter electrode _61, inside the second emitter electrode 6 ₂ It is formed.

Next after forming an insulating film having a base opening which is self-formed (not shown) on the entire surface to the second emitter electrode 6 _2, as shown in FIG. 4 (e), Au film /
A base electrode 8 made of a laminated film of a Ti film / Pt film is formed by vacuum evaporation.

[0043] At this time, since the base electrode 8 on the p-type GaAs layer 3 are formed in self-alignment with the second emitter electrode 6 _2, n ⁺ -type contact layer 5, n-type emitter layer 4
Never touch.

Thereafter, p-type GaAs is formed according to a well-known method.
The p-type base layer 3 is formed by patterning the s-layer 3, and then the collector electrode 9 is formed on the n ⁺ -type GaAs layer (n ⁺ -type collector layer) 2 to form the heterojunction bipolar transistor shown in FIG. Is completed.

[0045] According to the present embodiment as described above, in the step of FIG. 4 (c), the first emitter electrode ₆₁ narrower than the second emitter electrode 6 ₂ is formed, that is, the second emitter electrode 6 First pattern size reduced for ₂
Emitter electrode ₆₁ is formed, in the step of FIG. 4 (d), the can form a n ⁺ -type contact layer 5 and the n-type emitter layer 6 as defined in the first width at the emitter electrode _61, and FIG. in steps 4 (e), a base electrode 8 on the p-type GaAs layer 3 can be formed in a self-aligned manner with respect to the second emitter electrode 6 _2.

Therefore, according to the present embodiment, the base electrode 8 that does not contact the n ⁺ -type contact layer 5 and the n-type emitter layer 6 can be reliably formed on the p-type GaAs layer 3, and a short circuit between the base and the emitter can occur. A prevented heterojunction bipolar transistor can be realized. In this embodiment, a single emitter layer is used. However, a multilayer emitter layer including a semiconductor layer having a larger band gap than the base layer may be used. (Second Embodiment) FIG. 5 is a sectional view of a heterojunction bipolar transistor according to a second embodiment of the present invention. 6 and 7 are process sectional views showing a method for manufacturing the same heterojunction bipolar transistor.

This heterojunction bipolar transistor is of a type having an n-type ledge layer 14. Further, this heterojunction bipolar transistor has a first and a first pattern in which the pattern size is enlarged with respect to the n-type ledge layer 14.
It has second emitter electrodes 17 and 18 and further has a base electrode 25 formed in self-alignment with these first and second emitter electrodes 17 and 18. As a result, the base electrode 25 on the p-type base layer 13 is formed apart from the n-type ledge layer 14, and a short circuit between the emitter and the base is prevented.

Such a structure is formed on the side walls of the first and second emitter electrodes 17 and 18 as a mask used when etching the n-type InGaP layer to be the n-type ledge layer 14, and Second emitter electrodes 17, 18
By using the resist layer formed on the inner side, the film can be easily formed as described below.

First, as shown in FIG. 6A, an n ⁺ -type collector layer is formed on a semi-insulating GaAs substrate 11.
⁺ Type GaAs layer 12, thickness 50 nm to be p-type base layer
P-type GaAs layer 13, n-type InGaP layer 14 having a thickness of 30 nm to be an n-type ledge layer (shelf layer), n-type GaAs layer 15 having a thickness of 100 nm to be an n-type first emitter layer, and n ⁺ -type second layer 100 nm-thick n ⁺ -type InGa serving as an emitter layer
The As layer 16 is sequentially epitaxially grown.

[0050] Then, as shown in FIG. (A), n ⁺ -type In
On the GaAs layer 16, a thickness of 100 to serve as a first emitter electrode
nm, a 200 nm thick tungsten film 18 serving as a second emitter electrode, and a 300 nm thick film.
after sequentially depositing the SiO ₂ film 19 m, SiO ₂ film 19
A photoresist pattern 20 having a thickness of 1 μm and a width of 2 μm (= emitter width) is formed thereon.

Next, as shown in FIG. 6B, using the photoresist pattern 20 as a mask, the SiO ₂ film 19, the tungsten film 18, and the tungsten nitride film 17 are sequentially etched by RIE to have vertical side walls. A first emitter electrode 18 and a second emitter electrode 19 are formed. Thereafter, the photoresist pattern 20 and the SiO ₂ film 19 are formed.
Is removed.

Here, the RIE conditions for the SiO ₂ film 19 are as follows:
For example, the etching gas is a mixed gas of CF ₄ gas and H ₂ , the flow rate of CF ₄ / H ₂ is 20/10 SCCM, the RF power is 200 W, and the gas pressure is 7 Pa.

The RIE conditions for the tungsten film 18 include, for example, an etching gas of a mixed gas of CF ₄ gas and O ₂ , a flow rate of CF ₄ / O _{2 of} 20/10 SCCM, an RF power of 300 W, and a gas pressure of 5 Pa. .

Then, RIE of the tungsten nitride film 17 is performed.
The conditions are, for example, that the etching gas is a mixed gas of CF ₄ gas and O ₂ , the flow rate of CF ₄ / O ₂ is 20/10 SCCM, R
The F power is 150 W and the gas pressure is 7 Pa.

Next, as shown in FIG. 6C, the n-type GaAs layer 15 and the n-type InGaAs layer 16 are formed by using the first emitter electrode 18 and the second emitter electrode 19 as a mask.
Is wet-etched using a phosphoric acid-based etchant, so that the n-type first emitter layer 15 and n ⁺
A second emitter layer 16 is formed.

At this time, the n-type GaAs layer 15 and the n-type InGaAs layer 16 under the peripheral portions of the first emitter electrode 18 and the second emitter electrode 19 are also etched away, so that the n-type first emitter layer 15 and the n ⁺ -type A void 21 is formed on the side wall of the second emitter layer 16.

Next, as shown in FIG. 6D, the space 21 is filled with a resist layer 22. To form the resist layer 22, first, a positive photoresist is applied to the entire surface,
Next, the entire surface of the photoresist is exposed, and the photoresist is developed.

Next, as shown in FIG. 7E, the resist layer 22 is side-etched by RIE by about 0.15 μm. The RIE conditions for the resist layer 22 are, for example, an etching gas of O ₂ gas, a flow rate of 10 SCCM, an RF power of 100 W, and a pressure of 5 Pa.

FIG. 8 shows the relationship between the amount of side etching of the resist layer 22 by RIE using O ₂ gas and the etching time. From the figure, it can be seen that the side etching amount increases linearly as the etching time increases, and the etching rate is constant. The reproducibility was also confirmed. Therefore, the amount of side etching can be accurately controlled by the etching time. Thus, by controlling the etching time, a desired side etching amount (here, about 0.15 μm) can be reliably realized.

Next, as shown in FIG. 7F, the n-type InGaP layer 14 is wet-etched using the resist layer 22 as a mask and a hydrochloric acid-based etchant to thereby form the first emitter electrode 18 and the second emitter electrode 18. Electrode 19
The n-type ledge layer 14 is formed on the inner side of the peripheral portion of. That is, the ledge layer 14 having a reduced pattern size with respect to the first emitter electrode 18 and the second emitter electrode 19
To form

The width of the ledge layer 14 (the dimension in the horizontal direction in the figure)
Is defined by the width of the resist layer 22. The width of the resist 22 is defined by the amount of side etching. The amount of side etching can be accurately controlled by the etching time as described above. Therefore, the ledge layer 14 having a desired width can be reliably formed. The ledge layer 14 has a role of protecting the interface between the p-type GaAs layer (base layer) 13 and the n-type first emitter layer 15 and improving the reliability of the device.
As shown in (g), after depositing an SiO ₂ film 23 on the entire surface, a photoresist pattern 24 for forming a base opening is formed.

Next, as shown in FIG. 7 (h), the SiO ₂ film 23 is wet-etched using the photoresist pattern 24 as a mask to form a base opening in the SiO ₂ film 23. A base electrode 2 composed of a laminated film of, for example, an Au film / Ti film / Pt film on a GaAs layer.
5 is formed by vacuum deposition on the first emitter electrode 17 and the second
It is formed in a self-aligned manner with respect to the emitter electrode 18.

At this time, since the ledge layer 14 exists inside the peripheral portions of the first emitter electrode 18 and the second emitter electrode 19, the base electrode 25 can be prevented from contacting the ledge layer 14. Therefore, a short circuit between the emitter and the base can be prevented.

Thereafter, the photoresist pattern 24 and the SiO ₂ film 23 are removed, and then the p-type GaAs layer 13 is patterned according to a well-known method to form a p-type base layer 13, and then the n ⁺ -type GaAs A collector electrode 26 is formed on the layer (n ⁺ -type collector layer) 12 to complete the heterojunction bipolar transistor shown in FIG.

In this embodiment, a multilayer emitter layer including a semiconductor layer having a band gap larger than that of the base layer is used. However, a single emitter layer composed of only a semiconductor layer having a band gap larger than the base layer is used. May be used. Further, the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the gist of the present invention.

[0066]

As described above in detail, according to the present invention, a semiconductor having a heterojunction bipolar transistor capable of preventing a short circuit between a base and an emitter due to contact between a layer below an emitter electrode such as an emitter layer and a base electrode. The device can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a sample used for checking a side etching amount of a tungsten nitride film.

FIG. 2 is a characteristic diagram showing a relationship between a side etching amount and an over-etching time for a tungsten nitride film.

FIG. 3 is a cross-sectional view of the heterojunction bipolar transistor according to the first embodiment of the present invention.

FIG. 4 is a process sectional view showing the method for manufacturing the heterojunction bipolar transistor.

FIG. 5 is a sectional view of a heterojunction bipolar transistor according to a second embodiment of the present invention.

FIG. 6 is a process sectional view showing the first half of the method of manufacturing the heterojunction bipolar transistor;

FIG. 7 is a process sectional view showing the latter half of the method for manufacturing the same heterojunction bipolar transistor.

FIG. 8 is a characteristic diagram showing a relationship between a side etching amount of a resist layer and an etching time by RIE using O ₂ gas.

FIG. 9 is a process sectional view showing a method for manufacturing a conventional heterojunction bipolar transistor.

FIG. 10 is a process cross-sectional view showing another conventional method of manufacturing a heterojunction bipolar transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... GaAs substrate 2 ... n ⁺ type GaAs layer (n ⁺ type collector layer) 3 ... p type GaAs layer (p type base layer) 4 ... n type AlGaAs layer (n type emitter layer) 5 ... n ⁺ type GaAs layer ( n ⁺ -type contact layer) 6 ₁ tungsten nitride film (first emitter electrode) 6 ₂ ... tungsten film (second emitter electrode) 7 ... photoresist pattern 8 ... base electrode 9 ... a collector electrode 11 ... GaAs substrate 12 ... n ⁺ -type GaAs layer (n ⁺ -type collector layer) 13 ... p-type GaAs layer (p-type base layer) 14 ... n-type InGaP layer (n-type ledge layer) 15 ... n-type GaAs layer (n-type first emitter layer) 16 ... n ⁺ -type InGaAs layer (n ⁺ -type second emitter layer) 17 ... tungsten nitride film (first emitter electrode) 18 ... tungsten film (second emitter electrode) 19 ... SiO ₂ film 20 ... photo-resist pattern Action 21 ... gap 22 ... resist layer 23 ... SiO ₂ film 24 ... photo-resist pattern 25 ... base electrode 26 ... a collector electrode

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoshiaki Kitaura 1-Family Toshiba R & D Center, Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture 5F003 AP02 BA92 BF05 BH08 BH99 BM03 BP12 BS04 BS07 BS08

Claims (3)

[Claims] 1. A collector layer of a first conductivity type, a base layer of a second conductivity type provided on the collector layer, and a semiconductor layer provided on the base layer and having a larger band gap than the base layer A first conductive type emitter layer including: a first emitter electrode provided on the emitter layer; a second emitter layer provided on the first emitter electrode and having a pattern size enlarged with respect to the first emitter electrode. A semiconductor device comprising: an emitter electrode; and a base electrode provided on the base layer and formed in a self-aligned manner with respect to the second emitter electrode. 2. The method according to claim 1, wherein the first emitter electrode has a nitrogen content of 5%.
2. The semiconductor device according to claim 1, comprising a tungsten nitride film of not less than 40% and not more than 40%. 3. A collector layer of a first conductivity type; a base layer of a second conductivity type provided on the collector layer; a ledge layer of a first conductivity type provided on the base layer; A first conductivity type emitter layer including a semiconductor layer having a larger band gap than the base layer, and an emitter electrode provided on the emitter layer and having a pattern size enlarged with respect to the ledge layer; And a base electrode provided on the base layer and formed in self-alignment with the emitter electrode.