JP5878739B2 - Varactor diode and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a technique for improving the characteristics of a varactor diode manufactured on a semiconductor substrate and a semiconductor integrated circuit including the varactor diode.

  A phase lock method (PLL method) is employed as a stable high frequency variable frequency signal generator. The PLL signal generator includes a voltage controlled oscillator (VCO), a phase control circuit, and the like, and a bipolar transistor (hereinafter referred to as BT) or a field effect transistor (hereinafter referred to as BT) is used as a semiconductor element for configuring these circuits. Hereinafter, a varactor diode is essential. Further, in order to cope with the higher speed and higher frequency of circuits that are required every year, it is necessary to improve the performance of BT and FET, and a heterojunction BT (hereinafter referred to as HBT) manufactured on a compound semiconductor substrate. ) And heterojunction FETs (hereinafter referred to as HFETs) are suitable.

  Comparing the performance of HBTs or HFETs fabricated on GaAs (gallium arsenide) substrates and HBTs or HFETs fabricated on InP (indium phosphorus) substrates, the latter is superior because of its good electron transport properties Therefore, it is easy to cope with high speed and high frequency.

  In order to expand the oscillation frequency range of the VCO and the phase control range of the phase control circuit, it is necessary to expand the variable capacitance range while reducing the leakage current and parasitic resistance of the varactor diode. In addition, from the viewpoint of ease of use, it is necessary to ensure linearity in CV (voltage vs. capacity) characteristics and to reduce the control voltage range necessary for varying the capacity. Furthermore, in consideration of monolithic integration of HBT or HFET and a varactor diode, it is desirable to reduce the entire area and reduce the area occupied by the varactor diode.

  When configuring a VCO or phase control circuit, generally, a method is used in which an integrated circuit consisting of transistors and a varactor diode are separately manufactured and hybridly integrated. Not only becomes difficult, but also increases the cost.

  In order to solve this, there is a method of monolithically integrating a transistor and a varactor diode on a common semiconductor substrate. In this case, the following two methods are conceivable.

  The first method is limited to the case where the transistor is an HBT, but is a method of using either the emitter-base junction or the base-collector junction of the HBT or the pn junction of both as a varactor diode. According to this method, it is not necessary to grow an additional layer other than the HBT in the crystal growth, and it is possible to manufacture a varactor diode by an HBT manufacturing process only by changing a mask pattern in an integrated circuit manufacturing process. Although having an advantage, it is difficult to achieve both the high speed of the HBT and the expansion of the variable capacity range of the varactor.

  In the second method, a layer for manufacturing a varactor diode is grown on (or under) a layer for manufacturing an HBT or HFET, and a manufacturing process of the varactor diode is performed as a manufacturing process of the HBT or HFET. It is a method to add. This method complicates the crystal growth and manufacturing process, but it is possible to independently optimize the layer structure of each transistor and batactor diode.

  A technique for providing a layer for forming a varactor diode on top of a layer for forming a transistor in this manner is disclosed in, for example, Patent Document 1. This document technology relates to a technique for forming a varactor diode and a transistor by etching a layer grown on a GaAs semiconductor substrate. The concentration of a conductive impurity element in a semiconductor region joined to a conductive region of the varactor diode is By increasing stepwise toward the junction surface with the conductive region, the thickness of the depletion layer when the drive voltage is not applied is decreased to increase the maximum capacitance value and improve the capacitance change ratio.

JP 2005-19736 A

  However, in the technique of the above-mentioned document 1, as shown in FIG. 5 of the document, the capacity change with respect to the drive voltage becomes nonlinear in exchange for the increase in the maximum capacity, and the capacity change with respect to the voltage change in the region where the capacity is small. The ratio (sensitivity) is much smaller than the ratio (sensitivity) of the capacitance change with respect to the voltage change in a region with a large capacity. For this reason, the loop gain of the PLL circuit varies greatly depending on the frequency domain, making optimal design difficult. In particular, the capacitance change near zero bias is abrupt, and optimal phase control in this region is actually difficult.

  In addition, it is necessary to change the driving voltage over a wide range from near 0 volts to -15 volts or less, which increases the driving circuit and power supply.

  Further, the thickness of each layer constituting the varactor diode is large, and monolithic integration is difficult. That is, the total thickness of each n-type layer described in the impurity concentration profile of Table 4 presented as a preferred example of Document 1 reaches 1050 nm, and the thickness of the transistor formation layer is added to this. Therefore, the layer thickness of the entire integrated circuit becomes very large.

  In addition, only a structural example using a GaAs substrate is disclosed, and when an HBT or HFET and a varactor diode are monolithically integrated on an InP substrate that can easily cope with higher speed and higher frequency by the second method. It is difficult to realize a preferable configuration example.

  The present invention solves these problems, and the capacitance changes linearly and greatly with respect to a voltage change in a narrow range, and is formed on an InP substrate that can easily cope with high speed and high frequency with a thin layer thickness. An object of the present invention is to provide a varactor diode and a semiconductor integrated circuit that can be monolithically integrated with a transistor.

In order to solve the above problem, a varactor diode according to claim 1 of the present invention is provided.
In a varactor diode having a semiconductor substrate (21) and an epitaxial crystal layer having a hierarchical structure formed by a p region (50d), an I region (50c), and an n region (50b) on the semiconductor substrate ,
The p region is a p ⁺ type p-type impurity is contained at a high concentration, Ri Do from less material than the band gap energy band gap energy of said semiconductor substrate,
The I region is the contact with the semiconductor substrate side of the surface of the p region, an impurity concentration of 2 × ¹⁰ 17 ^{cm -3} or less, Ri Do from 25nm or more materials thickness,
The n region contains an n-type impurity, is in contact with the surface of the I region close to the semiconductor substrate, has a total region thickness of 400 nm or less, and has a larger band gap energy than the semiconductor substrate. It consists, possesses the density reduction part has an impurity concentration higher from the I region toward the semiconductor substrate side decreases (54-57),
The concentration-decreasing portion is composed of a plurality of layers formed such that the impurity concentration decreases and the thickness increases toward the semiconductor substrate side, and a layer (n7) in contact with the I region among the plurality of layers. Layer) has an n-type impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more, a layer closest to the semiconductor substrate (n4 layer) has an n-type impurity concentration of 2 × 10 ¹⁶ cm ⁻³ or less, and a thickness of 150 nm or more. It is characterized by that.

A varactor diode according to claim 2 of the present invention is the varactor diode according to claim 1,
InP as the semiconductor substrate,
InGaAs as the material of the p region,
InAlAs is used as a material of the concentration decreasing portion of the I region and the n region.
The varactor diode according to claim 3 of the present invention is the varactor diode according to claim 1 or 2,
The high-concentration impurity concentration is in a range of 5 × 10 ¹⁸ cm ⁻³ or more.

A semiconductor integrated circuit according to claim 4 of the present invention is
A semiconductor substrate (21);
The formed by a first epitaxial crystal layers constituting a hierarchical structure by the region including the n region of the components in each region or field effect transistors of the components npn bipolar transistor in the semiconductor substrate (31 to 38) and either of the transistors of the field effect transistor of the heterostructure using npn type heterojunction bipolar transistor or n-type carriers (30, 70),
A second epitaxial crystal layer (50a) having the same hierarchical structure as the first epitaxial crystal layer and provided at a position different from the first epitaxial crystal layer on the semiconductor substrate; A varactor diode (50 ) comprising a third epitaxial crystal layer (50b to 50d) having a hierarchical structure with a p region (50d), an I region (50c), and an n region (50b) on the second epitaxial crystal layer. In a semiconductor integrated circuit including
The p region of the varactor diode is a p ⁺ type p-type impurity is contained at a high concentration, Ri Do from less material than the band gap energy band gap energy of said semiconductor substrate,
The I region is in contact with the semiconductor substrate side of the surface of the p region of the varactor diode, the impurity concentration of 2 × ¹⁰ 17 ^{cm -3} or less, Ri Do the above material thickness is 25 nm,
The n region of the varactor diode contains an n-type impurity, is in contact with the surface of the I region close to the semiconductor substrate, has a total region thickness of 400 nm or less, and has a band gap energy of the semiconductor substrate. made larger material than the impurity concentration as going from the I region in the semiconductor substrate side have a density reduction part (54-57) to be lowered,
The concentration reducing portion of the varactor diode is composed of a plurality of layers formed such that the impurity concentration decreases and the thickness increases toward the semiconductor substrate side. The n-type impurity concentration of the layer in contact (n7 layer) is 5 × 10 ¹⁷ cm ⁻³ or more, the n-type impurity concentration of the layer closest to the semiconductor substrate (n4 layer) is 2 × 10 ¹⁶ cm ⁻³ or less, and the thickness is It is characterized by being 150 nm or more.

A semiconductor integrated circuit according to claim 5 of the present invention is the semiconductor integrated circuit according to claim 4 ,
InP as the semiconductor substrate,
InGaAs as the material of the p region of the varactor diode,
InAlAs is used as a material of the concentration decreasing portion of the I region and the n region of the varactor diode.

A semiconductor integrated circuit according to claim 6 of the present invention is the semiconductor integrated circuit according to claim 5 ,
An uppermost layer (38, 78) of the first epitaxial crystal layer farthest from the semiconductor substrate and an uppermost layer of the second epitaxial crystal layer having the same hierarchical structure as the first epitaxial crystal layer The cathode contact layers (38 ', 78') are n ⁺ -type InGaAs layers containing n- type impurities at a high concentration .

A semiconductor integrated circuit according to claim 7 of the present invention is the semiconductor integrated circuit according to claim 6 ,
An etching stop layer (52) made of InP is inserted between the concentration reducing portion of the varactor diode and the cathode contact layer.

A semiconductor integrated circuit according to claim 8 of the present invention is the semiconductor integrated circuit according to any one of claims 4 to 7,
When the transistor is the heterojunction bipolar transistor,
Of the second epitaxial crystal layer, an electrode (41 ') formed on a layer (31') corresponding to the collector contact layer (31) of the heterojunction bipolar transistor and a cathode contact layer of the varactor diode Formed between the cathode electrode (61) formed thereon or on the layer (31 ') corresponding to the collector contact layer (31) and the layer (35') corresponding to the base layer (35). The formed electrodes (41 ', 42) and the cathode electrode (61) are short-circuited by a wiring connecting the electrodes.
A semiconductor integrated circuit according to claim 9 of the present invention is the semiconductor integrated circuit according to any one of claims 4 to 8,
The high-concentration impurity concentration is in a range of 5 × 10 ¹⁸ cm ⁻³ or more.

  As described above, in the present invention, the impurity concentration of the n region of the varactor diode is decreased so as to be closer to the semiconductor substrate, and the material which is not doped or is lightly doped between the p region and the n region. An I region is provided, and this I region can reduce leakage current and give high linearity to the voltage-capacitance change characteristic.

Further, the layer in contact with the I region (n7) among the plurality of layers constituting the concentration reduction portion, the thickness of the entire n region is 400 nm or less, the impurity concentration of the I region is 2 × 10 ¹⁷ cm ⁻³ or less, the thickness is 25 nm or more. Layer) having an n-type impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more, a layer closest to the semiconductor substrate (n4 layer) having an n-type impurity concentration of 2 × 10 ¹⁶ cm ⁻³ or less, and a thickness of 150 nm or more. A varactor diode whose capacitance changes linearly and greatly with a voltage change in a range can be realized with a thin layer thickness.

  Further, by using InP as the semiconductor substrate, InGaAs as the material of the p region, and InAlAs as the material of the concentration decreasing portion of the I region and the n region, it is possible to cope with high speed and high frequency.

  In addition, as a semiconductor integrated circuit including a varactor, the cathode contact layer of the varactor and the emitter contact layer of the HBT or the ohmic contact layer of the HFET are formed by etching the common layer, so that the overall layer thickness is reduced and manufactured. The process can be simplified.

  Further, by inserting an etching stop layer made of InP between the concentration reducing portion of the varactor diode and the cathode contact layer, the etching selectivity in the solution etching can be increased, and the manufacturing process is facilitated.

  In the case where the transistor is a heterojunction bipolar transistor, the collector contact layer of the heterojunction bipolar transistor is a lower layer formed in the same layer structure as the heterojunction bipolar transistor between the cathode contact layer of the varactor diode and the semiconductor substrate. Between the electrode formed on the layer corresponding to the electrode and the cathode electrode of the varactor diode, or on the layer corresponding to the collector contact layer and the layer corresponding to the base layer, respectively, and the cathode of the varactor diode By short-circuiting the electrode, the transistor formed in the lower layer can be inactivated, and variation in capacitance parasitic on the cathode can be suppressed.

Structure diagram of a semiconductor integrated circuit according to an embodiment of the present invention Structure drawing with enlarged varactor part Diagram showing the relationship between impurity concentration and thickness of each layer of varactor The figure which shows the change of the voltage-capacitance characteristic by the difference in the thickness of I area | region The figure which shows the change of the voltage-capacitance characteristic by the difference in the impurity concentration of I area | region The figure which shows the change of the voltage-capacitance characteristic by the difference in the impurity concentration of the uppermost layer of the concentration decreasing part The figure which shows the change of the voltage-capacitance characteristic by the difference in the thickness of the lowest layer of the concentration decreasing part The figure which shows the change of the voltage-capacitance characteristic by the difference in the impurity concentration of the lowest layer of the concentration decreasing part The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment The figure which shows the manufacturing process of the semiconductor integrated circuit of embodiment Structure diagram of semiconductor integrated circuit when transistor is HFET

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an npn type heterobipolar transistor (hereinafter referred to as HBT) 30 formed by etching a layer epitaxially grown on a semiconductor substrate 21 made of InP, and a varactor diode (hereinafter referred to as HBT) to which the present invention is applied. The structure of the semiconductor integrated circuit 20 including the varactor 50 is shown. Here, the HBT 30 and the varactor 50 are shown one by one. However, the actual semiconductor integrated circuit 20 includes a large number of semiconductor elements, coils, resistors, capacitors, and the like including these.

  In this semiconductor integrated circuit 20, the HBT 30 and the varactor 50 are formed by performing a predetermined etching process from above on the layer epitaxially grown on the semiconductor substrate 21 made of InP. For example, the lower layer portion 50a serving as a base has the same layer structure as that of the HBT 30, and the actual portion of the varactor 50 is formed thereon.

First, the structure (common structure) of the HBT 30 and the lower layer portion 50a of the varactor 50 will be described. On the semiconductor substrate 21 made of InP, collector contact layers 31 and 31 'made of n ⁺ -InP are provided. Are provided with etching stopper layers 32 and 32 'made of n ⁺ -InGaAs (indium, gallium, and arsenic), and further, collector contact layers 33 and 33' made of n ⁺ -InP. Here, since the layer structure of the lower layer portion 50a is the same as that of the HBT 30, the same layer name will be given and described.

On the collector contact layers 33 and 33 ', n-InGaAs or collector layers 34 and 34' containing at least n-InGaAs and n-InP are formed, and a base layer made of p ⁺ -InGaAs is formed thereon. 35 and 35 'are formed (the HBT containing InP in the collector layer is called a double heterostructure bipolar transistor DHBT).

An emitter layer 36, 36 'made of n-InP is formed on the base layer 35, 35', and an n ⁺ -InP layer 37, 37 'is formed on the emitter layer 36, 36'. An emitter contact layer 38 made of n ⁺ -InGaAs is formed. On the varactor 50 side, a common layer with the emitter contact layer 38 on the HBT 30 side is used as the cathode contact layer 38 '. The n ⁺ -InP layers 37 and 37 ′ are layers for reducing the influence of conduction band discontinuity between InP in the emitter layer and InGaAs in the emitter contact layer.

  A collector electrode 41 having a multilayer structure of Ti (titanium) / Pt (platinum) / Au (gold) is formed on the etching stopper layer 32 on the HBT 30 side, and Pt / Ti / Pt / On the base electrodes 42 and 42 made of Au and the emitter contact layer 38, an emitter lower layer electrode 43 made of WSi (tungsten silicide), an emitter middle layer electrode 44 made of Ti / Pt / Au, and Pt / Ti / Pt / Au Each emitter upper layer electrode 45 is formed, whereby an npn transistor is formed. Then, each electrode of this transistor is wired to a varactor 50, other semiconductor element, LCR, or the like, which will be described later, to form, for example, a PLL circuit. In addition, the symbol of A / B of each electrode material shall represent the multilayer structure of A and B.

  On the other hand, the npn-type transistor structure formed in the lower layer portion 50a on the varactor 50 side is unnecessary for the varactor 50. When each terminal of the transistor is open, parasitic capacitance generated between the terminals is added to the diode to operate. In order to destabilize, the collector electrode 41 'formed on the etching stopper layer 32' and the base electrode 42 'formed on the base layer 35' are formed on the cathode contact layer 38 '. By connecting (short-circuiting) to the cathode electrode 61 made of Ti / Pt / Au by wiring, fluctuations in capacitance parasitic on the cathode side of the varactor 50 are prevented. Here, both the collector electrode 41 ′ and the base electrode 42 ′ are connected to the cathode electrode 61, but the same effect can be obtained even if only the collector electrode 41 ′ is provided and connected to the cathode electrode 61. .

  Next, the structure of the substantial part (upper layer part) of the varactor 50 formed together with the cathode electrode 61 on the cathode contact layer 38 'will be described.

  Since the varactor 50 is basically a pn junction diode, an n region 50b made of a material doped with an n-type impurity and a p region 50d doped with a p-type impurity are formed on the cathode contact layer 38 '. And the anode electrode 62 is formed thereon. In the case of the varactor 50 of the present invention, a material not doped with impurities between the n region 50b and the p region 50d or n type, p An I region 50c made of a material having a low impurity concentration of any of the molds is provided.

As shown in FIG. 2, n region 50b is 'has the structure (7 layers Including, cathode contact layer 38 cathode contact layer 38)' 6 layers of the n1 layer, order from the lower layer side, n ⁺ It is divided into an n2 layer 52 made of -InP, an n3 layer 53 made of n ⁺ -InAlAs (indium / aluminum / arsenic), and an n4 layer 54 to an n7 layer 57 made of n-InAlAs.

Here, the n2 layer 52 made of n ⁺ -InP is an etching stop layer, and the four n4 layers 54 to n7 layer 57 made of n-InAlAs having a medium impurity concentration are the concentration decreasing portions of this embodiment. The impurity concentration is set to be lower as the semiconductor substrate 21 is approached.

In addition, an I layer 58 made of i-InAlAs is provided as a single layer as an I region 50c on the n7 layer 57, and a band gap energy is smaller than that of the semiconductor substrate 21 as a p region 50d thereon. A p layer 59 made of p ⁺ -InGaAs is provided as a single layer, and an anode electrode 62 made of Pt / Ti / Pt / Au is provided thereon.

  As described above, in the varactor 50 of the embodiment, the I region 50c is provided between the n region 50b and the p region 50d, and the n region 50b extends from the I region 50c to the semiconductor substrate side (cathode contact layer 38 'side). ), A concentration-decreasing portion in which the n-type impurity concentration gradually decreases is formed.

  The inventors can provide the linearity of the characteristics of the varactor 50 to the voltage-capacitance change characteristic by selecting the thickness and impurity concentration of the I layer 50c in the varactor 50 having the above-described structure. Among them, the capacitance change ratio can be increased by selecting the impurity concentration and thickness of the uppermost n7 layer 57 following the I layer 50c, and by selecting the impurity concentration and thickness of the lowermost n4 layer 54. The inventors have found that the drive voltage range necessary for obtaining a predetermined change in capacity can be narrowed.

FIG. 3 shows a preferred embodiment of the thickness and impurity concentration of each layer found from various calculation results. In this example,
Cathode contact layer 38 ′ thickness 70 nm, impurity concentration 3 × 10 ¹⁹ cm ⁻³
The thickness of the n2 layer 52 is 5 nm and the impurity concentration is 5 × 10 ¹⁸ cm ^−3.
The thickness of the n3 layer 53 is 5 nm and the impurity concentration is 1 × 10 ¹⁹ cm ^−3.
The thickness of the n4 layer 54 is 200 nm, and the impurity concentration is 1 × 10 ¹⁶ cm ^−3.
The thickness of the n5 layer 55 is 80 nm, and the impurity concentration is 1 × 10 ¹⁷ cm ^−3.
The thickness of the n6 layer 56 is 30 nm, and the impurity concentration is 5 × 10 ¹⁷ cm ^−3.
The thickness of the n7 layer 57 is 10 nm, and the impurity concentration is 1 × 10 ¹⁸ cm ^−3.
The thickness of the I layer 58 is 30 nm, the impurity concentration is not doped, the thickness of the p layer 59 is 70 nm, and the impurity concentration is 4 × 10 ¹⁹ cm ^−3.
It is said.

  Hereinafter, the calculation result of the change of the voltage per unit area of the varactor 50 with respect to the impurity concentration and the thickness for the I layer 58, the n7 layer 57, and the n4 layer 54 that have been confirmed to have a great influence on the characteristics of the varactor. Indicates. However, as a precondition, the impurity concentration and thickness of the p layer 59, the n6 layer 56, the n5 layer 55, the n3 layer 53, the n2 layer 52, and the cathode contact layer 38 ′ are the same as those described in the embodiments.

  Characteristics A and B in FIG. 4 are voltage vs. capacity change characteristics when the thickness of the I layer 58 not doped with impurities is set to 25 nm and 0 (that is, the I layer 58 is omitted). From B and the characteristics of the structure of the example, it can be seen that when the thickness of the I layer 58 is reduced, the degree of capacitance change in the range where the drive voltage is low increases and becomes nonlinear characteristics.

Further, characteristics C and D in FIG. 5 are change characteristics of voltage versus capacity when the impurity concentration of the I layer 58 having a thickness of 30 nm is set to 2 × 10 ¹⁷ cm ⁻³ and 5 × 10 ¹⁷ cm ^−3. From the characteristics of this figure and the characteristics of the structure of the example, it can be seen that the higher the impurity concentration of the I layer 58, the greater the degree of capacitance change in the range where the drive voltage is low, and the non-linear characteristics. .

Based on the above characteristics A to D and the results of other structural examples (not shown), the thickness and impurity concentration of the I layer 58 are 20 nm or more in thickness and 2 × 10 ¹⁷ cm ⁻³ or less in impurity concentration (even if not doped). It was confirmed that sufficient linearity can be given to the change of voltage versus capacitance.

Characteristics E and F in FIG. 6 are characteristics when the impurity concentration of the n7 layer 57 having a thickness of 10 nm is set to 5 × 10 ¹⁷ cm ⁻³ and 3 × 10 ¹⁷ cm ⁻³ . However, when the impurity concentration of the n7 layer 57 is set to 3 × 10 ¹⁷ cm ⁻³ , the same concentration is set so that the impurity concentration of the lower n6 layer 56 does not become higher than that of the n7 layer 57. . From the characteristics in this figure, it can be seen that the lower the impurity concentration of the n7 layer 57, the lower the maximum capacitance value and the lower the capacitance change ratio.

Based on the characteristics E and F and the results of other structural examples (not shown), the thickness and impurity concentration of the n7 layer 57 are 10 nm thick and the impurity concentration is 5 × 10 ¹⁷ cm ⁻³ or more (the structural example E By setting the lower limit, it was confirmed that a sufficiently large capacity maximum value could be secured and a large capacity change ratio could be realized.

Also, the characteristics G and H in FIG. 7 are characteristics when the thickness of the n4 layer 54 having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ is set to 150 nm and 50 nm. It can be seen that the smaller the thickness, the larger the minimum capacitance value, and the smaller the capacitance change ratio.

Further, characteristics I and J in FIG. 8 are characteristics when the impurity concentration of the n4 layer 54 having a thickness of 200 nm is set to 2 × 10 ¹⁶ cm ⁻³ and 5 × 10 ¹⁶ cm ⁻³ . From the characteristics, it can be seen that the higher the impurity concentration of the n4 layer 54, the larger the absolute value of the drive voltage for obtaining the minimum capacitance value.

Based on the above characteristics G to J and the results of other structural examples (not shown), the thickness and impurity concentration of the n4 layer 54 are 150 nm or more and the impurity concentration is 2 × 10 ¹⁶ cm ⁻³ or less. It was confirmed that a sufficiently small capacitance minimum value can be realized with a low driving voltage.

  In addition to the above-described conditions, it is necessary to limit the overall thickness of the varactor 50. However, in consideration of the above-described conditions and the structure of the preferred embodiment, the upper limit of the thickness of the n region 50b is set to 400 nm. Can be said to be preferable in production.

  The n2 layer 52 and the n3 layer 53 having a high impurity concentration in the lower layer of the n region 50b are provided to facilitate the etching process, and these two layers and the cathode contact layer 38 'under the two layers are provided. Has little effect on the characteristics of the varactor 50.

  As described above, the varactor 50 according to the embodiment reduces the impurity concentration of the n region 50b so as to be closer to the semiconductor substrate 21, and does not dope impurities between the p region 50d and the n region 50b or has a low concentration. An I region 50c made of a doped material is provided, and this I region 50c can reduce leakage current and give high linearity to the voltage-capacitance change characteristic.

Further, the entire thickness of the n region 50b is 400 nm or less, the impurity concentration of the I region 50c is 2 × 10 ¹⁷ cm ⁻³ or less, the thickness is 25 nm or more, and contacts the I region 50c among the plurality of layers constituting the concentration reducing portion. The n-type impurity concentration of the n7 layer 58 is 5 × 10 ¹⁷ cm ⁻³ or more, the n-type impurity concentration of the n4 layer 54 closest to the semiconductor substrate 21 is 2 × 10 ¹⁶ cm ⁻³ or less, and the thickness is 150 nm or more. range capacity relative to the voltage change of the varactor diode to change linearly and large, can be realized with a thin layer thickness.

  Further, since InP is used as the semiconductor substrate 21, InGaAs is used as the material of the p region 50d, and InAlAs is used as the material of the concentration decreasing portion of the I region 50c and the n region 50b, it is possible to cope with high speed and high frequency.

  Further, as the semiconductor integrated circuit 20 including the varactor 50, the cathode contact layer 38 'of the varactor 50 and the emitter contact layer 38 of the HBT 30 are formed by etching the common layer, thereby reducing the overall layer thickness. The manufacturing process can be simplified.

  Further, by inserting an etching stop layer made of InP between the concentration reducing portion of the varactor 50 and the cathode contact layer 38 ', the etching selectivity in solution etching can be increased, and the manufacturing process is facilitated.

  Further, when the transistor formed together with the varactor 50 is the HBT 30, the collector contact layer 31 ′ of the lower layer portion 50 b formed in the same layer structure as the HBT 30 between the cathode contact layer 38 ′ of the varactor 50 and the semiconductor substrate 21. Between the electrode 41 ′ and the cathode electrode 61 formed on each other or between the electrodes 41 ′ and 42 ′ formed on the collector contact layer 31 ′ and the base layer 35 ′ and the cathode electrode 61, respectively. Therefore, it is possible to inactivate the transistor formed in the lower layer portion 50b and suppress the variation in capacitance parasitic on the cathode.

Next, a method for manufacturing the semiconductor integrated circuit 20 having the above structure will be described.
First, as shown in FIG. 9, eight layers (excluding electrode materials) 131 to 138 necessary for the formation of the HBT 30 are epitaxially grown on the semiconductor substrate 21, and further the varactor 50 is formed thereon. A material 100 obtained by epitaxially growing eight layers (excluding electrode materials) 152 to 159 necessary for formation is prepared, and an anode electrode 62 is formed by evaporation at the varactor anode formation position of the uppermost layer 159.

  Here, the lower eight layers 131 to 138 have the same thickness and material as the respective layers 31 to 38 of the HBT 30, and the upper eight layers 152 to 159 correspond to the respective layers 52 to 59 of the varactor 50. And the same thickness and material.

Next, as shown in FIG. 10, the range excluding the position of the varactor cathode electrode is covered with a resist 101, and wet etching is performed to the front of the n ⁺ -InP layer 152 which is an etching stop layer. Wet etching with another material exposes a portion of the surface of layer 138 that becomes cathode contact layer 38 '.

  Then, as shown in FIG. 11, a cathode electrode 61 is deposited on the exposed surface of the layer 138, and unnecessary resist 101 is removed.

  Subsequently, as shown in FIG. 12, the entire surface is covered with a protective film 102 (silicon oxide film or silicon nitride film) (chemical vapor deposition). Further, as shown in FIG. The portion of the protective film which is covered with and is not covered with the resist 103 is removed by dry etching, and the removed portion is wet-etched to expose the surface of the layer 138 which becomes the emitter contact layer 38 of the HBT 30.

  Subsequently, as shown in FIG. 14, the entire surface is covered with the WSi film 104, and the emitter middle layer electrode 44 is formed by evaporation at the emitter formation position in the surface of the film, and further dry etched, as shown in FIG. A portion of the WSi film 104 that is not covered with the emitter middle layer electrode 44 is removed to form the emitter lower layer electrode 43.

  Subsequently, as shown in FIG. 16, the surface of the layer 135 serving as the base layers 35 and 35 ′ is exposed by wet etching on the portion not covered with the protective film 102 and the emitter lower layer electrode 43, and as shown in FIG. Base electrodes 42, 42 ′ are formed by vapor deposition on the surface of the layer 135, and simultaneously, an emitter upper layer electrode 45 is formed by vapor deposition on the emitter middle layer electrode 44.

  Subsequently, the entire surface is protected by the organic film 105 as shown in FIG. 18, and the portions other than the intermediate portion between the HBT 30 and the varactor 50 are covered with the resist 106 as shown in FIG. Dry etching is performed, and further, wet etching is performed as shown in FIG. 20 to remove the layer 132 before the etching stopper layer. As shown in FIG. 21, the collector electrode 41, 41 'is formed by vapor deposition.

  Further, as shown in FIG. 22, the area except for the portion between the collector electrodes 41 and 41 'is covered with a resist 107, and wet etching is performed on the uncovered portion, whereby the collector contact layers 31, 31' Are separated, and the elements of the HBT 30 and the varactor 50 are separated.

  If the protective film and the resist are removed in this state, the structure is the same as that shown in FIG. 1. However, when the semiconductor integrated circuit is actually manufactured, the resist 107 is removed and each of the structures shown in FIG. The semiconductor integrated circuit 20 is completed by wiring the electrodes (shown in black) and covering the surface with the organic film 108 for element protection.

  The above embodiment is an example of the varactor 50 formed on the substrate together with the HBT 30. However, the varactor 50 may be formed together with the HFET 70 as in the semiconductor integrated circuit 20 ′ shown in FIG.

The HFET 70 includes an InAlAs layer 71, an InGaAs layer 72, an InAlAs layer 73, a doping portion 74, an InAlAs layer 75, an InP layer 76, an InAlAs layer 77, and an n ⁺ -InGaAs layer (ohmic contact layer) 78 on the InP substrate 21. Epitaxial crystal growth is performed by etching each layer, and two ohmic electrodes (drain electrodes) made of Ti / Pt / Au are formed on an n ⁺ -InGaAs layer (ohmic contact layer) 78. , Source electrodes) 81 and 82 are formed, and a gate electrode 83 is provided therebetween.

The lower layer portion 50a of the varactor 50 is formed of layers 71 'to 78' having the same structure as that of the HFET 70, and the uppermost layer 78 'made of n ⁺ -InGaAs is used as the cathode contact layer. The form is the same.

Also in this case, the cathode contact layer 78 ′ of the varactor 50 is formed by etching the common layer with the n ⁺ -InGaAs layer (ohmic contact layer) 78 of the HFET 70. It can be simplified.

  20, 20 '... Semiconductor integrated circuit, 21 ... Semiconductor substrate, 30 ... HBT, 31, 31' ... Collector contact layer, 32, 32 '... Etching stopper layer, 33, 33' ... Collector contact layer 34, 34 '... Collector layer, 35, 35' ... Base layer, 36, 36 '... Emitter layer, 37, 37' ... n-InP layer, 38, 38 '... Emitter contact layer, 41 , 41 '... collector electrode, 42, 42' ... base electrode, 43 ... emitter lower layer electrode, 44 ... emitter middle layer electrode, 45 ... emitter upper layer electrode, 50 ... varactor, 50a ... lower layer part, 50b ... n region, 50c ... I region, 50d ... p region, 52 ... n2 layer, 53 ... n3 layer, 54 ... n4 layer, 55 ... n5 layer, 56 ... n6 layer, 57 ... n7 layer, 58 …… I layer 59 ...... p layer, 61 ...... cathode electrode, 62 ...... anode electrode, 70 ...... HFET

Claims (9)

In a varactor diode having a semiconductor substrate (21) and an epitaxial crystal layer having a hierarchical structure formed by a p region (50d), an I region (50c), and an n region (50b) on the semiconductor substrate ,
The p region is a p ⁺ type p-type impurity is contained at a high concentration, Ri Do from less material than the band gap energy band gap energy of said semiconductor substrate,
The I region is the contact with the semiconductor substrate side of the surface of the p region, an impurity concentration of 2 × ¹⁰ 17 ^{cm -3} or less, Ri Do from 25nm or more materials thickness,
The n region contains an n-type impurity, is in contact with the surface of the I region close to the semiconductor substrate, has a total region thickness of 400 nm or less, and has a larger band gap energy than the semiconductor substrate. It consists, possesses the density reduction part has an impurity concentration higher from the I region toward the semiconductor substrate side decreases (54-57),
The concentration-decreasing portion is composed of a plurality of layers formed such that the impurity concentration decreases and the thickness increases toward the semiconductor substrate side, and a layer (n7) in contact with the I region among the plurality of layers. Layer) has an n-type impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more, a layer closest to the semiconductor substrate (n4 layer) has an n-type impurity concentration of 2 × 10 ¹⁶ cm ⁻³ or less, and a thickness of 150 nm or more. A varactor diode characterized by that. InP as the semiconductor substrate,
InGaAs as the material of the p region,
2. The varactor diode according to claim 1, wherein InAlAs is used as a material of the concentration decreasing portion of the I region and the n region. The high impurity concentration is 5 × 10 ¹⁸ cm ^-3 3. The varactor diode according to claim 1, wherein the varactor diode is in the above range. A semiconductor substrate (21);
Formed on the semiconductor substrate by first epitaxial crystal layers (31 to 38) having a hierarchical structure formed by npn regions of bipolar transistor components or regions including n regions of field effect transistor components. either an npn heterojunction bipolar transistor or a heterostructure field effect transistor using n-type carriers (30, 70);
A second epitaxial crystal layer (50a) having the same hierarchical structure as the first epitaxial crystal layer and provided at a position different from the first epitaxial crystal layer on the semiconductor substrate; A varactor diode (50) comprising a third epitaxial crystal layer (50b to 50d) having a hierarchical structure with a p region (50d), an I region (50c), and an n region (50b) on the second epitaxial crystal layer. In a semiconductor integrated circuit including
The p region of the varactor diode is p ⁺ type containing a high concentration of p-type impurities, and is made of a material whose band gap energy is smaller than the band gap energy of the semiconductor substrate,
The I region is in contact with the surface of the p region of the varactor diode near the semiconductor substrate, and is made of a material having an impurity concentration of 2 × 10 ¹⁷ cm ⁻³ or less and a thickness of 25 nm or more,
The n region of the varactor diode contains an n-type impurity, is in contact with the surface of the I region close to the semiconductor substrate, has a total region thickness of 400 nm or less, and has a band gap energy of the semiconductor substrate. A concentration reducing portion (54 to 57) in which the impurity concentration decreases from the I region toward the semiconductor substrate.
The concentration reducing portion of the varactor diode is composed of a plurality of layers formed such that the impurity concentration decreases and the thickness increases toward the semiconductor substrate side. The n-type impurity concentration of the layer in contact (n7 layer) is 5 × 10 ¹⁷ cm ⁻³ or more, the n-type impurity concentration of the layer closest to the semiconductor substrate (n4 layer) is 2 × 10 ¹⁶ cm ⁻³ or less, and the thickness is A semiconductor integrated circuit having a thickness of 150 nm or more. InP as the semiconductor substrate,
InGaAs as the material of the p region of the varactor diode,
5. The semiconductor integrated circuit according to claim 4, wherein InAlAs is used as a material of the concentration decreasing portion of the I region and n region of the varactor diode . An uppermost layer (38, 78) of the first epitaxial crystal layer farthest from the semiconductor substrate and an uppermost layer of the second epitaxial crystal layer having the same hierarchical structure as the first epitaxial crystal layer 6. The semiconductor integrated circuit according to claim 5, wherein the cathode contact layer (38 ′, 78 ′) is an n ⁺ -type InGaAs layer containing an n-type impurity in a high concentration . The semiconductor integrated circuit according to claim 6 , wherein an etching stop layer (52) made of InP is inserted between the concentration reducing portion of the varactor diode and the cathode contact layer . When the transistor is the heterojunction bipolar transistor,
Of the second epitaxial crystal layer, an electrode (41 ') formed on a layer (31') corresponding to the collector contact layer (31) of the heterojunction bipolar transistor and a cathode contact layer of the varactor diode Formed between the cathode electrode (61) formed thereon or on the layer (31 ') corresponding to the collector contact layer (31) and the layer (35') corresponding to the base layer (35). The semiconductor according to any one of claims 4 to 7, wherein the electrode (41 ', 42) and the cathode electrode (61) are short-circuited by a wiring connecting the electrodes (41', 42). Integrated circuit. The high impurity concentration is 5 × 10 ¹⁸ cm ^-3 9. The semiconductor integrated circuit according to claim 4, wherein the semiconductor integrated circuit is in the above range.

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