JP2006278542A - Switching circuit device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid puncture due to secondary breakdown in a switch circuit device by HBT and to sharply enhance reliability. <P>SOLUTION: In the switching circuit device, the base electrode 8 of a unit HBT is connected with a ballast resistor 102 formed of a resistive layer continuous to a base layer. A switching element is constituted by connecting a plurality of unit elements each connected with the HBT and the ballast resistor in parallel. Consequently, heat generated from the unit HBT is transmitted directly to the ballast resistor in each unit element. Since the resistor has a negative temperature coefficient, resistance of a ballast resistor being connected with the unit HBT increases as heat is generated therefrom and the function as a ballast is enhanced. Consequently, puncture due to secondary breakdown is avoided in a switching circuit device by HBT and reliability can be sharply enhanced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a switch circuit device using a heterojunction bipolar transistor and a manufacturing method thereof, and more particularly to a temperature compensation type switch circuit device and a manufacturing method thereof.

Heterojunction bipolar transistor (Heterojunction Bipolar Transistor: hereinafter HBT) is a base concentration because of the high high current amplification factor _{h FE} emitter efficiency than normal homojunction bipolar transistor can be increased significantly, over the entire base Transistor operation can be made uniform. As a result, the current density is high and the on-resistance is low because of the high current density, low on-resistance, and high efficiency compared with GaAs MESFET (Metal Semiconductor Field Effect Transistor), GaAs JFET (Junction FET), and HEMT (High Electron Mobility Transistor). Are better.

  In mobile communication devices such as mobile phones, highly efficient and small high-frequency switching elements are indispensable. Therefore, as shown in FIG. 13, a switch circuit having a bidirectional heterojunction bipolar transistor as a switching element is known.

  FIG. 13 shows an example of a switch circuit using an HBT as a switching element. FIG. 13A is a circuit diagram, and FIG. 13B is a cross-sectional view illustrating the structure of an HBT.

  As shown in FIG. 13A, this circuit includes a first HBT 320 whose emitter is connected to the antenna ANT and a second HBT 321 whose collector is connected to the antenna ANT, and the collector of the first HBT 320 transmits. It is connected to the use side circuit Tx. The emitter of the second HBT 321 is connected to the reception side circuit Rx, and the bases of the HBTs 320 and 321 are connected to the transmission control terminal CtrlTx and the reception control terminal CtrlRx via the resistor 122, respectively.

  As shown in FIG. 13B, an n-type GaAs subcollector layer 311 is formed on a semi-insulating GaAs substrate 310, and an n-type AlGaAs collector layer 312, a p-type GaAs base layer 313, and an n-type are formed on the subcollector layer 311. An AlGaAs emitter layer 314, an n-type GaAs emitter contact layer 315, and the like are stacked in a mesa shape.

A collector electrode 316 is disposed on the surface of the subcollector layer 311 at a position sandwiching the collector layer 312. A base electrode 317 is disposed on the surface of the base layer 313 at a position sandwiching the emitter layer 314. An emitter electrode 318 is disposed on the emitter contact layer 315.
JP 2000-260782 A

  The emitter electrode 318, base electrode 317, and collector electrode 316 of the HBT are formed in a comb shape. The structure shown in FIG. 13B is used as one unit element, and a plurality of unit elements are connected in parallel to form an active element such as a switching element.

  In the HBT, since the base-emitter current has a positive temperature coefficient, the collector current also has a positive temperature coefficient. Accordingly, when the current density is improved by increasing the base current, the current concentrates on one unit element among the plurality of HBT unit elements connected in parallel to cause a secondary breakdown, which easily leads to breakdown. .

  Conventionally, in order to avoid such a problem in reliability, there has been a problem that the current density cannot be sufficiently improved.

  The present invention has been made in view of such a problem. First, a plurality of stacked semiconductor layers on a compound semiconductor substrate and forming at least one heterojunction, and provided on the substrate, the semiconductor layer being a collector layer, a base layer, A transistor having a collector electrode, a base electrode and an emitter electrode as an emitter layer; a resistance layer provided on the substrate; continuous with the base layer; and a unit element having the resistance layer connected to the base electrode of the transistor; A switching element in which unit elements are connected in parallel; a first RF port connected to a collector electrode or an emitter electrode of the switching element; and a plurality of second RF ports connected to an emitter electrode or a collector electrode of the switching element. , By the control signal applied to the base electrode of the switching element. Solves by forming a signal path between the first 2RF port.

  Second, a step of laminating a plurality of semiconductor layers forming at least one heterojunction on a compound semiconductor substrate, a step of mesa etching each of the semiconductor layers to form a collector layer, a base layer, and an emitter layer, A step of forming a resistance layer continuous with the base layer; a step of forming a collector electrode, a base electrode, and an emitter electrode respectively connected to the collector layer, the base layer, and the emitter layer by an ohmic metal layer; and forming a transistor; A wiring metal layer connecting the resistance layer and the other resistance layer, and forming a wiring for connecting the transistor and the other transistor.

  According to this embodiment, an element in which a ballast resistor formed by a resistance layer continuous with a base layer of a unit HBT is connected to a base electrode of the unit HBT is used as a unit element, and a plurality of unit elements are connected in parallel to form a switching element. To do. As a result, the heat generated by the unit HBT is directly transmitted to the ballast resistor in each unit element. Since the resistor has a negative temperature coefficient, when a certain unit HBT generates heat, the resistance value of the ballast resistor connected thereto increases, and the function as a ballast is further improved. Therefore, it is possible to avoid the breakdown due to the secondary breakdown in the switch circuit device using the HBT, and to greatly improve the reliability. Further, since a high frequency signal is not input to the base electrode, even if a ballast resistor is connected to the base, it does not directly affect the high frequency characteristics of the switch circuit device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  First, the first embodiment will be described with reference to FIGS.

  FIG. 1 shows a circuit diagram of the switching circuit device of the present embodiment. The switching circuit device is, for example, an SPDT (Single Pole Double Throw) switch MMIC.

  A plurality of unit elements 100 are connected in parallel to the first switching element SW1. Each unit element 100 is formed by connecting a ballast resistor 102 to the base of an HBT (hereinafter referred to as a unit HBT) 101 composed of the minimum elements. The resistance value of the ballast resistor 102 is about several hundred to several KΩ. The second switching element SW2 is also configured by connecting a plurality of unit elements 100 in parallel. The unit HBT 101 will be described later.

  The collectors of the unit elements 100 constituting the first switching element SW1 and the second switching element SW2 are common and connected to the first RF port. The first RF port is, for example, a common input terminal IN.

  Further, the emitter electrode of each unit element 100 constituting the first switching element SW1 and the emitter electrode of each unit element 100 constituting the second switching element SW2 are respectively connected to the second RF port. The second RF port is, for example, a first output terminal OUT1 and a second output terminal OUT2.

  The base electrode of each unit element 100 constituting the first and second switching elements SW1 and SW2 is connected to the control terminal via the separation element 30, respectively. That is, the base electrode of the unit element 100 constituting the first switching element SW1 is connected to the first control terminal Ctl1, and the base electrode of the unit element 100 constituting the second switching element SW2 is connected to the second control terminal Ctl2. The separation element 30 is a resistor, and is arranged for the purpose of preventing a high-frequency signal from leaking through the base electrode with respect to the DC potential of the control terminals Ctl1 and Ctl2 serving as AC grounding. The resistance value of the separation element 30 is about 5 KΩ to 10 KΩ.

  A case where the control signals applied to the first control terminal Ctl1 and the second control terminal Ctl2 are complementary signals will be described. In this case, when the signal at the first control terminal Ctl1 is at the H level (eg, 3V), the signal at the second control terminal Ctl2 is at the L level (eg, 0V). Then, the switching element to which the H level is applied becomes conductive, and a signal path is formed between the first RF port and the second RF port.

For example, when the H level signal is applied to the first control terminal Ctl1, based units HBT 101 of the first switching element SW1 - around the upper emitter voltage of the ON voltage _{V BE} of the unit HBT 101, a unit HBT 101 is turned on.

  At this time, since the L-level signal is applied to the second control terminal Ctl2, the second switching element SW2 does not operate. As a result, one signal path is formed between the common input terminal IN and the first output terminal OUT1, and for example, a high-frequency analog signal input to the common input terminal IN is output from the first output terminal OUT1.

  On the other hand, when an H level signal is applied to the second control terminal Ctl2, one signal path is formed between the common input terminal IN and the second output terminal OUT2.

  A bias point BP is connected to the emitter electrode and the collector electrode of the first and second switching elements SW1, SW2. The bias point BP applies a bias potential (for example, a GND potential) equal to the emitter electrode and the collector electrode of the first switching element SW1 and the second switching element SW2.

  The high-frequency signal separating element 30 is connected between the emitter electrode of the first and second switching elements SW1 and SW2 and the bias point BP, and between the collector electrode of the first and second switching elements SW1 and SW2 and the bias point BP. To do. The separation element 30 is a resistor having a resistance value of 5 KΩ to 10 KΩ, for example, and prevents the high frequency signal from leaking with respect to the bias potential (GND potential).

Hereinafter, the circuit operation of FIG. 1 will be described. The on-voltage (base-emitter voltage) V _BE of the unit HBT 101 is set to 1.6 V, for example. The unit HBT 101 is turned on when the potential of the base electrode becomes 1.6 V or more higher than the potential of the emitter electrode and the collector electrode. Here, the potential of the emitter electrode and the collector electrode of the unit HBT 101 is set to the GND potential (0 V).

  For example, when 3V is applied to the first control terminal Ctl1, in the on-side switching element (first switching element SW1), the potential difference between the first control terminal Ctl1 and the potentials of the emitter electrode and the collector electrode of the unit HBT101 is 3V. (= 3V-0V). This is sufficiently higher than the potential (1.6 V) at which the unit HBT 101 of the first switching element SW1 is turned on.

  The resistance value of the resistor which is the separation element 30 connected to the bias point BP is about 5 to 10 KΩ. Although voltage drop occurs due to the base current flowing through this resistor, the unit HBT 101 of the first switching element SW1 is sufficiently turned on by the potential applied from the first control terminal Ctl1 even if this is taken into consideration, and the emitter-collector is conductive. To do.

  On the other hand, on the off side (second switching element SW2), the potential of the base electrode is 0V with respect to the potential 0V (GND) of the emitter electrode and the collector electrode of the unit HBT101. Since the unit HBT101 of the second switching element SW2 is turned on when the potential of the control terminal Ctl becomes 1.6V or more higher than the potential of the emitter electrode and the collector electrode of the unit HBT101, the off-side unit HBT101 has an amplitude of 1.6V. Can withstand the power of An amplitude of 1.6 V corresponds to a power of 20.1 dBm, and can be used for wireless LAN and Bluetooth.

  As described above, as the operation of the switching circuit device of the first embodiment, the control signals applied to the first control terminal Ctl1 and the second control terminal Ctl2 are complementary signals, and the first switching element SW1 and the second switching element SW2 The case where either of them is conducted is shown.

  However, the control signals applied to the first control terminal Ctl1 and the second control terminal Ctl2 may both be L level. When both are at L level, both SW1 and SW2 are cut off.

  Here, the common input terminal IN, the first output terminal OUT1, and the second output terminal OUT2 that are RF ports are set to the GND potential. Since a switch circuit device using an FET as a switching element cannot set the RF port to the GND potential, it is necessary to connect an external capacitor to the RF port. However, this embodiment is not necessary, and the mounting area can be reduced as compared with a switch circuit device using FETs as switching elements.

  FIG. 2 shows a pattern example of a switch MMIC in which the circuit of FIG. 1 is integrated on a compound semiconductor substrate.

  First and second switching elements SW1 and SW2 for switching are arranged on a GaAs substrate. Further, the pads I, O1, O2, C1, C2, and G serving as the common input terminal IN, the first output terminal OUT1, the second output terminal OUT2, the first control terminal Ctl1, the second control terminal Ctl2, and the ground terminal GND are the substrate. It is provided in the vicinity.

  The first switching element SW1, the second switching element SW2, and the pads are arranged symmetrically with respect to the center of the chip. Accordingly, the first switching element SW1 side will be described below, but the same applies to the second switching element SW2 side.

  The first switching element SW1 is configured by connecting a plurality of unit elements 100 in parallel, and each unit element 100 includes a unit HBT 101 and a ballast resistor 102. The unit HBT 101 and the ballast resistor 102 are formed by stacking a plurality of semiconductor layers on a substrate and making each semiconductor layer have a predetermined mesa structure. Further, an element constituting the switch MMIC such as a resistor is formed by the impurity region made of the semiconductor layer. As will be described later, the impurity region of this embodiment is formed by providing an isolation region 20 that reaches the substrate.

  The emitter electrode 9, the base electrode 8, and the collector electrode 7 of the first layer of the unit HBT 101 are formed in a comb shape by an ohmic metal layer. The second-layer emitter electrode 15 and the collector electrode 13 are formed of a wiring metal layer, and the emitter electrode 15 is formed in the same comb shape as the first-layer emitter electrode 9. The collector electrode 13 in the second layer is connected to the collector electrode 13 of another unit HBT 101 by the collector wiring 130 and is connected to the common input terminal pad I. An emitter wiring 150 made of a gold plating layer is formed on the second-layer emitter electrode 15, and is connected to the emitter electrode 15 of the other unit HBT 101 and to the first output terminal pad O1. A gold plating layer is also superimposed on the collector wiring 130.

  The unit HBT 101 connects the emitter electrodes 9 and 15 and the collector electrodes 7 and 13 to the GND pad G serving as the bias point BP in order to draw the base current. The emitter electrode 15 is commonly connected to the first output terminal pad O1 by the emitter wiring 150. Therefore, by connecting the output terminal pad O1 and the GND pad G, the emitter electrodes 9 and 15 can be connected to the bias point BP. The collector electrode 13 is commonly connected by a collector wiring 130. Therefore, the collector electrodes 7 and 13 can be connected to the bias point BP by connecting the collector wiring 130 and the GND pad G via the resistance of the separation element 30. The bias point BP (GND pad G) is disposed on the opposite side of the common input terminal pad I between the first output terminal pad O1 and the second output terminal pad O2 as shown in FIG. With this arrangement, a bias potential can be applied to the emitter electrode and the collector electrode of the unit HBT 101 without particularly securing a new space.

  The ballast resistor 102 is obtained by extending a base layer with which the base electrode 8 of the unit HBT 101 contacts with a predetermined length. The base layer is a semiconductor layer having a high impurity concentration, which will be described later, and is patterned into a ballast resistor 102 having a resistance value of about several hundred to several KΩ by patterning with a predetermined length. The unit element 100 of this embodiment is configured by the unit HBT 101 and the ballast resistor 102 connected to the base electrode 8.

  The ballast resistor 102 is connected to the base wiring 120 and is connected to the first control terminal Ctl1 via a resistor that is the separation element 30.

  A resistor serving as a separation element 30 is connected between the first output terminal pad O1 and the ground terminal pad G. Further, a resistor serving as the separation element 30 is connected between the common input terminal pad I and the ground terminal pad G. The separation element prevents leakage of high frequency signals.

  The resistance of the separation element 30 is the impurity region 23 separated by the separation region 20. A peripheral impurity region 170 is provided around each pad and around the base wiring 120 to improve isolation.

  The unit element 100 will be described with reference to FIG. 3A is an enlarged plan view of the unit element, and FIG. 3B is a cross-sectional view taken along the line aa in FIG. 3A.

  As will be described later, the unit HBT 101 is formed by mesa-etching each semiconductor layer in a desired pattern to form each semiconductor layer that becomes an emitter layer and a base layer in a mesa shape.

  The ohmic metal layer (AuGe / Ni / Au) provides the first emitter electrode 9 and the collector electrode 7 connected to the emitter layer and the collector layer, respectively, and the ohmic metal layer (Pt / Ti / Pt / Au) provides a base. A base electrode 8 connected to the layer is formed. The emitter electrode 9 and the collector electrode 7 are provided in a comb shape. A base electrode 8 is arranged around the emitter electrode 9 in the center as hatched. Two collector electrodes 7 are arranged on the subcollector layer outside the base electrode 8.

  On the emitter electrode 9 and the collector electrode 7 of the first layer, the emitter electrode 15 and the collector electrode 13 of the second layer are provided by a wiring metal layer (Ti / Pt / Au) overlapping therewith. The second-layer emitter electrode 15 has a comb shape similar to that of the first layer. The second-layer collector electrode 13 is continuous with the collector wiring 130. The base electrode 8 has a single-layer structure with only an ohmic metal layer. On the emitter electrode 15 of the second layer, an emitter wiring 150 is provided by a gold plating layer.

  The ballast resistor 102 is provided on the same substrate and semiconductor layer as the unit HBT 101. The base layer 4 is formed by mesa etching, and the base electrode 8 is in contact with one end of the base layer 4 like hatching. The other end is in contact with the resistive ohmic electrode 12 as hatched.

  The resistance ohmic electrode 12 is formed in an island shape by the same ohmic metal layer as the base electrode 8. The ballast resistor 102 uses the resistance ohmic electrode 12 and the base electrode 8 of the unit HBT 101 as electrodes at both ends. In the present embodiment, the resistive ohmic electrode 12 of the ballast resistor 102 is used as the base electrode 12 of the unit element 100.

  A base wiring 120 made of a wiring metal layer (Ti / Pt / Au) is formed on the base electrode 12. The base wiring 120 is commonly connected to the base electrode 12 of the other unit element 100. Base wiring 120 extends in a direction orthogonal to the extending direction of each electrode of comb-shaped unit HBT 101.

  In general, the HBT is mostly used for an amplifier circuit or a local oscillation circuit. In an amplification circuit or a local oscillation circuit using an HBT, a high-frequency signal is input to the base. Therefore, when a ballast resistor is connected to the base, the high-frequency characteristics deteriorate. However, when an HBT is used for the switch circuit, no high-frequency signal is input to the base, so even if a ballast resistor is connected to the base, the high-frequency characteristics of the switch circuit device are not directly affected.

  The ballast resistor 102 needs to function for each unit element 100 to prevent secondary breakdown of the unit element 100. Therefore, when the unit HBT 101 is connected in parallel to form a switching element, the base electrode 8 of the unit HBT 101 is not commonly connected, but the base electrode 12 of the unit element 100 (resistance ohmic electrode 12 of the ballast resistor 102) is commonly connected. .

  The collector electrode and the emitter electrode of the unit element 100 are the collector electrode 7 and the emitter electrode 9 of the unit HBT 101, respectively.

  The collector electrode, base electrode, and emitter electrode of the switching element are obtained by commonly connecting the collector electrode 7, the base electrode 8, and the emitter electrode 9 of the unit element 100, respectively. That is, that is, the collector electrodes 13 and 7 of each unit HBT 101 are commonly connected to each other by the collector wiring 130, and the emitter electrodes 15 and 9 of each unit HBT 101 are commonly connected to each other by the emitter wiring 150. The collector electrodes 7 and 13 are shared by the adjacent unit elements 100. Furthermore, the base electrode 12 of each unit element is commonly connected to each other by the base wiring 120.

  A bias point having an equal potential is connected to the emitter electrode 9 and the collector electrode 7 of each unit HBT 101 to give a predetermined base-emitter voltage bias and a base-collector voltage bias, and to draw a base current.

  The peripheral impurity region 170 of the base wiring 120 is an impurity region 23 in which the semiconductor layer is separated by the separation region 20. Since the isolation region 20 is an insulating region by ion implantation of B + or the like, the region other than the isolation region 20 becomes the impurity region 23 in this embodiment.

  The unit element 100 of the present embodiment includes a unit HBT 101 having a minimum unit mesa structure having an emitter electrode 9, a base electrode 8, and a collector electrode 7 as indicated by broken lines, and a ballast resistor 102 extending from the base layer 4 of the unit HBT 101. .

  Referring to FIG. 3B, on a semi-insulating GaAs substrate 1, a plurality of semiconductor layers, that is, a sub-collector layer 2 of an n + type GaAs layer, a collector layer 3 of an n type InGaP layer, and a p + type GaAs layer are formed. A base layer 4, an emitter layer 5 of an n-type InGaP layer, and an emitter contact layer 6 of an n + type GaAs layer are stacked. A part of the semiconductor layer is removed by etching to form a unit HBT 101 having a mesa structure and a ballast resistor 102.

  On the emitter contact layer 6, a first-layer emitter electrode 9, a second-layer emitter electrode 15, and a third-layer emitter wiring 150 are provided.

  The ballast resistor 102 is formed by mesa-etching the p + -type GaAs layer 4 and the n-type InGaP layer 3 serving as the base layer and collector layer of the unit HBT 101 into a pattern having a desired resistance value. That is, the unit HBT 101 is provided on the same substrate and is continuous with the base layer 4 and the semiconductor layer below it. The p + type GaAs layer functions as a resistance layer.

  A base electrode 8 contacts the base layer 4, and a resistance ohmic electrode 12 contacts one end of the ballast resistor 102. The resistance ohmic electrode (base electrode of the unit element 100) 12 is further connected to the base wiring 120. The base wiring 120 extends on the subcollector layer 2 through the insulating film 50 and is commonly connected to the base electrode 12 of each unit element 100. Under the base wiring 120, the impurity region 23 is separated by the insulating region 20 reaching the substrate 1.

  The semiconductor layer to be the emitter layer 5 and the collector layer 3 may be an AlGaAs layer instead of the InGaP layer, and in any case, is lattice-matched with the GaAs layer of the base layer 4a.

  Here, the mesa shape and the wiring direction will be described.

  When wet etching is employed for GaAs mesa etching, the crystal plane affects the mesa shape. As the relationship between the crystal direction and the mesa shape, the mesa shape when tracing the surface of the etching step in the direction parallel to the direction of [01 bar 1 bar] (hereinafter referred to as [01-1-) is a forward mesa shape (trapezoidal shape). Shape). Further, the mesa shape when the etching step surface is traced in the direction perpendicular to the [01-1-] direction is an inverted mesa shape (overhang shape).

  That is, for example, when the wiring metal layer moves up and down the mesa step, a step coverage problem occurs depending on the mesa shape or the extending direction of the wiring metal layer.

  When the metal layer extends in a direction parallel to the [01-1-] direction and moves up and down the mesa step, the step coverage problem does not occur because the metal layer has a forward mesa shape. However, when the wiring extends in the direction perpendicular to the [01-1-] direction and goes up and down the mesa level difference, it has an inverted mesa shape, which causes a step coverage problem.

  In this embodiment, the emitter mesa EM shown in FIG. 3A is formed by mesa etching (emitter mesa etching) for forming the emitter contact layer 6 and the emitter layer 5 of the unit HBT 101.

  A mesa is also formed in the region of the ballast resistor 102 at the same time by mesa etching (base mesa etching) for forming the base layer 4 and the collector layer 3 of the unit HBT 101. That is, in FIG. 3A, the mesa is formed at the same time as the base mesa BM. Accordingly, the base wiring 120 that connects the ballast resistors 102 moves up and down the base mesa BM.

  Therefore, in the present embodiment, the direction in which the base wiring 120 moves up and down the mesa is aligned, and both extend in the direction parallel to the [01-1-] direction (the direction of the arrow in the figure).

  With reference to FIG. 4, the unit HBT of this embodiment is demonstrated. 4A is a cross-sectional view showing an example of the unit HBT, and is a cross-sectional view taken along the line bb of FIG. 3A. The second and higher electrodes are omitted. 4B and 4C are characteristic diagrams of the unit HBT.

  Referring to FIG. 4A, a subcollector layer 2 is formed on a semi-insulating GaAs substrate 1, and a collector layer 3, a base layer 4, an emitter layer 5, and an emitter contact layer 6 are formed on the subcollector layer 2. It is configured to be stacked in a mesa shape.

The sub-collector layer 2 of the unit HBT 101 is an n + -type GaAs layer formed on the substrate 1 by an epitaxial growth method and doped with silicon (Si) at a relatively high impurity concentration of ³ to 6E18 cm ⁻³ . Its film thickness is several thousand mm. The collector layer 3 is an n-type InGaP layer formed on a partial region of the subcollector layer 2 and doped to an impurity concentration of about 1 to 5E17 cm ⁻³ by silicon doping. The film thickness is 1000 to 5000 mm. The base layer 4 is a p + type GaAs layer formed on the collector layer 3 and doped to an impurity concentration of about 1 to 50E18 cm ⁻³ by carbon (C) doping. The film thickness is several hundred to 2,000 mm. The emitter layer 5 is an n-type InGaP layer formed on a partial region of the base layer 4 and doped to an impurity concentration of about 1 to 5E17 cm ⁻³ by silicon doping. The film thickness is 1000 to 5000 mm. The emitter layer 5 is lattice-matched with the upper and lower GaAs layers. The emitter contact layer 6 is an n + -type GaAs layer formed on the emitter layer 5 and doped to an impurity concentration of about ³ to 6E18 cm ⁻³ by silicon doping, and has a film thickness of several thousand Å.

  On the surface of the subcollector layer 2, a collector electrode 7 made of an AuGe / Ni / Au layer is disposed at a position sandwiching the collector layer 3. On the surface of the base layer 4, a base electrode 8 made of a Pt / Ti / Pt / Au layer is disposed at a position sandwiching the emitter layer 5. An emitter electrode 9 made of an AuGe / Ni / Au layer is disposed on the emitter contact layer 6. In the present embodiment, as shown in the figure, the HBT configured by the minimum unit is set as the unit HBT 101.

  In the unit HBT 101, the emitter layer 5 and the base layer 4 form an InGaP / GaAs heterojunction, and the collector layer 3 and the base layer 4 also form an InGaP / GaAs heterojunction. A transistor is operated in a forward direction in which the emitter layer 5 operates as an emitter (hereinafter referred to as a forward transistor operation), and in a reverse direction in which the emitter layer 5 operates as a collector (hereinafter referred to as a reverse transistor operation). Each structural parameter is controlled so that the characteristics are substantially the same, and the collector-emitter voltage is operated at 0 V, and the collector-emitter current is operated at a bias around 0 A.

4B and 4C are characteristic diagrams of the unit HBT 101. FIG. Figure collector at a given base current _{I B} - shows the V-I curve of the emitter voltage _{V CE} and the collector current Ic.

In a given base current I _B collector - called emitter voltage V _CE and the collector current Ic is positive (+) value sequentially transistor transistor shown a negative (-) value transistor of the opposite transistor shown a.

As shown in FIG. 4B, the unit HBT 101 of this embodiment includes an on-resistance Ron (= ΔV _CE / ΔI _C ) during forward transistor operation and an on-resistance Ron ′ (= ΔV _CE ′ / ΔI _C ) during reverse transistor operation. The HBT is configured so that ') is substantially equal. In order to realize this, the emitter layer 5 and the collector layer 3 basically have the same structure. For example, when an InGaP layer is used for the emitter layer 5, an InGaP layer is also used for the collector layer 3. When InGaP layers are used for the emitter layer 5 and the collector layer 3, they are lattice-matched with the GaAs layers (sub-collector layer 2 and emitter contact layer 6), respectively. Further, when AlGaAs layers are used for the emitter layer 5 and the collector layer 3, the molar ratio of Al is made the same.

  Then, the impurity concentration of the emitter layer 5 and the impurity concentration of the collector layer 3 are set to substantially the same value. As a result, the base-collector breakdown voltage is lower than that of a normal HBT. However, in the switch circuit device, a base-collector breakdown voltage of 7 to 8 V is sufficient.

  As described above, the unit HBT 101 employs an HBT in which the emitter and the collector are symmetric with respect to the base (hereinafter, symmetric HBT). The symmetrical HBT can operate with a collector-emitter voltage of 0 A by operating the collector-emitter voltage with a bias of 0V.

Note that the rising voltage of the forward transistor (same as the rising voltage of the reverse transistor) is preferably 0 V as shown in FIG. However, as shown in FIG. 4C, the forward voltage of the forward transistor may not be 0 V but may have an offset voltage V _OFF . In this case, when the bias collector-emitter voltage V _CE to 0V, and the collector - slight current consumption occurs in the emitter.

  One cause of offset voltage generation in an HBT in which the emitter and collector are not symmetrical is the asymmetry of the emitter and collector. However, in many cases, the symmetric HBT has basically the same structure of the emitter and the collector. Therefore, the offset voltage of the symmetric HBT is very small compared to the non-symmetrical HBT. However, there may be an offset voltage although it is small. One of the causes is a band spike at the bottom of the conduction band of the heterojunction between the base and the emitter and between the base and the collector. Therefore, in such a case, a structure that eliminates band spikes is preferable.

  FIG. 5 is a sectional view for explaining another structure of the unit HBT 101.

  FIG. 5A shows a structure having a grading layer in order to eliminate band spikes.

For example, an Al _0.3 Ga _0.7 As layer is employed for the emitter layer 5 and the collector layer 3. Then, the grading layer 32 is disposed between the base and the emitter and between the base and the collector. That is, an n-type Al _X Ga _1-X As (X = 0 → 0.3) layer gradually changing from GaAs to Al _0.3 Ga _0.7 As is disposed between the base and the emitter, and the base-collector is arranged. For example, an n-type Al _X Ga _1-X As (X = 0.3 → 0) layer that gradually changes from Al _0.3 Ga _0.7 As to GaAs is disposed. Thereby, the offset voltage can be further reduced extremely.

  FIG. 5B shows a case where the heterojunction is shifted from the pn junction between the emitter and the base, and the emitter layer 5 is an n-type AlGaAs layer.

  As a general HBT structure, the emitter-base pn junction between the n-type AlGaAs layer of the emitter layer 5 and the p-type GaAs layer of the base layer 4 coincides with the heterojunction. In this case, a band spike is present at the bottom of the conduction band, and this band spike is one of the causes of the offset voltage generation. In order to prevent the occurrence of an offset voltage due to a band spike, an n-type GaAs layer 5 ′ is added between the base layer 4 (p-type GaAs layer) and the emitter layer 5 (n-type AlGaAs layer), thereby positioning the heterojunction position. It may be shifted from the pn junction position between the so-emitters. In addition, since it is a symmetric type HBT, an n-type GaAs layer 3 ′ is further added between the base layer 4 (p-type GaAs layer) and the collector layer 3 (n-type AlGaAs layer), thereby changing the heterojunction position between the base and the collector. It may be shifted from the pn junction position. In this case, since the heterojunction position does not coincide with the pn junction between the emitter and the base and the pn junction between the collector and the base, the offset voltage can be made very small.

  As an HBT principle, an AlGaAs layer having a band gap larger than that of the GaAs layer as the base layer 4 is arranged as the emitter layer 5 so that holes in the base are not injected into the emitter side. Similarly, during reverse transistor operation, the collector functions as an emitter, so an AlGaAs layer having a larger band gap than the GaAs layer as the base layer 4 is disposed as the collector layer 3.

  In the case of this structure, the junction of the added n-type GaAs layer 5 'and the emitter layer n-type AlGaAs layer 5 located thereon is a heterojunction. Similarly, the junction between the added n-type GaAs layer 3 'and the n-type AlGaAs layer 3 as the collector layer located therebelow becomes a heterojunction.

  Further, the on-resistances Ron and Ron ′ may be slightly different as an asymmetry other than the offset voltage. The cause is the difference between the emitter parasitic resistance and collector parasitic resistance. In that case, the impurity concentration and thickness of the emitter layer 5, the collector layer 3, and further the emitter contact layer 6 and the subcollector layer 2 may be adjusted so that the on-resistances Ron and Ron 'are equal.

In this embodiment, the symmetric HBT is a unit HBT 101, and a ballast resistor 102 is connected to each unit HBT 101 to constitute a switch circuit device. As a result, a switch circuit with a current consumption between the collector and the emitter of 0 A is realized. Furthermore, in the symmetric HBT, the on-resistance Ron during forward transistor operation and the on-resistance Ron ′ during reverse transistor operation are substantially equal, so that the collector-emitter voltage _VCE is positive in the amplitude of the high-frequency signal, and the collector-emitter voltage V _A switch circuit with good linearity can be obtained at the switching portion where _CE is negative.

The switch circuit using GaAs MESFET or HEMT has a drain-source bias of 0 V, so that the drain-source consumption current is 0 A, and the drain-source voltage V _DS is positive in the amplitude of the high-frequency signal. The linearity is good at the switching portion where the _VDS is negative. That is, the switch circuit of the present embodiment has the same advantages as the GaAs MESFET and HEMT switch circuits. Further, the on-resistance of the bipolar device HBT is overwhelmingly lower than that of the unipolar device FET, and when a switch circuit is formed, the high frequency characteristics are greatly improved, and the chip size can be greatly reduced.

  In general, an HBT can potentially have a very high current density and a very low on-resistance Ron compared to a HEMT. However, the HBT has a problem that the current concentrates on one unit HBT due to the positive feedback action due to temperature and breaks due to secondary breakdown. That is, the base-emitter voltage-base current characteristic of the HBT has a positive coefficient with respect to temperature. For this reason, a certain unit HBT 101 element may have a slightly larger base-emitter voltage bias applied to another unit HBT 101 due to some design non-uniformity factor. As a result, a large amount of base current and collector current flow, the temperature rises, more base current and collector current flow, and finally breakdown. This is the normal secondary yielding process. For this reason, the current density cannot actually be increased sufficiently.

  However, in the unit element 100 of the present embodiment, the secondary breakdown process is not actually started. The unit element 100 has a configuration in which a ballast resistor 102 that is continuous with the base layer 4 of the unit HBT 101 and is formed of a resistance layer is connected to the base electrode 8 of the unit HBT 101. That is, heat generated by the operation of the unit HBT 101 can be directly transmitted to the ballast resistor 102. Since the ballast resistor 102 has a negative temperature coefficient, the resistance value of the ballast resistor 102 increases when the unit HBT 101 generates heat. The original function of the ballast resistor 102 is to increase the voltage drop across the ballast resistor 102 as the base current increases. As a result, the base-emitter voltage decreases, so that the base current and the collector current can be reduced and secondary breakdown can be prevented.

  Therefore, with the structure of the present embodiment, the resistance value of the ballast resistor 102 can be further increased by the heat generation of the unit HBT 101, and thus the function as a ballast can be further increased. The heat generation of the unit HBT 101 can significantly reduce the base current and the collector current of the unit HBT 101, and the unit HBT 101 can be sufficiently cooled. That is, as a result, occurrence of secondary breakdown can be effectively prevented. In addition, since no high frequency signal is input to the base electrode 8, even if the ballast resistor 102 is connected to the base, the high frequency characteristics of the switch circuit device are not directly affected.

  That is, according to the present embodiment, even if the switch circuit device is configured by an HBT, it is possible to prevent the occurrence of secondary breakdown, so that the current density of the HBT can be significantly increased as compared with the prior art. As a result, the on-resistance Ron of the first and second switching elements SW1 and SW2 can be made very small, and the insertion loss of the switch MMIC can be made very small.

  Since the HEMT generally used in the switch MMIC is a unipolar device, the HBT is a bipolar device, so that the current density can be greatly increased and the on-resistance Ron can be extremely reduced. Further, since the unit HBT 101 is a symmetric HBT, the current consumption between the collector and the emitter is set to 0, so that an energy saving operation is possible. The reason is that the collector-emitter voltage can be biased to 0V in the symmetric HBT 101 in the same manner as the drain-source voltage is biased to 0V in the HEMT.

  FIG. 6 shows a cross-sectional view of the pad and the wiring. 6A and 6B are cross-sectional views taken along line cc in FIG. 2, and FIG. 6C is a cross-sectional view taken along line dd in FIG.

  The common input terminal pad I, the first output terminal pad O1, the first control terminal pad C1 (the same applies to the second switching element SW2 side), the pad P serving as the ground terminal pad G and the base wiring 120 are sub-collector layers as shown in the figure. It is provided on the (n + type GaAs) layer. The pad P and the base wiring 120 are provided on the subcollector layer 2 through the nitride film 51 (FIG. 6B) or directly provided on the subcollector layer 2, and a Schottky junction is formed with the surface of the subcollector layer 2. It forms (FIG. 6 (A), (C)).

  Therefore, as a countermeasure against isolation around the pad P and the base wiring 120, a peripheral impurity region 170 (impurity region 23) is disposed around the pad P and the base wiring 120. The impurity region 23 of the present embodiment is formed by being separated by the insulating region 20 as described above.

  FIG. 7 shows a second embodiment. The second embodiment differs from the switch MMIC of the first embodiment in the configuration of the unit element 100, and is otherwise the same as that of the first embodiment. Further, the figure is a cross-sectional view taken along the line aa in FIG.

  The unit element 100 of the second embodiment has a structure in which the parasitic capacitance of the unit element 100 of the first embodiment is reduced. In the structure of FIG. 3B, the ballast resistor 102 is formed by extending the base mesa etching pattern of the unit HBT 101.

  However, when the base mesa etching pattern is extended, the collector layer 2 under the base layer 4 is also extended. That is, a parasitic capacitance is added between the base and collector of the ballast resistor 102. The addition of parasitic capacitance becomes a factor that increases the insertion loss of the switch circuit device. Therefore, in order to reduce the parasitic capacitance of the ballast resistor 102, it is preferable to provide a collector insulating region 21 by ion implantation.

  Since the collector layer 2 is insulated in the region where the base mesa is extended by this ion implantation, a structure in which almost no parasitic capacitance is added is realized.

Here, the collector insulating region 21 is a region insulated by ion implantation of impurities (B +), similarly to the insulating region 20 for isolating the impurity region 23, and in a region completely electrically insulated. Absent. Further, the ion implantation is not so high that all the layers are insulated. That is, it is formed by boron implantation with a dose amount (for example, about 0.5 to 5 × 10 ¹² cm ⁻² ) sufficient to insulate only the collector layer (n-type InGaP layer) 2. Other components are the same as those in the first embodiment (same as in FIG. 3B).

  The base layer 4, which is a p + -type GaAs layer, has a very high impurity concentration and is hardly affected by the ion implantation for forming the collector insulating region 21. Therefore, the ballast resistor 102 and the resistive ohmic electrode 12 may have the same configuration as that of the first embodiment (FIG. 3B), and the resistance value of the ballast resistor 102 does not change.

  The collector insulating region 21 is provided so as to reach the GaAs substrate 1, and boron is also implanted into the subcollector layer 2. However, since the sub-collector layer 2 of the n + -type GaAs layer has a high impurity concentration, it is not insulated by ion implantation for forming the collector insulating region 21.

  That is, the collector insulating region 21 insulates only the collector layer 3 below the ballast resistor 102. In the case of the structure in FIG. 3B, a parasitic capacitance of about 0.3 pF to several pF is added if the ballast resistor 102 has a resistance value of about several hundred Ω to several KΩ. On the other hand, the parasitic capacitance added by the structure of FIG. 7 can be greatly reduced.

  Note that ion implantation for forming the collector insulating region 21 may also be performed under the base electrode 8. Thereby, the parasitic capacitance between the base and the collector can be further reduced.

  With reference to FIG. 8 to FIG. 10, the manufacturing method of the switch circuit device of the present embodiment will be described focusing on unit elements. In the following description, the unit element according to the second embodiment will be described as an example. However, the unit element manufacturing method according to the first embodiment is the following manufacturing method except for the step of forming the collector insulating region. Since it is the same, description is abbreviate | omitted. Further, the left side of each figure shows a cross-sectional view taken along the line aa of FIG.

  1st process: The process of laminating | stacking the some semiconductor layer which forms at least 1 heterojunction in a compound semiconductor substrate.

  On the GaAs substrate 1, an n + type GaAs layer 2, an n type InGaP layer 3, a p + type GaAs layer 4, an n type InGaP layer 5, and an n + type GaAs layer 6 are sequentially formed. The n-type InGaP layer 5 is lattice-matched with the upper and lower GaAs layers (FIG. 8A).

  Second and third steps: a step of mesa etching each semiconductor layer to form a collector layer, a base layer, and an emitter layer, and forming a resistance layer continuous to the base layer.

  A photoetching process for forming the emitter layer of the unit HBT is performed. First, the n + -type GaAs layer 6 is mesa-etched, and then the n-type InGaP layer 5 is partially mesa-etched. Thereafter, the remaining n-type InGaP layer 5 is mesa-etched by a new photoetching process to remove the resist. As a result, the emitter contact layer 6 and the emitter layer 5 are formed in a mesa shape (emitter mesa EM), and a ledge (shelf) L is formed below the emitter layer 5 as shown in the right figure.

Next, a resist (not shown) is provided to form a collector insulating region, and a photolithography process is performed. For example, an impurity with a dose of about 0.5 to 5 × 10 ¹² cm ⁻² is ion-implanted while exposing the formation region of the ballast resistor. Thereafter, the resist is removed (FIG. 8B).

  Next, a photoetching process for forming the base layer is performed. The p + type GaAs layer 4 and the n type InGaP layer 3 are mesa-etched to remove the resist.

  Thereby, the base layer 4 and the collector layer 3 are formed in a mesa shape (base mesa BM). The emitter contact layer 6 is exposed at the uppermost layer, and the base layer 4 is exposed outside the emitter layer 5. The subcollector layer 2 is exposed outside the base layer 4.

  At the same time, the ballast resistor 102 having a resistance value of about several hundred to several KΩ is formed in a mesa shape by extending the base mesa pattern by several μm to several tens of μm in the extending direction of the comb.

  Furthermore, an insulating region for isolating the impurity region 23 such as the peripheral impurity region 170 of the switching element constituted by the HBT and the base wiring 120 is formed. That is, a new resist (not shown) is provided and a photolithography process is performed. Boron (B +) ions are implanted by exposing the formation region of the insulating region, the resist is removed, and annealing is performed at 500 ° C. for about 30 seconds. Thus, the collector insulating region formation 21 and the insulating region 20 reaching the substrate 1 are formed simultaneously (FIG. 9A). The collector layer 3 below the ballast resistor 102 is insulated by the collector insulating region 21. That is, in the region of the ballast resistor 102, the parasitic capacitance between the base and the collector can be greatly reduced.

  An impurity region such as a separation element (resistance) constituting the switch circuit device is also formed at the same time.

  Fourth step: A step of forming a transistor by forming a collector electrode, a base electrode, and an emitter electrode respectively connected to a collector layer, a base layer, and an emitter layer by using an ohmic metal layer.

  Next, a photolithography process for forming a first-layer emitter electrode and collector electrode is performed. After vapor deposition of the ohmic metal layer (AuGe / Ni / Au), lift-off and alloy are performed to form the emitter electrode 9 and the collector electrode 7 of the first layer of the unit HBT 101. The emitter electrode 9 and the collector electrode 7 are formed in a comb shape. Thereafter, a photolithography process for forming the base electrode is performed. After depositing the ohmic metal layer (Pt / Ti / Pt / Au), lift-off and alloying are performed to form the base electrode 8 of the unit HBT 101. At the same time, a resistive ohmic electrode 12 for the ballast resistor 102 is formed. The base electrode 8 has a pattern surrounding the emitter electrode 9 and the resistance ohmic electrode 12 has an island pattern, which are formed as hatched in FIG. 3A (FIG. 9B).

  A nitride film 51 serving as a passivation film is deposited on the entire surface. The nitride film 51 is etched to form a contact hole CH, and the resist is removed (FIG. 10A).

  Fifth step: a step of connecting a resistance layer and another resistance layer by a wiring metal layer and forming a wiring for connecting the transistor and another transistor.

  A new photolithography process is performed to deposit a second-layer electrode and a wiring metal layer (Ti / Pt / Au) to be a wiring on the entire surface. That is, the second-layer collector electrode 13 and the emitter electrode 15 are formed in contact with the first-layer collector electrode 7 and the emitter electrode 9, respectively. Further, a base wiring 120 that contacts the resistance ohmic electrode 12 is formed.

  Thereafter, polyimide 60 is applied to the entire surface. A photolithography process is performed to etch the polyimide 60 on the second-layer emitter electrode 15. Thereafter, the resist is removed and the polyimide 60 is cured.

  Next, a base metal layer (Ti / Pt / Au) (not shown) is deposited on the entire surface. A photolithography process is performed to expose the emitter wiring 150 pattern and apply gold plating. After removing the resist, unnecessary base metal layers are removed by ion milling. Thereby, an emitter wiring 150 for wiring the emitter electrodes 15 and 9 of each HBT 101 is formed. Further, a gold plating layer and each pad overlapping the collector wiring 130 are also formed.

  Next, a third embodiment of the present invention will be described with reference to FIG. 11 and FIG.

  The third embodiment is a switch circuit device that can operate with one control terminal by providing a logic circuit.

  FIG. 11 is a circuit diagram, and FIG. 11A shows a case where an inverter circuit 41 having a resistance load is connected as a logic circuit.

  In FIG. 11A, a resistance load 411 and a GaAs MESFET 412 (pinch-off voltage Vp = 0V: enhancement type) are connected in series at a connection point CP, and the connection point CP and, for example, the base of the second switching element SW2 are connected. The connection is made through the separation element 30. The gate of the MESFET 412 is connected to one control terminal Ctl.

  FIG. 11B shows a case where an inverter circuit 41 of an enhancement type / depletion type DCFL (Direct Coupled FET Logic) is connected as a logic circuit. That is, the source and gate of the depletion type MESFET 413 (pinch-off voltage Vp = −1V) and the drain of the enhancement type MESFET 414 (pinch-off voltage Vp = 0 V) are connected in series at the connection point CP, and the connection point CP and, for example, the second switching element The base of SW2 is connected via the separation element 30. Also, the gate of the enhancement type MESFET 414 is connected to one control terminal Ctl. In FIG. 11, the other components are the same as those in the first embodiment, and thus description thereof is omitted.

  By connecting the inverter circuit 41 in this way, the control signal applied to the control terminal Ctl is applied to the base of the first switching element SW1, and the complementary signal of the control signal is applied to the base of the second switching element SW2. . That is, the control terminal can be made one by the SPDT switch MMIC.

  The logic circuit 41 can also be formed of a resistor and / or MESFET. That is, the switch MMIC with the built-in logic circuit can be integrated on one chip of the GaAs substrate.

  FIG. 12 shows the inverter circuit 41 of the enhancement / depletion type DCFL shown in FIG. 12A is a plan pattern view, and FIG. 12B is a cross-sectional view taken along the line ee of FIG. 12A.

  In the D-type FET 413, the first gate electrode 127 is disposed between the source electrode 135d and the drain electrode 136d of the second layer made of the wiring metal layer. Below the source electrode 135d and the drain electrode 136d, a first source electrode 115d and a drain electrode 116d made of an ohmic metal layer are disposed, and the operation region is separated by the separation region 20 indicated by a two-dot chain line. The source electrode 115d and the drain electrode 116d are connected to the contact layers 6sd and 6dd, respectively.

  The first gate electrode 127 is disposed between the source electrode and the drain electrode, and is connected to the second-layer source electrode 135d outside the operation region.

In the E-type FET 414, the second source electrode 135e and the drain electrode 136e made of a wiring metal layer are alternately arranged, and the second gate electrode 128 is arranged therebetween.
Below the source electrode 135e and the drain electrode 136e, a first source electrode 115e and a drain electrode 116e made of an ohmic metal layer are disposed. The source electrode 115e and the drain electrode 116e are connected to the contact layers 6se and 6de, respectively.

  The drain electrode 136e of the second layer at the end of the E-type FET 414 (same as the drain electrode 116e of the first layer) is shared with the source electrode 135d of the second layer of the D-type FET 413 (same as the source electrode 115d of the first layer). is doing. Similarly, the contact layer 6de at the end of the E-type FET 414 is shared with the contact layer 6sd of the D-type FET 413.

  For the first gate electrode 127 and the second gate electrode 128, the deposition thickness of Pt of the gate metal layer (Pt / Mo) is made different, the embedding depth in the channel layer 5a is appropriately selected, and a predetermined pinch-off voltage Vp is set. Realized.

  In addition, each semiconductor layer of a figure can utilize the same layer as the semiconductor layer of unit HBT101. That is, the emitter contact layer 6, the emitter layer 5, and the base layer 4 of the unit HBT 101 can be shared with the contact layers 6sd, 6se, 6dd, and 6de, the channel layer 5a, and the p-type buffer layer 4a of the D-type FET 413 and the E-type FET 414, respectively.

Since all the HBTs 101 of the embodiment of the present invention are symmetrical, the emitter and collector of the HBT 101 may be interchanged in the first, second, and third embodiments.

It is a circuit diagram for demonstrating this invention. It is a top view for demonstrating this invention. It is (A) top view and (B) sectional view for explaining the present invention. It is (A) sectional drawing, (B) characteristic view, and (C) characteristic view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is a circuit diagram for demonstrating this invention. It is (A) top view and (B) sectional view for explaining the present invention. It is (A) circuit diagram and (B) sectional drawing for demonstrating the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 Subcollector layer 3 Collector layer 4 Base layer 5 Emitter layer 6 Emitter contact layer 7, 13 Collector electrode 8 Base electrode 9, 15 Emitter electrode 4a P-type buffer layer 5a Channel layer 6sd, 6se, 6dd, 6de Contact layer DESCRIPTION OF SYMBOLS 12 Resistance ohmic electrode 20 Insulation area | region 21 Collector insulation area | region 23 Impurity area | region 30 Separation element 32 Grading layer 41 Inverter circuit 51 Nitride film 60 Polyimide 100 Unit element 101 Unit HBT
102 Ballast resistor 115e, 115d, 135e, 135d Source electrode 116e, 116d, 136e, 136d Drain electrode 120 Base wiring 127 First gate electrode 128 Second gate electrode 130 Collector wiring 150 Emitter wiring 170 Peripheral impurity region 411 Resistance 412 MESFET
413 D-type FET
414 E-type FET
CP connection point IN common input terminal OUT1 first output terminal OUT2 second output terminal Ctl control terminal Ctl1 first control terminal Crl2 second control terminal I, O1, O2, C1, C2, G pad P pad
320 first HBT
321 second HBT
122 resistor 311 subcollector layer 312 collector layer 313 base layer 314 emitter layer 315 emitter contact layer 316 collector electrode 317 base electrode 318 emitter electrode

Claims (13)

A plurality of semiconductor layers stacked on a compound semiconductor substrate and forming at least one heterojunction;
A transistor provided on the substrate and having the collector layer, the base layer, and the emitter layer as the semiconductor layer, and a collector electrode, a base electrode, and an emitter electrode;
A resistance layer provided on the substrate and continuous with the base layer;
A unit element in which the resistance layer is connected to the base electrode of the transistor;
A switching element in which the unit elements are connected in parallel;
A first RF port connected to the collector electrode or emitter electrode of the switching element;
A plurality of second RF ports connected to an emitter electrode or a collector electrode of the switching element,
A switch circuit device, wherein a signal path is formed between the first and second RF ports by a control signal applied to a base electrode of the switching element.   2. The switch circuit device according to claim 1, wherein a first wiring layer connected to the resistance layer is provided, and the base electrode of the unit element and the base electrode of another unit element are commonly connected by the wiring layer.   2. A second wiring layer and a third wiring layer respectively connected to the emitter electrode and the collector electrode are provided, and the unit element and other unit elements are commonly connected by the second and third wiring layers. 2. The switch circuit device according to 1.   The transistor has a heterojunction between the emitter layer and the base layer and between the base layer and the collector layer, and the on-resistance value during forward transistor operation and the on-resistance value during reverse transistor operation are one base current value. The switch circuit device according to claim 1, wherein the switch circuit devices are substantially equal to each other.   2. The switch circuit according to claim 1, further comprising: a plurality of the switching elements and a logic circuit connected to at least one control terminal, wherein a control signal is applied to the base electrode from the one control terminal. apparatus.   The switch circuit device according to claim 1, wherein the base layer is a p + GaAs layer.   The switch circuit device according to claim 1, wherein the emitter layer is an InGaP layer or an AlGaAs layer.   The switch circuit device according to claim 1, wherein a collector current of the transistor has a negative temperature coefficient.   2. The switch circuit device according to claim 1, wherein bias points for applying an equal bias potential to the emitter electrode and the collector electrode are connected to each other.   10. The switch circuit device according to claim 9, wherein a high-frequency signal separation element is connected between the emitter electrode and the bias point and between the collector electrode and the bias point. 11.   2. The switch circuit device according to claim 1, wherein the collector layer below the resistance layer is insulated by ion implantation of impurities. Laminating a plurality of semiconductor layers forming at least one heterojunction on a compound semiconductor substrate;
Etching each of the semiconductor layers to form a collector layer, a base layer, and an emitter layer;
Forming a continuous resistance layer on the base layer;
Forming a transistor by forming a collector electrode, a base electrode, and an emitter electrode respectively connected to the collector layer, the base layer, and the emitter layer by an ohmic metal layer; and
And a step of connecting the resistance layer and the other resistance layer by a wiring metal layer, and forming a wiring for connecting the transistor and the other transistor. 13. The method of manufacturing a switch circuit device according to claim 12, wherein the collector layer below the resistance layer is insulated before the formation of the resistance layer.