JP2009064923A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having an ESD protection network capable of suppressing an increase in an area. <P>SOLUTION: The semiconductor device is provided with: a processing portion of a high-frequency signal with an input terminal 11 and an output terminal 21; a spiral shape p side region 17 which is a spiral and consecutive p side region; a spiral shape n side region 19 which is a consecutive n side region having the same form as the spiral shape p side region 17; and a spiral and consecutive pn junction having the same form constituted by bonding the spiral shape p side region 17 and the spiral shape n side region 19, wherein there is provided an ESD protection element in which an edge of the spiral shape n side region 19 used as an edge of a spiral is connected to the input terminal 11 and an edge of the spiral shape p side region 17 used as the other edge of the spiral is connected to a ground terminal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an ESD protection circuit.

  2. Description of the Related Art Semiconductor devices, particularly semiconductor devices using compound semiconductors, are widely used for microwave to millimeter wave high-frequency circuits because of their good high-frequency (RF) characteristics and the ability to easily obtain a semi-insulating substrate.

  Increasing the resistance of the high-frequency circuit to electrostatic discharge (hereinafter referred to as ESD) is to increase the reliability of the semiconductor device and is an important item. Here, ESD is a phenomenon in which high-energy charges accumulated in a device or a human body existing outside a circuit of a semiconductor device are instantaneously discharged to the circuit. Since ESD that occurs when a semiconductor device is incorporated into an application device is often unpredictable, it is required to ensure ESD tolerance on the circuit side of the semiconductor device.

  2. Description of the Related Art Conventionally, an ESD protection circuit of a semiconductor device uses a circuit format that prevents this high energy charge from flowing into a thermally weak semiconductor element. For example, a circuit in which a diode is connected between an input terminal to be protected and a ground terminal of the semiconductor device is used. When a voltage equal to or higher than the on-voltage of the diode is applied to the terminal, the diode becomes conductive and prevents charge from flowing into the protected circuit. The circuit connected to the diode has no practical problem as a protection circuit for terminals corresponding to direct current (DC) or low frequency operation such as a power supply terminal and a control terminal, but it is an input related to RF operation. For the terminal and the output terminal, there are problems such that the matching condition varies depending on the capacitance component of the diode, and the operation different from the design occurs due to the capacitance variation accompanying the voltage variation.

  As a countermeasure against this problem, for example, a protection circuit in which a diode and an inductor are connected in series between an input terminal and a ground terminal is disclosed (for example, see Patent Document 1).

However, the disclosed protection circuit can suppress the RF effect of the protection circuit even when the protection circuit is added to the input terminal, but when implementing this protection circuit as an actual semiconductor device, Since the diode and the inductor are arranged in parallel in a plane, there is a problem that a large area is required compared to a conventional protection circuit in which only the diode is arranged. In particular, since a semiconductor device using a compound semiconductor is expensive, not only can a demand for miniaturization due to an increase in area be satisfied, but it also has a problem of an increase in cost.
JP-A-10-173136 (page 3, FIG. 1)

  An object of the present invention is to provide a semiconductor device having an ESD protection circuit capable of suppressing an increase in area.

  A semiconductor device according to one embodiment of the present invention includes a processing portion having an input terminal for inputting a high-frequency signal and an output terminal for outputting the high-frequency signal, a p-side region that is continuous in a spiral, and a shape similar to that of the spiral. And the end of the n-side region that is one end of the spiral has the same shape as the spiral in which the p-side region and the n-side region are joined. An ESD protection element connected to a processing unit and having an end of a p-side region serving as the other end of the spiral connected to a ground terminal is provided.

  According to another aspect of the present invention, there is provided a semiconductor device having a processing unit having an input terminal for inputting a high-frequency signal and an output terminal for outputting a high-frequency signal, a continuous p-side region forming a spiral, and the same shape as the spiral. And an end portion of the n-side region which has a continuous pn junction having the same shape as the spiral in which the p-side region and the n-side region are joined, and serves as one end portion of the spiral. Is connected to a ground terminal, and an end portion of the p-side region which is the other end portion of the spiral is provided with an ESD protection element connected to the processing portion.

  According to the present invention, a semiconductor device having an ESD protection circuit capable of suppressing an increase in area can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the figure shown below, the same code | symbol is attached | subjected to the same component.

  A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a diagram schematically showing a high-frequency circuit including an ESD protection circuit used in a semiconductor device. FIG. 2 is a plan view schematically showing the semiconductor device. FIG. 3 schematically shows an ESD protection circuit of the semiconductor device, and is a cross-sectional view taken along the line AA of FIG.

  As shown in FIG. 1, the semiconductor device 1 includes a transistor 13 which is a high-frequency signal processing unit having an input terminal 11 for inputting a high-frequency signal and an output terminal 21 for outputting a high-frequency signal, a spiral p-side region 17, and a spiral. And a spiral pn junction 15 (using a diode symbol) in which the spiral p-side region 17 and the spiral n-side region 19 are joined, and is a spiral shape that is one end of the spiral. An ESD protection element 25 having an end portion of the n-side region 19 connected to the input terminal 11 and an end portion of the spiral p-side region 17 which is the other end portion of the spiral connected to the ground terminal 23 is provided.

  The transistor 13 is, for example, an npn heterojunction bipolar transistor, with the input terminal 11 connected to the base, the output terminal 21 connected to the collector, and the ground terminal 23 connected to the emitter. The high-frequency signal processing unit, that is, the transistor 13 is in a relationship of a protected circuit with respect to the protection circuit having the ESD protection element 25. The semiconductor device 1 processes, for example, amplifies the high-frequency signal input from the input terminal 11 via the transistor 13 and outputs the amplified signal to the output terminal 21.

  The spiral p-side region 17 of the ESD protection element 25 is shown in FIG. 1 as a configuration in which a plurality of discretely distributed inductors are connected in series. As will be described later, a single strip-shaped region 17 is formed. The p-side semiconductor layer and the electrode connected to the p-side semiconductor layer form one spiral.

  In the spiral n-side region 19, like the spiral p-side region 17, one n-side semiconductor layer having a band shape forms one spiral, that is, an inductor. The shape of the spiral n-side region 19 and the shape of the spiral p-side region 17 are not necessarily the same in the width of the band, but have the same number of turns.

  The spiral p-side region 17 and the spiral n-side region 19 are joined to form a spiral pn junction 15. In other words, the pn junction 15 is shown in FIG. 1 as a plurality of discretely distributed pn junctions 15, but like the spiral p-side region 17 and the spiral n-side region 19, the pn junction 15 is spiral. In the middle position between the p-side and n-side regions 17 and 19, a strip-shaped spiral is formed and has a continuous distribution. In other words, the ESD protection element 25 has a form in which a diode spreads in a spiral shape.

  As shown in FIG. 2, in the semiconductor device 1, the transistor 13 and the ESD protection element 25 are disposed adjacent to each other in a region surrounded by the element isolation region interface 31 a indicated by a broken line. The transistor 13 has a structure in which a collector electrode 33, an emitter electrode 35, and a base electrode 34 are disposed between these electrodes 33 and 35. The ESD protection element 25 has a spiral shape, and has an upper spiral p-side region 17 and a lower spiral n-side region 19 in the direction perpendicular to the paper surface in a substantially overlapping state.

  The base electrode 34 and the n-side electrode 43 at the end of the spiral n-side region 19 are connected to the input terminal 11 via the wiring layer 37. The collector electrode 33 is connected to the output terminal 21 through the wiring layer 39. The emitter electrode 35 is connected to the ground terminal 23 through a wiring layer (not shown), and the spiral p-side region 17 is connected to the ground terminal 23 through a wiring layer 38.

  As shown in FIG. 3, the ESD protection element 25 has a spiral n-side region 19 formed on the semi-insulating GaAs substrate 5 and a spiral p-side region 17 formed thereon. Yes. Isolation for forming a spiral shape of the ESD protection element 25, isolation from other elements, and the like are performed in an element isolation region 31 reaching the surface from the semi-insulating GaAs substrate 5.

  The spiral n-side region 19 has, for example, an n + type semiconductor layer 6 epitaxially grown on the GaAs substrate 5 and an n type semiconductor layer 7 grown thereon. For the n + -type and n-type semiconductor layers 6 and 7, for example, an n + -type and n-type GaAs layer common to the collector layer including the sub-collector layer used in the transistor 13 can be used.

  The spiral p-side region 17 includes, for example, a p-type semiconductor layer 8 that is epitaxially grown. As the p-type semiconductor layer 8, a p-type GaAs layer common to the base layer used in the transistor 13 can be used.

  Next, the structure of the ESD protection element 25 will be described, including the manufacturing method. After the epitaxial growth, an element isolation region 31 is formed in a region where the ESD protection element 25 patterned with a resist (not shown) or the like is formed, simultaneously with a region where the transistor 13 is formed, for example. The element isolation region 31 is arranged so that, for example, B or H is ion-implanted so as to reach the GaAs substrate 5 from the epitaxially grown layer, and is arranged between the elements, so as to form a spiral in the element. The

  As described above, the ESD protection element 25 uses an n + -type, n-type GaAs layer, and p-type GaAs layer that are epitaxially grown, which are constituent elements of the transistor 13, for example, a resist patterned by a photolithography method (illustrated). A mesa-shaped spiral is formed on the p-type semiconductor layer 8 and the n-type semiconductor layer 7 by etching. Since it is formed by etching, the pn junction 15 forms a spiral that is substantially the same as the shape of the p-type semiconductor layer 8. Further, the n-type semiconductor layer 7 is etched by a similar method to form an opening reaching the n + -type semiconductor layer 6.

  A p-side electrode 44 made of, for example, Pt / Ti / Pt / Au is formed on the patterned p-type semiconductor layer 8. On the other hand, an n-side electrode 43 made of, for example, AuGe / Ni / Au is formed in the opening reaching the n + type semiconductor layer 6.

  An insulating film 45 made of, for example, a silicon oxide film or a silicon nitride film is formed so as to cover the n-side electrode 43, the p-side electrode 44, the mesa-shaped slope and plane, and then the n-side electrode 43 An opening is provided in the insulating film 45 on the surface. A wiring layer 37 made of Ti / Pt / Au, for example, connected to the n-side electrode 43 through this opening is formed. Further, a wiring layer 38 made of Ti / Pt / Au connected to the p-side electrode 44 (not shown) is formed.

  A protective film 51 made of, for example, an organic film such as polyimide or an inorganic film such as a silicon oxide film and a silicon nitride film is formed so as to cover the wiring layers 37 and 38, the insulating film 45, and the like, and the semiconductor device 1 is completed. . Note that the protective film 51 can be shared with a protective film such as the transistor 13.

  As described above, the ESD protection element 25 forming the ESD protection circuit of the semiconductor device 1 has a spiral similar to the spiral p-side region 17 and the spiral p-side region 17 which are continuous p-side regions forming a spiral. A spiral n-side region 19 which is a continuous n-side region, and a continuous pn junction 15 in which a spiral p-side region 17 and a spiral n-side region 19 are joined in a perpendicular direction to the surface. And the end of the spiral n-side region 19 that is one end of the spiral is connected to the input terminal 11, and the end of the spiral p-side region 17 that is the other end of the spiral is connected to the ground terminal 23. Yes.

  The ESD protection element 25 has an inductor and a diode connected in series as an equivalent circuit. That is, the ESD protection element 25 has a high impedance in terms of high frequency, so that it is possible to suppress the influence of the high frequency signal that is the protected circuit of the semiconductor device 1 on the processing unit. On the other hand, the ESD protection element 25 is formed so that the inductor and the diode overlap with each other in the direction perpendicular to the surface in the same region. Therefore, the ESD protection element 25 is formed substantially only in the area required for the inductor. As compared with a case where the two are arranged in parallel in a plane, an increase in the occupied area is suppressed. As a result, an increase in the area of the semiconductor device 1 having the ESD protection circuit is suppressed.

  The ESD protection element 25 operates as a large-area diode in which the spiral p-side region 17 and the spiral n-side region 19 are bonded to a relatively low frequency component that is the main component of ESD. The diode having a large area has a characteristic that the ESD tolerance of the protection circuit itself including the ESD protection element 25 can be increased. In spite of the large-area diode, since the inductor is connected in series, the high-frequency component looks like a high impedance, so that the influence of the high-frequency characteristics on the protected circuit of the semiconductor device 1 can be suppressed.

  As described above, the semiconductor device 1 having the ESD protection element 25 has the same or more ESD protection characteristics as compared with the case where the inductor and the diode are arranged in parallel in a plane, and the increase in area is suppressed. As a result, an increase in cost can be suppressed.

  Further, the ESD protection element 25 has a predetermined inductance in the spiral p-side region 17 and the spiral n-side region 19, and parasitic capacitance is generated by a pn junction in which the spiral p-side and the n-type regions 17 and 19 are joined. Therefore, it is possible to function as a distributed constant type low-frequency component suppression filter based on inductance and parasitic capacitance. As a result, the semiconductor device 1 can remove a relatively low-frequency component and process a high-frequency signal with less noise.

  A semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 4 is a diagram schematically showing a high-frequency circuit including an ESD protection circuit used in a semiconductor device. FIG. 5 is a plan view schematically showing an ESD protection circuit in the semiconductor device. The difference from the ESD protection circuit of the first embodiment, that is, the ESD protection element 25 is that an inductor is further added in series. In addition, the same code | symbol is attached | subjected to the same component as Example 1, and the description is abbreviate | omitted.

  As shown in FIG. 4, the semiconductor device 2 has a configuration in which a spiral inductor 61 is added and connected between the input terminal 11 of the semiconductor device 1 of the first embodiment and the ESD protection element 25. . Specifically, the end of the spiral n-side region 19 that is one end of the spiral of the ESD protection element 25 is connected to the input terminal 11 via the inductor 61. The spiral winding direction of the inductor 61 is electrically opposite to the spiral winding direction of the ESD protection element 25.

  As shown in FIG. 5, the semiconductor device 2 partially shown includes an inductor 61 that is wound clockwise from the wiring layer 37 toward the n-side electrode 43 from the outside toward the inside. After the inductor 61 is connected to the n-side electrode 43, the spiral p-side, n-side regions 17, 19 and the like form a spiral wound clockwise from the inside to the outside, as in the first embodiment. The inductor 61 has substantially the same width as the spiral p-side region 17, is on the upper side in the direction perpendicular to the paper surface, and overlaps in many regions through an insulating film 45 (not shown). ing.

  As described above, the ESD protection circuit of the semiconductor device 2 similarly includes the ESD protection element 25 of the semiconductor device 1 of the first embodiment, and the end of the spiral n-side region 19 of the ESD protection element 25 is The inductor 61 is connected to the input terminal 11.

  As a result, the semiconductor device 2 has the same effects as the semiconductor device 1 of the first embodiment. In addition, since the inductor 61 is provided at a position corresponding to the position directly above the spiral p-side region 17, an increase in inductance, that is, an impedance in terms of high frequency, while an increase in the area occupied by the ESD protection circuit is suppressed. The increase is planned.

  Further, since the inductor 61 has a winding direction that is electrically opposite to the spiral of the ESD protection element 25, the mutual inductance of both is added, and the impedance is further increased in terms of high frequency.

  As mentioned above, this invention is not limited to the said Example, In the range which does not deviate from the summary of this invention, it can change and implement variously.

  For example, in the embodiment, the example in which the processing unit of the high-frequency signal of the semiconductor device is an npn type heterojunction bipolar transistor has been described, but this may be a pnp type heterojunction bipolar transistor, MESFET (Metal Semiconductor Field Effect Transistor), JFET. (Junction FET), HEMT (High Electron Mobility Transistor), etc. can be replaced. In this case, the polarity of the ESD protection element can be set to a direction suitable for ESD protection of each high-frequency circuit.

  In the embodiment, the n-side region and the p-side region of the ESD protection element of the ESD protection circuit are connected to the input terminal and the ground terminal, respectively. However, the p-side region and the n-side region of the ESD protection element are shown. Can be connected to the input terminal and the ground terminal, respectively. In addition, it is possible to connect regions having different polarities of the two ESD protection elements to the input terminal and to connect regions having opposite polarities to the ground terminal.

  In the embodiment, the example in which the n-side region and the p-side region of the ESD protection element of the ESD protection circuit are connected to the input terminal and the ground terminal, respectively. Are connected to the output terminal and the ground terminal, respectively, the n-side region and the p-side region of the ESD protection element are connected to the ground terminal and the output terminal, respectively, and the two ESD protection elements have different polarities. Can be connected to the output terminal, and regions having different polarities can be connected to the ground terminal.

  In the embodiment, the example in which the inductor of the ESD protection circuit is connected between the ESD protection element and the high-frequency signal processing unit is shown. However, the inductor is connected between the ESD protection element and the ground terminal. Is possible.

  In the embodiments, an example in which a GaAs substrate is used as the semiconductor device is shown, but another compound semiconductor substrate such as InP or GaN, an oxide substrate, or the like can be used as the semiconductor device.

  In the embodiment, the p-type and n-type semiconductor layers are formed by epitaxial growth. However, all or part of the semiconductor layers can be formed by ion implantation or the like.

  In the embodiment, the ESD protection element or the like is connected to the processing unit having the input terminal and the output terminal, but other circuits or the like for improving the quality of the high-frequency signal may be further connected.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A processing unit having an input terminal for inputting a high-frequency signal and an output terminal for outputting a high-frequency signal, a p-side region continuous in a spiral, an n-side region continuous in the same shape as the spiral, and The p-side region and the n-side region have a continuous pn junction having the same shape as the spiral, and the end of the n-side region serving as one end of the spiral is connected to the processing unit, A semiconductor device comprising: an ESD protection element in which an end of a p-side region serving as the other end of the spiral is connected to a ground terminal.

(Additional remark 2) The said process part is a semiconductor device of Additional remark 1 which has a heterojunction bipolar transistor.

(Supplementary Note 3) The n-type semiconductor layer in the n-side region is an n-type semiconductor layer equivalent to the collector layer of the heterojunction bipolar transistor, and the p-type semiconductor layer in the p-side region is the heterojunction bipolar. The semiconductor device according to appendix 2, which is a p-type semiconductor layer equivalent to a base layer of a transistor.

BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows typically the high frequency circuit containing the ESD protection circuit used for the semiconductor device which concerns on Example 1 of this invention. 1 is a plan view schematically showing a semiconductor device according to Example 1 of the present invention. FIG. 3 is a diagram schematically illustrating the ESD protection circuit of the semiconductor device according to the first embodiment of the invention, and a cross-sectional view taken along line AA in FIG. 2. The figure which shows typically the high frequency circuit containing the ESD protection circuit used for the semiconductor device which concerns on Example 2 of this invention. The top view which shows typically the ESD protection circuit in the semiconductor device which concerns on Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Semiconductor device 5 GaAs substrate 6 n + type semiconductor layer 7 n type semiconductor layer 8 p type semiconductor layer 11 Input terminal 13 Transistor 15 pn junction 17 Spiral p side area 19 Spiral n side area 21 Output terminal 23 Ground terminal 25 ESD protection element 31 Element isolation region 31a Element isolation region interface 33 Collector electrode 34 Base electrode 35 Emitter electrodes 37, 38, 39 Wiring layer 43 N side electrode 44 P side electrode 45 Insulating film 51 Protective film 61 Inductor

Claims (5)

A processing unit having an input terminal for inputting a high-frequency signal and an output terminal for outputting the high-frequency signal;
A p-side region continuous in a spiral, an n-side region continuous in the same shape as the spiral, and a pn junction continuous in the same shape as the spiral in which the p-side region and the n-side region are joined. An ESD protection element having an end of the n-side region serving as one end of the spiral connected to the processing unit and an end of the p-side region serving as the other end of the spiral connected to a ground terminal; ,
A semiconductor device comprising:   An inductor having a shape similar to the spiral and substantially overlapping in plan view is formed between the end of the n-side region and the processing unit, and between the end of the p-side region and the ground terminal. The semiconductor device according to claim 1, wherein the semiconductor device is additionally provided in at least one of them. A processing unit having an input terminal for inputting a high-frequency signal and an output terminal for outputting the high-frequency signal;
A p-side region continuous in a spiral, an n-side region continuous in the same shape as the spiral, and a pn junction continuous in the same shape as the spiral in which the p-side region and the n-side region are joined. An ESD protection element in which an end of the n-side region serving as one end of the spiral is connected to a ground terminal and an end of the p-side region serving as the other end of the spiral is connected to the processing unit; ,
A semiconductor device comprising:   An inductor having a shape similar to the spiral and substantially overlapping in plan view is formed between the end of the n-side region and the ground terminal, and between the end of the p-side region and the processing unit. The semiconductor device according to claim 3, wherein the semiconductor device is additionally provided in at least one of them.   5. The semiconductor device according to claim 2, wherein the inductor has a winding direction that is electrically opposite to a winding direction of the ESD protection element. 6.

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