TW202418544A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a high electron mobility transistor disposed in an annular active element region, and a resistor disposed in a passive element region surrounded by the annular active element region. The high electron mobility transistor includes a first portion of a compound semiconductor barrier layer stacked on a first portion of a compound semiconductor channel layer, and a source electrode, a gate electrode, and a drain electrode disposed on the first portion of the compound semiconductor barrier layer. The resistor includes a second portion of the compound semiconductor barrier layer stacked on a second portion of the compound semiconductor channel layer, and an input terminal electrode disposed on the second portion of the compound semiconductor barrier layer and located at the center of the passive element region.

Description

Semiconductor Devices

The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices integrating high electron mobility transistors and resistors.

In semiconductor technology, III-V compound semiconductors can be used to form various integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors, or high electron mobility transistors (HEMTs). HEMTs are transistors with a two-dimensional electron gas (2DEG) adjacent to the junction between two materials with different band gaps (i.e., heterojunctions). Since HEMTs use 2DEG as the carrier channel of the transistor instead of the doped region, they have many attractive properties compared to the conventional metal oxide semiconductor field effect transistor (MOSFET), such as high electron mobility, the ability to transmit signals at high frequencies, high breakdown voltage, and low on-resistance.

In recent years, HEMTs have been used in many applications, such as battery monitoring and management systems, three-phase motor control circuits, etc., due to their high breakdown voltage and low on-resistance. In these applications, accurate sensing of the high-voltage terminal current is required, such as using an inductive current sensing resistor, which is usually an independent component separated from the HEMT and electrically connected to the HEMT to form an electronic circuit. However, an independent inductive current sensing resistor separated from the HEMT requires a larger footprint for the electronic circuit and increases manufacturing costs.

In view of this, the present disclosure proposes a semiconductor device that integrates a resistor in a region where a high electron mobility transistor is formed, so that the resistor electrically connected to the high electron mobility transistor does not occupy additional area, which can save the layout area of the electronic circuit. In addition, the resistor of the embodiment of the present disclosure is a resistor using a two-dimensional electron gas (2DEG). Compared with a silicon-based resistor, the resistor of the embodiment of the present disclosure is more accurate in sensing current and is more electrically robust. At the same time, the manufacturing process of the resistor of the embodiment of the present disclosure and the high electron mobility transistor can be integrated together, which is relatively simple in manufacturing.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a high electron mobility transistor and a resistor. The high electron mobility transistor is arranged in an annular active element region, and the resistor is arranged in a passive element region surrounded by the annular active element region. The high electron mobility transistor includes a first portion of a compound semiconductor barrier layer stacked on a first portion of a compound semiconductor channel layer, and a source electrode, a gate electrode, and a drain electrode arranged on the first portion of the compound semiconductor barrier layer. The resistor includes a second portion of a compound semiconductor barrier layer stacked on a second portion of the compound semiconductor channel layer, and an input terminal electrode arranged on the second portion of the compound semiconductor barrier layer and located at the center of the passive element region.

In order to make the features of the present disclosure clear and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and layouts. The purpose of providing these embodiments is only for illustration and not for any limitation. For example, the description below of "a first feature is formed on or above a second feature" may mean "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, and are not used to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in the present disclosure, such as "under", "low", "down", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they themselves do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupled", "coupled", and "electrically connected" mentioned in the present disclosure include any direct and indirect electrical connection means. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

In the present disclosure, "compound semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element. The group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Furthermore, the "compound semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), their analogs or combinations of the above compounds, but not limited thereto. In addition, depending on the needs, the compound semiconductor may also include dopants to be a compound semiconductor with a specific conductivity type, such as an n-type or p-type compound semiconductor. Hereinafter, compound semiconductors may also be referred to as III-V semiconductors.

Although the invention disclosed herein is described below by means of specific embodiments, the inventive principles of the invention disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and the omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a semiconductor device that integrates a high electron mobility transistor and a resistor, wherein the resistor is integrated in a region where the high electron mobility transistor is formed, the resistor is electrically connected to the high electron mobility transistor, and does not occupy an additional area, thereby saving the layout area of the electronic circuit. In addition, the resistor of the embodiment of the present disclosure is a two-dimensional electron gas (2DEG) resistor, which is more accurate in sensing current and more electrically robust and durable than a silicon-based resistor. At the same time, the manufacturing processes of the resistor and the high electron mobility transistor of the embodiment of the present disclosure can be integrated together, and there is no need to form an additional photoresist layer to make the resistor, so the manufacturing process is simple and the manufacturing cost can be reduced.

FIG. 1 is a schematic top view of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes an annular active device region 100A and a passive device region 100R surrounded by the annular active device region 100A. A high electron mobility transistor (HEMT) of the semiconductor device 100 is disposed in the annular active device region 100A, and a resistor of the semiconductor device 100 is disposed in the passive device region 100R. The high electron mobility transistor (HEMT) includes a first portion 107-1 of a compound semiconductor barrier layer stacked on a first portion 105-1 of a compound semiconductor channel layer. As shown in FIG. 1 , in one embodiment, the first portion 107-1 of the compound semiconductor barrier layer and the first portion 105-1 of the compound semiconductor channel layer are vertically aligned, and the top view shape thereof is a circular ring, that is, the top view shape of the annular active device region 100A is a circular ring. In other embodiments, the top view shape of the annular active device region 100A may be an elliptical ring, a rectangular ring, a polygonal ring, or an annular region of other geometric shapes. In addition, the high electron mobility transistor (HEMT) further includes a source electrode 140, a gate electrode 130, and a drain electrode 120 disposed on the first portion 107-1 of the compound semiconductor barrier layer. As shown in FIG. 1 , in one embodiment, the top-view shapes of the source electrode 140, the gate electrode 130, and the drain electrode 120 are circular rings separated from each other, but are not limited thereto. The top-view shapes of the source electrode 140, the gate electrode 130, and the drain electrode 120 may also be elliptical rings, rectangular rings, or polygonal rings, which may be adjusted according to the top-view shape of the annular active device region 100A. In addition, the drain electrode 120 is adjacent to the passive device region 100R, the source electrode 140 is distant from the passive device region 100R, and the gate electrode 130 is located between the source electrode 140 and the drain electrode 120. In some embodiments, the distance between the drain electrode 120 and the gate electrode 130 may be greater than the distance between the source electrode 140 and the gate electrode 130.

In addition, the resistor of the semiconductor device 100 includes a second portion 107-2 of the compound semiconductor barrier layer stacked on the second portion 105-2 of the compound semiconductor channel layer, and an input terminal electrode 110 disposed on the second portion 107-2 of the compound semiconductor barrier layer and located at the center of the passive device region 100R. As shown in FIG. 1 , in one embodiment, the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer are vertically aligned, and their top view shape is a radial shape radiating from the input terminal electrode 110 toward the drain electrode 120, and the gap between the radial shapes can be filled with an insulating material 109. In some embodiments, the compound semiconductor channel layer is composed of, for example, gallium nitride (GaN), and the compound semiconductor barrier layer is composed of, for example, aluminum gallium nitride (AlGaN). The stacked structure of the second portion 107-2 of the compound semiconductor barrier layer and the second portion 105-2 of the compound semiconductor channel layer in the passive device region 100R can generate a two-dimensional electron gas (2DEG) near the junction interface between two materials with different energy gaps, that is, the two-dimensional electron gas (2DEG) is generated in the second portion 105-2 of the compound semiconductor channel layer and is close to the second portion 107-2 of the compound semiconductor barrier layer. Therefore, the resistor of the semiconductor device 100 can also be called a two-dimensional electron gas (2DEG) resistor. In this embodiment, the resistance value of the resistor can be changed by adjusting the area ratio of the second portion 107-2 of the radiation-shaped compound semiconductor barrier layer and the second portion 105-2 of the compound semiconductor channel layer in the passive device region 100R. The higher the area ratio of the radiation-shaped portion is, the lower the resistance value of the resistor is.

FIG. 2 is a circuit diagram of a semiconductor device 100 according to some embodiments of the present disclosure. One end of a resistor R in a passive device region 100R of the semiconductor device 100 is electrically coupled to an input terminal electrode 110 to receive a high voltage VH. The other end of the resistor R is electrically coupled to a drain electrode D of a high electron mobility transistor HEMT in a ring-shaped active device region 100A. The drain voltage VD obtained by reducing the high voltage VH through the resistor R is transmitted to the drain electrode D, wherein the potential of the input terminal electrode 110 is higher than the potential of the drain electrode D. The gate electrode G of the high electron mobility transistor HEMT receives the gate voltage VG, and the source electrode S of the high electron mobility transistor HEMT is electrically coupled to a low voltage end voltage VL, such as a ground end. According to an embodiment of the present disclosure, the resistor R of the semiconductor device 100 is disposed at the high voltage end of the circuit and is connected in series with the high electron mobility transistor (HEMT), whereby the resistor R can be used to monitor the high voltage end current to protect the high electron mobility transistor HEMT.

FIG. 3 is a schematic cross-sectional view of a semiconductor device 100 along the cross-sectional cut line A-A' of FIG. 1 according to an embodiment of the present disclosure. The semiconductor device 100 includes a substrate 101. In some embodiments, the material of the substrate 101 may include ceramic, silicon carbide (SiC), aluminum nitride (AlN), sapphire or silicon. When the substrate 101 is a material with high hardness, high thermal conductivity and low electrical conductivity, such as a ceramic substrate, it is more suitable for high-voltage semiconductor devices. The above-mentioned high hardness, high thermal conductivity and low electrical conductivity are relative to a single crystal silicon substrate, and a high-voltage semiconductor device refers to a semiconductor device with an operating voltage higher than 50V. In some embodiments, the substrate 101 may be a semiconductor on insulator (SOI) substrate. In other embodiments, the substrate 101 may be provided by a composite substrate (also referred to as a QST substrate) in which a core substrate is wrapped by a composite material layer, wherein the core substrate comprises ceramic, silicon carbide, aluminum nitride, sapphire or silicon, and the composite material layer comprises an insulating material layer and a semiconductor material layer, wherein the insulating material layer may be a single layer or multiple layers of silicon oxide, silicon nitride or silicon oxynitride, and the semiconductor material layer may be silicon or polycrystalline silicon, and the composite material layer located on the back side of the core substrate is removed by a thinning process, such as by a grinding or etching process, so that the back side of the core substrate is exposed.

In addition, the semiconductor device 100 further includes a buffer layer 103, a compound semiconductor channel layer 105, and a compound semiconductor barrier layer 107 stacked sequentially from bottom to top on the substrate 101. The buffer layer 103 can be used to reduce the stress or lattice mismatch between the substrate 101 and the compound semiconductor channel layer 105. In some embodiments, a nucleation layer can be disposed between the buffer layer 103 and the substrate 101, and a high resistance layer (or electrical isolation layer) can be disposed between the buffer layer 103 and the compound semiconductor channel layer 105. The materials of the seed layer, the buffer layer 103 and the high resistance layer include compound semiconductors. In some embodiments, the seed layer is, for example, an aluminum nitride (AlN) layer, the buffer layer 103 can be a superlattice (SL) structure, for example, including a plurality of layers of alternatingly stacked aluminum gallium nitride (AlGaN) layers and aluminum nitride (AlN) layers, and the high resistance layer is, for example, a carbon-doped gallium nitride (c-GaN) layer, but is not limited thereto. In addition, in some embodiments, the compound semiconductor channel layer 105 is, for example, an undoped gallium nitride (u-GaN) layer, and the compound semiconductor barrier layer 107 is a compound semiconductor layer having a larger energy gap than the compound semiconductor channel layer 105, such as an aluminum gallium nitride (AlGaN) layer, but is not limited thereto. The composition and structural configuration of the above-mentioned compound semiconductor layers of the semiconductor device 100 can be determined according to the requirements of various semiconductor devices.

Still referring to FIG. 3 , the compound semiconductor channel layer 105 of the semiconductor device 100 includes a first portion 105-1 located in the annular active device region 100A and a second portion 105-2 located in the passive device region 100R, and the compound semiconductor barrier layer 107 also includes a first portion 107-1 located in the annular active device region 100A and a second portion 107-2 located in the passive device region 100R. In addition, a source electrode 140, a gate electrode 130 and a drain electrode 120 are disposed on the first portion 107-1 of the compound semiconductor barrier layer 107 in the annular active device region 100A to form a high electron mobility transistor. In some embodiments, the high electron mobility transistor (HEMT) is an enhanced mode HEMT, and a compound semiconductor capping layer (not shown) is disposed between the gate electrode 130 and the first portion 107 - 1 of the compound semiconductor barrier layer 107. In other embodiments, the high electron mobility transistor (HEMT) is a depletion mode HEMT, and the gate electrode 130 may be disposed in a recess of the first portion 107 - 1 of the compound semiconductor barrier layer 107. In addition, an input electrode 110 is set on the second part 107-2 of the compound semiconductor barrier layer 107 in the passive device region 100R, a voltage (e.g., a high voltage) is received by the input electrode 110, and a stacked structure of the second part 105-2 of the compound semiconductor channel layer 105 and the second part 107-2 of the compound semiconductor barrier layer 107 serves as a resistor material. In some embodiments, the composition of the input electrode 110 can be the same as that of the source electrode 140 and the drain electrode 120, such as titanium (Ti), aluminum (Al), nickel (Ni), gold (Au) or a multi-layer stacked structure of the aforementioned metal layers, and the source electrode 140, the drain electrode 120 and the input electrode 110 can be formed simultaneously using the same process steps.

FIG. 4 is a schematic top view of a semiconductor device 100 according to another embodiment of the present disclosure. The difference between the semiconductor device 100 in FIG. 4 and FIG. 1 is that the stacking structure of the second portion 105-2 of the compound semiconductor channel layer 105 and the second portion 107-2 of the compound semiconductor barrier layer 107 in the passive element region 100R of the semiconductor device 100 in FIG. 4 is in a spiral shape when viewed from top. One end of the spiral is connected to the input electrode 110, and the other end of the spiral is connected to the drain electrode 120, that is, the spiral is connected from the input electrode 110 to the drain electrode 120, and the gap between the spirals can be filled with the insulating material 109. This embodiment also uses the two-dimensional electron gas (2DEG) generated by the stacked structure of the second part 105-2 of the compound semiconductor channel layer and the second part 107-2 of the compound semiconductor barrier layer as a resistor, so it can also be called a two-dimensional electron gas (2DEG) resistor. In this embodiment, the resistance value of the resistor can be changed by adjusting the number of turns of the spiral. When the number of turns of the spiral is more, the path of the current from the input electrode 110 to the drain electrode 120 is longer, and the resistance value of the resistor is higher.

FIG. 5 is a schematic cross-sectional view of a semiconductor device 100 along the cross-sectional cut line B-B' of FIG. 4 according to another embodiment of the present disclosure. In the semiconductor device 100 of FIG. 5, the stacked structure of the second portion 105-2 of the compound semiconductor channel layer 105 and the second portion 107-2 of the compound semiconductor barrier layer 107 in the passive device region 100R is in a spiral shape when viewed from above, and the space between the spirals is filled with an insulating material 109, such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. In addition, an input terminal electrode 110 is disposed on the second portion 107-2 of the compound semiconductor barrier layer 107 in the passive device region 100R. In one embodiment, the input electrode 110 overlaps with a portion of the spiral end and a portion of the insulating material 109 in a top view.

FIG. 6 is a schematic top view of a semiconductor device 100 according to yet another embodiment of the present disclosure. In the semiconductor device 100 of FIG. 6 , the stacked structure of the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer of the passive device region 100R has a top view shape of a plurality of rings separated from each other. These rings separated from each other are arranged in a concentric circle manner between the input electrode 110 and the drain electrode 120. In addition, the resistor of the passive device region 100R further includes a plurality of conductive rings 150 separated from each other, which are disposed on the second portion 107-2 of the compound semiconductor barrier layer. In a top view, these conductive rings 150 separated from each other are located between a plurality of rings separated from each other formed by the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer, so as to electrically connect these rings in series. In addition, these conductive rings 150 separated from each other are laterally separated from the input electrode 110 of the resistor. This embodiment also utilizes the two-dimensional electron gas (2DEG) generated by the stacked structure of the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer as a resistor, and therefore can be called a two-dimensional electron gas (2DEG) resistor, wherein a plurality of conductive rings 150 separated from each other are used to electrically connect the separated rings that generate the two-dimensional electron gas (2DEG). In this embodiment, the resistance value of the resistor can be changed by adjusting the number of the separated rings. When the number of rings is greater, the path of the current from the input terminal electrode 110 to the drain electrode 120 is longer, and the resistance value of the resistor is higher.

FIG. 7 is a schematic cross-sectional view of the semiconductor device 100 along the cross-sectional cut line C-C’ of FIG. 6 according to yet another embodiment of the present disclosure. In the semiconductor device 100 of FIG. 7 , the stacked structure of the second portion 105-2 of the compound semiconductor channel layer 105 and the second portion 107-2 of the compound semiconductor barrier layer 107 of the passive device region 100R is in the shape of a plurality of rings separated from each other in a top view, and the gaps between these rings are filled with an insulating material 109, such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. In addition, on the second portion 107-2 of the compound semiconductor barrier layer 107 of the passive device region 100R, an input electrode 110 is set at the center of the passive device region 100R, and a plurality of conductive rings 150 separated from each other are set between the input electrode 110 and the drain electrode 120. When viewed from above, these conductive rings 150 partially overlap with the aforementioned plurality of separated rings, and the input electrode 110 is located directly above a portion of the insulating material 109, and these conductive rings 150 are located directly above another portion of the insulating material 109. In some embodiments, the composition of the input electrode 110 and the conductive rings 150 may be the same as that of the source electrode 140 and the drain electrode 120, such as titanium (Ti), aluminum (Al), nickel (Ni), gold (Au) or a multi-layer stacked structure of the aforementioned metal layers, and the source electrode 140, the drain electrode 120, the input electrode 110 and the conductive rings 150 may be formed simultaneously using the same process steps.

FIG. 8 is a schematic top view of a semiconductor device 100 according to yet another embodiment of the present disclosure. In the semiconductor device 100 of FIG. 8 , the stacked structure of the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer of the passive device region 100R is circular in top view, and the input terminal electrode 110 is located at the center of the circle. In addition, the resistor of the passive device region 100R further includes a spiral conductor 160 connected from the input terminal electrode 110 to the drain electrode 120, which is disposed on the second portion 107-2 of the compound semiconductor barrier layer. This embodiment can also utilize the two-dimensional electron gas (2DEG) generated by the stacked structure of the second part 105-2 of the compound semiconductor channel layer and the second part 107-2 of the compound semiconductor barrier layer as a resistor, and can therefore be called a two-dimensional electron gas (2DEG) resistor, wherein the spiral conductor 160 connected from the input electrode 110 to the drain electrode 120 can be used as one of the current paths, thereby adjusting the resistance value of the resistor, for example, the number of turns of the spiral conductor 160 can be increased to increase the resistance value of the resistor.

In some embodiments, an insulating doped region is formed in the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer to form a two-dimensional electron gas (2DEG) as a resistor in a top view in a radial shape radiating from the input electrode 110 toward the drain electrode 120, a spiral shape connecting from the input electrode 110 to the drain electrode 120, or a concentric circle shape arranged from the input electrode 110 to the drain electrode 120. The insulating doped region may be formed, for example, by applying external energy to destroy the lattice of the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer, or by performing an ion implantation process to implant specific non-conductive dopants into the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer.

FIG. 9 is a schematic cross-sectional view of a semiconductor device 100 along the cross-sectional cut line D-D’ of FIG. 8 according to yet another embodiment of the present disclosure. In the semiconductor device 100 of FIG. 9 , the input electrode 110 and the spiral conductor 160 are both disposed on the second portion 107-2 of the compound semiconductor barrier layer of the passive device region 100R, and the input electrode 110 is in contact with a partial section of one end of the spiral conductor 160 and is connected to each other. In one embodiment, the input electrode 110 and the spiral conductor 160 may be formed by the same conductive layer, for example, by depositing and patterning the same metal layer to simultaneously form the input electrode 110 and the spiral conductor 160. The input electrode 110 and the spiral conductor 160 may be made of metal or polysilicon, for example.

The semiconductor device of the embodiment of the present disclosure integrates a resistor and a high electron mobility transistor, wherein the resistor is a two-dimensional electron gas (2DEG) resistor, and the resistor is arranged in the region where the high electron mobility transistor is formed, so that the resistor does not occupy an additional area, which can save the layout area of the electronic circuit. In addition, compared with silicon-based resistors, the two-dimensional electron gas (2DEG) resistor of the embodiment of the present disclosure is more accurate in sensing current and is more durable in terms of electrical properties. In addition, one end of the resistor of the embodiment disclosed herein can be electrically coupled to the high voltage end of the circuit, and the other end of the resistor can be electrically coupled to the drain electrode of the high electron mobility transistor, so that the resistor can be used to monitor the current at the high voltage end to protect the high electron mobility transistor. In addition, the manufacturing process of the resistor and the high electron mobility transistor of the embodiment disclosed herein can be integrated together, and no additional photoresist layer needs to be formed, and no additional photolithography and etching process needs to be performed. The resistor and the high electron mobility transistor can be manufactured at the same time. Therefore, the manufacturing process steps of the semiconductor device of the embodiment disclosed herein are simple, and the manufacturing cost can be reduced. The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: semiconductor device 100A: annular active element region 100R: passive element region 101: substrate 103: buffer layer 105: compound semiconductor channel layer 105-1: first part of compound semiconductor channel 105-2: second part of compound semiconductor channel 107: compound semiconductor barrier layer 107-1: first part of compound semiconductor barrier layer 107-2: second part of compound semiconductor barrier layer 109: insulating material 110: input electrode 120, D: drain electrode 130, G: gate electrode 140, S: source electrode 150: Multiple conductive rings separated from each other 160: Helical conductor VH: High voltage VD: Drain voltage VG: Gate voltage VL: Low voltage R: Resistor HEMT: High electron mobility transistor

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to at the same time when reading this disclosure. Through the specific embodiments in this article and referring to the corresponding drawings, the specific embodiments of the disclosure are explained in detail, and the working principle of the specific embodiments of the disclosure is explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced. Figure 1 is a schematic top view of a semiconductor device drawn according to an embodiment of the disclosure. Figure 2 is a circuit diagram of a semiconductor device drawn according to some embodiments of the disclosure. Figure 3 is a schematic cross-sectional view of a semiconductor device along the cross-sectional tangent line A-A' of Figure 1 drawn according to an embodiment of the disclosure. FIG. 4 is a schematic diagram of a semiconductor device according to another embodiment of the present disclosure, viewed from above. FIG. 5 is a schematic diagram of a cross-section of a semiconductor device along the cross-section line B-B' of FIG. 4, viewed from above. FIG. 6 is a schematic diagram of a semiconductor device according to another embodiment of the present disclosure, viewed from above. FIG. 7 is a schematic diagram of a cross-section of a semiconductor device according to another embodiment of the present disclosure, viewed from above. FIG. 8 is a schematic diagram of a semiconductor device according to another embodiment of the present disclosure, viewed from above. FIG. 9 is a schematic diagram of a cross-section of a semiconductor device according to another embodiment of the present disclosure, viewed from above.

100:Semiconductor devices

100A: Ring-shaped active component area

100R: Passive component area

105-1: The first part of the compound semiconductor channel

105-2: The second part of the compound semiconductor channel

107-1: The first part of the compound semiconductor barrier layer

107-2: The second part of the compound semiconductor barrier layer

109: Insulation materials

110: Input electrode

120. D: Drain electrode

130. G: Gate electrode

140, S: source electrode

Claims (13)

A semiconductor device, comprising: A high electron mobility transistor, arranged in an annular active element region, comprising: A first portion of a compound semiconductor channel layer; A first portion of a compound semiconductor barrier layer, stacked on the first portion of the compound semiconductor channel layer; and A source electrode, a gate electrode and a drain electrode, arranged on the first portion of the compound semiconductor barrier layer; and A resistor, arranged in a passive element region surrounded by the annular active element region, comprising: A second portion of the compound semiconductor channel layer; A second portion of the compound semiconductor barrier layer, stacked on the second portion of the compound semiconductor channel layer; and An input electrode is disposed on the second portion of the compound semiconductor barrier layer and is located at the center of the passive device region. A semiconductor device as described in claim 1, wherein the resistor is a two-dimensional electron gas and its top-view shape includes a radiation shape, a spiral shape or a concentric circle shape from the input electrode toward the drain electrode. A semiconductor device as described in claim 1, wherein one end of the resistor is electrically coupled to the input electrode, and the other end of the resistor is electrically coupled to the drain electrode. A semiconductor device as described in claim 1, wherein the second portion of the compound semiconductor channel layer of the resistor and the second portion of the compound semiconductor barrier layer are vertically aligned, and their top-view shape includes a radiating shape or a spiral shape from the input electrode toward the drain electrode. A semiconductor device as described in claim 4, wherein the gaps between the radiating shapes or the spiral shapes are filled with an insulating material. A semiconductor device as described in claim 1, wherein the second portion of the compound semiconductor channel layer of the resistor and the second portion of the compound semiconductor barrier layer are vertically aligned, and its top-view shape includes a plurality of rings separated from each other and arranged in a concentric manner between the input electrode and the drain electrode. A semiconductor device as described in claim 6, wherein the resistor further includes a plurality of conductive rings separated from each other, disposed on the second portion of the compound semiconductor barrier layer, such that in a top view, the plurality of conductive rings separated from each other are located between the plurality of rings separated from each other to electrically connect the plurality of rings separated from each other in series. A semiconductor device as described in claim 6, wherein the gaps between the plurality of rings separated from each other are filled with an insulating material. A semiconductor device as described in claim 8, wherein the input electrode is located above a portion of the insulating material, and the plurality of conductive rings separated from each other are located above another portion of the insulating material. A semiconductor device as described in claim 1, wherein the second portion of the compound semiconductor channel layer of the resistor is vertically aligned with the second portion of the compound semiconductor barrier layer, and its top-view shape includes a circle, and the input electrode is located at the center of the circle. A semiconductor device as described in claim 10, wherein the resistor further includes a spiral conductor connected from the input electrode to the drain electrode, and is disposed on the second portion of the compound semiconductor barrier layer. A semiconductor device as described in claim 1, wherein the top-view shapes of the source electrode, the gate electrode and the drain electrode include three rings separated from each other. A semiconductor device as described in claim 1, wherein the potential of the input electrode is higher than the potential of the drain electrode.

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