TWI837931B - Semiconductor device and fabrication method thereof - Google Patents

Abstract

A semiconductor device includes a substrate having an active element region and a passive element region. A compound semiconductor channel layer, a compound semiconductor barrier layer and a first compound semiconductor cap layer are disposed on the substrate in sequence and located in the active element region A gate electrode is disposed on the first compound semiconductor cap layer. A source electrode and a drain electrode are disposed on the compound semiconductor barrier layer and located on two sides of the gate electrode, respectively, to construct a high electron mobility transistor. A second compound semiconductor cap layer is disposed on the substrate and located in the passive element region to construct a resistor.

Description

Semiconductor device and method for manufacturing the same

The present disclosure relates to semiconductor devices, in particular to semiconductor devices integrating resistors and high electron mobility transistors and methods for manufacturing the same.

In AC/DC power conversion circuits, resistors are usually used as voltage dividers. Currently, most semiconductor components use silicon as the base material and channel, and semiconductor components that generally use silicon usually use polysilicon to make resistors, and place the polysilicon resistors on field oxide (FOX). The voltage that this polysilicon resistor can withstand is limited by the thickness of the field oxide, and when the voltage at both ends of the resistor increases, the polysilicon depletion phenomenon will become more serious, causing the resistance value to be nonlinear when the voltage changes.

With the development of high-voltage and high-power devices, semiconductor devices using gallium nitride (GaN), such as high electron mobility transistors (HEMT), have gradually replaced semiconductor devices using silicon due to their low on-resistance and high voltage, high frequency and high current resistance. However, in AC/DC power conversion circuits and other digital logic circuits, there are still many problems to be overcome in integrating resistors with high electron mobility transistors.

In view of this, the present disclosure proposes a semiconductor device integrating a resistor and a high electron mobility transistor and a manufacturing method thereof, which utilizes a compound semiconductor material layer forming a capping layer of a high electron mobility transistor, and can form a resistor in a passive element region without additional processes and masks, thereby completing a semiconductor device integrating a resistor and a high electron mobility transistor.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a compound semiconductor channel layer, a compound semiconductor barrier layer, a first compound semiconductor capping layer, a gate electrode, a source electrode, a drain electrode, and a second compound semiconductor capping layer. The substrate has an active element region and a passive element region, a compound semiconductor channel layer, a compound semiconductor barrier layer and a first compound semiconductor cap layer are sequentially arranged on the substrate and located in the active element region, a gate electrode is arranged on the first compound semiconductor cap layer, a source electrode and a drain electrode are arranged on the compound semiconductor barrier layer and are respectively located on both sides of the gate electrode to form a high electron mobility transistor, and a second compound semiconductor cap layer is arranged on the substrate and located in the passive element region to form a resistor.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps: providing a substrate having an active device region and a passive device region; sequentially forming a compound semiconductor channel layer, a compound semiconductor barrier layer, and a compound semiconductor cap layer in the active device region and the passive device region on the substrate; forming an isolation region in the compound semiconductor channel layer in the passive device region; patterning the compound semiconductor Semiconductor capping layer, to form a first compound semiconductor capping layer in the active element region, and to form a second compound semiconductor capping layer in the passive element region, wherein the second compound semiconductor capping layer constitutes a resistor; a gate electrode is formed on the first compound semiconductor capping layer; and a source electrode and a drain electrode are formed on the compound semiconductor barrier layer, respectively located on both sides of the gate electrode, to constitute a high electron mobility transistor.

In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the help of the attached drawings.

100:Semiconductor devices

100A: Active component area

100B: Passive component area

101: Base

102: Seed layer

103: Buffer layer

104: High resistance layer

105: Epitaxial stacking

106: Compound semiconductor channel layer

107: Shallow trench isolation area

108: Compound semiconductor barrier layer

109: Isolation area

110-1: The first compound semiconductor capping layer

110-2: Second compound semiconductor capping layer

110-2A1, 110-2A2: Long strip

110-2B: Continuous curved shape

110-2C: spiral

112: Gate electrode

113: Patterned conductive layer

113-1: The first part of the patterned conductive layer

113-2: The second part of the patterned conductive layer

114: Source electrode

116: Drain electrode

118: Cut-off area

120: Contact

120-1: First contact

120-2: Second contact

130: Conductor layer

132: Source contact

133: Drain contact

134: Interlayer dielectric layer

140: Depression

HEMT: High Electron Mobility Transistor

R: Resistor

2DEG: Two-dimensional electron gas region

L1, L2: length

W1, W2: Width

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to simultaneously when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail, and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

Figure 1 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view of a semiconductor device along the cross-sectional line A-A’ of FIG. 1 according to an embodiment of the present disclosure.

FIG. 3 is a schematic cross-sectional view of a resistor of a semiconductor device along the cross-sectional cut line B-B' of FIG. 1 according to an embodiment of the present disclosure.

FIG. 4 is a schematic cross-sectional view of a semiconductor device along the cross-sectional cut line C-C' of FIG. 1 according to an embodiment of the present disclosure.

FIG. 5 is a schematic cross-sectional view of a semiconductor device along the cross-sectional cut line C-C' of FIG. 1 according to another embodiment of the present disclosure.

FIG. 6 is a schematic cross-sectional view of a semiconductor device along the cross-sectional cut line C-C' of FIG. 1 according to yet another embodiment of the present disclosure.

FIG. 7 is a schematic cross-sectional view of a semiconductor device along the cross-sectional cut line C-C' of FIG. 1 according to another embodiment of the present disclosure.

Semiconductor devices

FIG. 8 is a schematic top view of a resistor of a semiconductor device according to an embodiment of the present disclosure.

FIG. 9 is a schematic top view of a resistor of a semiconductor device according to other embodiments of the present disclosure.

FIG. 10 is a graph showing the current versus voltage of a resistor in a semiconductor device according to some embodiments of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of semiconductor devices during use and operation. With the different orientations of the semiconductor device (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupling", "coupling", and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

In the present disclosure, "compound semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element. The group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Furthermore, the "compound semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), their analogs or combinations of the above compounds, but not limited thereto. In addition, depending on the needs, the compound semiconductor may also include dopants to be a compound semiconductor with a specific conductivity type, such as an n-type or p-type compound semiconductor. In the following text, compound semiconductors may also be referred to as III-V semiconductors.

Although the invention disclosed herein is described below by means of specific embodiments, the inventive principle disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a semiconductor device integrating a resistor and a high electron mobility transistor and a manufacturing method thereof. The semiconductor device utilizes the high resistance characteristics of a compound semiconductor material layer, such as a gallium nitride (GaN) layer, which forms a cap layer of a high electron mobility transistor to form a resistor in a passive device region. The compound semiconductor cap layer of a high electron mobility transistor can be formed in an active device region by epitaxial growth and patterning processes without the need for additional process steps and masks, and a resistor composed of the compound semiconductor cap layer can be formed in a passive device region.

In addition, the resistor of the embodiment disclosed in the present invention can obtain resistors with different resistance values by adjusting the aspect ratio or winding shape of the compound semiconductor cap layer in the passive device region, and the resistor can be connected in parallel and/or in series with a high electron mobility transistor and/or other components, such as a Zener diode, to form a semiconductor device. Compared with the semiconductor device using a conventional polysilicon resistor, the manufacture of the resistor of the semiconductor device disclosed in the present invention can be compatible with the process of the high electron mobility transistor, thereby saving process steps and manufacturing costs. At the same time, since the resistor located in the passive device region of the present disclosure is formed by using the material of the compound semiconductor cap layer, its resistance value is stable and easy to control, and will not be affected by the concentration of the two-dimensional electron gas (2DEG) in the channel layer of the high electron mobility transistor, and is suitable for application in high voltage and high power AC/DC power conversion circuits and other digital logic circuits.

FIG. 1 is a schematic top view of a semiconductor device 100 integrating a resistor R and a high electron mobility transistor HEMT according to an embodiment of the present disclosure. A substrate 101 of the semiconductor device 100 may include an active component region 100A and a passive component region 100B, wherein the high electron mobility transistor HEMT is located in the active component region 100A, and the resistor R is located in the passive component region 100B. High electron mobility transistor of semiconductor device 100 The HEMT includes a compound semiconductor channel layer (hereinafter referred to as the channel layer) 106 and a compound semiconductor barrier layer (hereinafter referred to as the barrier layer) 108 disposed on a substrate 101, a first compound semiconductor cap layer (hereinafter referred to as the first cap layer) 110-1 and a gate electrode 112 disposed on the barrier layer 108, and a source electrode 114 and a drain electrode 116 are also disposed on the barrier layer 108 and are located on both sides of the gate electrode 112, respectively. As shown in FIG. 1 , the long axes of the first cap layer 110-1, the gate electrode 112, the source electrode 114, and the drain electrode 116 all extend along a first direction (e.g., X direction) and are arranged along a second direction (e.g., Y direction). In one embodiment, the layout of the high electron mobility transistor HEMT is that two gate electrodes 112 are respectively located at the upper and lower sides of the source electrode 114, the drain electrode 116 is a common drain, and the distance between the drain electrode 116 and the gate electrode 112 is greater than the distance between the source electrode 114 and the gate electrode 112. In addition, a source contact 132 is provided on the source electrode 114, and a drain contact 133 is provided on the drain electrode 116.

According to the embodiment of the present disclosure, the second compound semiconductor capping layer (hereinafter referred to as the second capping layer) 110-2 is disposed on the substrate 101 and located in the passive device region 100B to form a resistor R. The long axis of the second capping layer 110-2 extends along the second direction (e.g., the Y direction), that is, the extension direction of the second capping layer 110-2 is different from the extension direction of the first capping layer 110-1. In some embodiments, the compound semiconductor channel layer 106 and the compound semiconductor barrier layer 108 of the semiconductor device 100 may extend continuously from the active device region 100A to the passive device region 100B, and the semiconductor device 100 further includes an isolation region 109 disposed in the compound semiconductor channel layer 106 of the passive device region 100B, and a second cap layer 110-2 is disposed on the compound semiconductor barrier layer 108 of the passive device region 100B. In addition, the semiconductor device 100 further includes a patterned conductive layer 113 disposed directly above the second cap layer 110-2, and the patterned conductive layer 113 and the gate electrode 112 may be formed by patterning the same conductive material layer. The semiconductor device 100 further includes a plurality of contacts, such as a first contact 120-1 and a second contact 120-2, which are respectively disposed directly above the first portion 113-1 and the second portion 113-2 of the patterned conductive layer. In some embodiments, the first contact 120-1 is electrically connected to the second cap layer 110-2, and is electrically connected to the source electrode 114 via the wiring layer 130 and the source contact 132. The second contact 120-2 is also electrically connected to the second cap layer 110-2, and is electrically connected to the drain electrode 116 via another wiring layer 130 and the drain contact 133, so that the resistor R is connected in parallel with the high electron mobility transistor HEMT. In other embodiments, the semiconductor device 100 further includes other contacts disposed directly above other portions of the patterned conductive layer, and through other conductive layers, the resistor R is electrically connected to other components, such as other high electron mobility transistors and/or Zener diodes in series and/or in parallel.

FIG. 2 is a schematic cross-sectional view of a semiconductor device 100 along the cross-sectional cut line A-A' of FIG. 1 according to an embodiment of the present disclosure. In some embodiments, the semiconductor device 100 may include an epitaxial stack 105 disposed on a substrate 101, and the epitaxial stack 105 is continuously formed in an active device region 100A and a passive device region 100B. The material of the substrate 101 may include ceramic, silicon carbide (SiC), aluminum nitride (AlN), sapphire or silicon. In addition, the substrate 101 can be a semiconductor on insulator (SOI) substrate covered with an insulating layer, or the substrate 101 can be provided by a composite substrate (also known as a QST substrate) in which a core substrate is wrapped by a composite material layer, wherein the core substrate includes ceramic, silicon carbide, aluminum nitride, sapphire or silicon, and the composite material layer includes an insulating material layer and a semiconductor material layer, wherein the insulating material layer can be a single layer or multiple layers of silicon oxide, silicon nitride or silicon oxynitride, and the semiconductor material layer can be silicon or polycrystalline silicon, and the composite material layer located on the back side of the core substrate will be removed through a thinning process, such as through a grinding or etching process, so that the back side of the core substrate is exposed. In some embodiments, the epitaxial stack 105 may include a nucleation layer 102, a buffer layer 103, and a high resistance layer (or electrical isolation layer) 104 stacked in sequence from bottom to top. In some embodiments, the nucleation layer 102 is, for example, an aluminum nitride (AlN) layer, the buffer layer 103 may be a superlattice (SL) structure, for example, including a plurality of layers of alternately stacked aluminum gallium nitride (AlGaN) layers and aluminum nitride (AlN) layers, and the high resistance layer 104 is, for example, a carbon-doped gallium nitride (c-GaN) layer, but is not limited thereto.

In addition, as shown in FIG. 2 , the high electron mobility transistor HEMT of the semiconductor device 100 includes a channel layer 106 disposed on the high resistance layer 104, a barrier layer 108 stacked on the channel layer 106, a first cap layer 110-1 disposed on the barrier layer 108, a gate electrode 112 disposed on the first cap layer 110-1, a source electrode 114 and a drain electrode 116 disposed on the barrier layer 108, and located on both sides of the gate electrode 112, respectively. Since there is a discontinuous energy gap between the channel layer 106 and the barrier layer 108, by stacking the channel layer 106 and the barrier layer 108 on each other, electrons are gathered at the heterojunction between the channel layer 106 and the barrier layer 108 due to the piezoelectric effect, thereby generating a thin layer with high electron mobility, that is, a two-dimensional electron gas region 2DEG in the channel layer 106. In addition, as shown in FIG. 2, for an enhancement-mode (E-mode) (or normally off) high electron mobility transistor, when no positive voltage is applied to the gate electrode 112, the region covered by the first cap layer 110-1 will not form a two-dimensional electron gas and can be regarded as a 2DEG cutoff region. At this time, there will be no conduction between the source electrode 114 and the drain electrode 116.

In some embodiments, the channel layer 106 is, for example, an undoped gallium nitride (u-GaN) layer, the barrier layer 108 is a compound semiconductor layer having a larger energy gap than the channel layer 106, such as an aluminum gallium nitride (AlGaN) layer, and the first cap layer 110-1 is, for example, a p-type gallium nitride (p-GaN) layer, but is not limited thereto. The composition and structural configuration of the above-mentioned compound semiconductor layers of the high electron mobility transistor structure HEMT can be determined according to the requirements of various semiconductor devices. In addition, the materials of the gate electrode 112, the source electrode 114, and the drain electrode 116 can include metals, alloys, metal nitrides, or semiconductor materials (such as polysilicon). In some embodiments, the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), or other suitable conductive materials, or a combination thereof. In addition, the gate electrode 112 may form a Schottky contact with the first cap layer 110-1, and the source electrode 114 and the drain electrode 116 may form an ohmic contact with the barrier layer 108 and the channel layer 106 therebelow. In addition, as shown in FIG. 2, the source electrode 114 and the drain electrode 116 can be electrically connected to different wire layers 130 via source contacts 132 and drain contacts 133, respectively. The source contacts 132 and drain contacts 133 are formed in the interlayer dielectric layer 134, and the wire layer 130 is formed on the interlayer dielectric layer 134. The source contacts 132, the drain contacts 133 and the wire layer 130 are formed of conductive materials, such as tungsten (W), copper (Cu), aluminum (Al) and other suitable conductive materials.

As shown in FIG. 2, in one embodiment, the channel layer 106 and the barrier layer 108 may extend continuously from the active device region 100A to the passive device region 100B, and the isolation region 109 is disposed in the channel layer 106 of the passive device region 100B, so that the passive device region 100B does not generate a two-dimensional electron gas (2DEG). The second cap layer 110-2 constituting the resistor R is disposed on the barrier layer 108, the first portion 113-1 of the patterned conductive layer 113 is disposed on the second cap layer 110-2, and the first contact 120-1 is disposed directly above the first portion 113-1 of the patterned conductive layer. In one embodiment, the conductive layer 130 continuously extends from the passive device region 100B to the active device region 100A, and the second cap layer 110-2 is electrically connected to the source electrode 114 via the first portion 113-1 of the patterned conductive layer, the first contact 120-1, the conductive layer 130, and the source contact 132. In another embodiment, the conductive layer 130 on the first contact 120-1 and the conductive layer 130 on the source contact 132 may be separate conductive layers 130, and the separate conductive layers 130 are electrically connected to each other via another conductive layer above the conductive layer 130 to complete the electrical connection between the second cap layer 110-2 and the source electrode 114. In addition, in one embodiment, the patterned conductive layer 113 on the second cap layer 110-2 and the gate electrode 112 of the active device region 100A can be formed by patterning the same conductive material layer, and a Schottky contact can be generated between the patterned conductive layer 113 and the second cap layer 110-2. In another embodiment, an ohmic contact can be generated between the patterned conductive layer 113 and the second cap layer 110-2 by selecting the material of the patterned conductive layer 113. In some embodiments, a bias can be applied to the patterned conductive layer 113 to adjust the electrical properties of the resistor R of the passive device region 100B. Among them, the resistance value of the Schottky contact under a small bias voltage is higher than the resistance value under a large bias voltage, but the bias range of the small bias voltage is very small, such as 0V to 25V. Therefore, the electrical adjustment of the resistor R is mainly achieved by changing the layout of the second cap layer 110-2 or changing the doping concentration or doping type of the second cap layer 110-2 under the premise that there is no 2DEG below.

According to some embodiments of the present disclosure, an epitaxial stack 105 can be formed on a substrate 101 through an epitaxial growth process, and a compound semiconductor channel layer 106, a compound semiconductor barrier layer 108 and a compound semiconductor capping layer are sequentially deposited on the epitaxial stack 105 in the active device region 100A and the passive device region 100B. In one embodiment, before the compound semiconductor barrier layer 108 and the compound semiconductor capping layer are deposited, an isolation region 109 is formed in the compound semiconductor channel layer 106 of the passive device region 100B. Then, the compound semiconductor capping layers located in the active device region 100A and the passive device region 100B are patterned simultaneously through the same patterning process (such as photolithography and etching process) to form a first capping layer 110-1 in the active device region 100A and a second capping layer 110-2 in the passive device region 100B. In some embodiments of the present disclosure, the material composition of the first cap layer 110-1 and the second cap layer 110-2 may be the same, for example, both are formed of p-type gallium nitride (p-GaN), and the p-type doping concentration of the first cap layer 110-1 and the second cap layer 110-2 is the same, so the first cap layer 110-1 and the second cap layer 110-2 can be formed simultaneously through the same epitaxial growth process and the same patterning process, and during the epitaxial growth process, p-type doping with the same doping concentration can be added to the active device region 100A and the passive device region 100B.

In addition, in other embodiments, the material compositions of the first cap layer 110-1 and the second cap layer 110-2 may be different. For example, the first cap layer 110-1 may be formed of p-type gallium nitride (p-GaN), and the second cap layer 110-2 may be formed of gallium nitride, n-type gallium nitride or p-type gallium nitride, wherein the doping concentration of the p-type dopant in the second cap layer 110-2 may be different from the doping concentration of the p-type dopant in the first cap layer 110-1. In these embodiments, the first capping layer 110-1 and the second capping layer 110-2 can be deposited by the same epitaxial growth process, and during the epitaxial growth process, p-type doping with different doping concentrations can be added to the active device region 100A and the passive device region 100B, or different dopings, such as p-type and n-type doping, can be added, and then the first capping layer 110-1 and the second capping layer 110-2 can be formed by the same patterning process.

FIG. 3 is a schematic cross-sectional view of a resistor R of a semiconductor device 100 along the cross-sectional cut line B-B' of FIG. 1 according to an embodiment of the present disclosure. A gate electrode 112, a first portion 113-1 of a patterned conductive layer, another gate electrode 112, a second portion 113-1 of a patterned conductive layer are sequentially arranged on a second cap layer 110-2 of the resistor R along the Y axis. The first portion 113-2 of the patterned conductive layer is provided with a first contact 120-1 directly above the first portion 113-1 of the patterned conductive layer, and the second contact 120-2 is provided directly above the second portion 113-2 of the patterned conductive layer. The first contact 120-1 and the second contact 120-2 are respectively electrically connected to the wire layers 130 separated from each other through the interlayer dielectric layer 134. In this embodiment, the second cap layer 110-2 as a resistor R can be electrically coupled to other components, such as high electron mobility transistors HEMTs, Zener diodes, and/or other components in AC/DC power conversion circuits and other digital logic circuits through these contacts and multiple wire layers. In addition, since the passive device region 100B does not form a two-dimensional electron gas and can be regarded as a 2DEG cutoff region, the current from the wiring layer 130 can enter the second cap layer 110-2 through the second contact 120-2, transmit in the second cap layer 110-2 and generate the required voltage drop, and then enter the wiring layer 130 through the first contact 120-1.

FIG. 4 is a schematic cross-sectional view of the semiconductor device 100 along the cross-sectional cut line C-C' of FIG. 1 according to an embodiment of the present disclosure. The cross-sectional cut line C-C' passes through the second cap layer 110-2 of the passive device region 100B, and passes through the channel layer 106 and the barrier layer 108 of the active device region 100A, but does not pass through the source, gate and drain of the active device region 100A, so as to explain the structural difference between the passive device region 100B and the active device region 100A in the channel layer 106 and the barrier layer 108. As shown in FIG. 4, in one embodiment, an isolation region 109 is provided in the channel layer 106 of the passive device region 100B, so that the passive device region 100B does not generate a two-dimensional electron gas 2DEG. In one embodiment, before forming the barrier layer 108, inert ions, such as nitrogen, oxygen or a combination thereof, may be implanted into the channel layer 106 through an ion implantation process to destroy the lattice structure of the channel layer 106 and generate a high resistance region, thereby forming an isolation region 109 (also referred to as an inert ion implantation region), wherein the bottom surface of the isolation region 109 may be higher than the bottom surface of the channel layer 106, or flush with the bottom surface of the channel layer 106, and the bottom surface height of the isolation region 109 is determined by the energy of the ion implantation process. In this embodiment, the second capping layer 110-2 of the passive device region 100B is disposed on the barrier layer 108.

FIG. 5 is a schematic cross-sectional view of the semiconductor device 100 along the cross-sectional cut line C-C' of FIG. 1 according to another embodiment of the present disclosure. In this embodiment, the barrier layer 108 and the entire channel layer 106 of the passive device region 100B are removed by an etching process to form a recess 140. The recess 140 prevents the passive device region 100B from generating a two-dimensional electron gas 2DEG. As shown in FIG. 5, in one embodiment, the bottom surface of the recess 140 can be flush with the bottom surface of the channel layer 106, and the depth of the recess 140 is determined by the parameters of the etching process. In this embodiment, the second capping layer 110-2 of the passive element region 100B is disposed in the recess 140 and is located on the bottom surface of the recess 140, that is, the second capping layer 110-2 as the resistor R can be directly formed on the epitaxial stack 105, and the bottom surface of the second capping layer 110-2 contacts the top surface of the epitaxial stack 105.

FIG. 6 is a schematic cross-sectional view of the semiconductor device 100 along the cross-sectional cut line C-C' of FIG. 1 according to another embodiment of the present disclosure. In this embodiment, the barrier layer 108 and part of the channel layer 106 of the passive device region 100B are removed by an etching process to form a recess 140. The recess 140 prevents the passive device region 100B from generating a two-dimensional electron gas 2DEG. As shown in FIG. 6, in one embodiment, the bottom surface of the recess 140 can be higher than the bottom surface of the channel layer 106, and the depth of the recess 140 is determined by the parameters of the etching process. In this embodiment, the second cap layer 110-2 of the passive device region 100B is disposed in the recess 140 and is located on the bottom surface of the recess 140.

FIG. 7 is a schematic cross-sectional view of the semiconductor device 100 along the cross-sectional cut line C-C' of FIG. 1 according to yet another embodiment of the present disclosure. In this embodiment, a shallow trench isolation (STI) 107 is provided in the barrier layer 108 and the channel layer 106 of the passive device region 100B so that the passive device region 100B does not generate a two-dimensional electron gas 2DEG. In this embodiment, a trench is formed in the barrier layer 108 and the channel layer 106 of the passive device region 100B by an etching process. The bottom surface of the trench can be higher than the bottom surface of the channel layer 106, or flush with the bottom surface of the channel layer 106. The height of the bottom surface of the trench is determined by the etching process for forming the trench. Then, a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials, is filled in the trench to form a shallow trench isolation region 107. In this embodiment, the second capping layer 110-2 of the passive element region 100B serving as a resistor R can be formed on the shallow trench isolation region 107, for example, the bottom surface of the second capping layer 110-2 can contact the top surface of the shallow trench isolation region 107, so that the resistance value of the resistor R of the semiconductor device 100 is increased.

In some embodiments of the present disclosure, the isolation region 109 (also referred to as an ion implantation region) or the shallow trench isolation region 107 located directly below the second cap layer 110-2 has a higher resistance value than the channel layer 106, so that the isolation region 109 or the shallow trench isolation region 107 helps to increase the resistance value of the resistor R.

FIG. 8 is a schematic top view of a resistor R according to an embodiment of the present disclosure. In this embodiment, the top view shape of the resistor R of the semiconductor device 100 can be a plurality of strips 110-2A1 and 110-2A2. The strip-shaped resistor R can obtain different resistance values by adjusting the aspect ratio. For example, the length L1 of the strip 110-2A1 is substantially equal to the length L2 of the strip 110-2A2. 0-2A2 has a length L2, but the width W1 of the strip 110-2A1 is smaller than the width W2 of the strip 110-2A2, so that the aspect ratio L1/W1 of the strip 110-2A1 is greater than the aspect ratio L2/W2 of the strip 110-2A2, and the resistance value of the resistor of the strip 110-2A1 is greater than the resistance value of the resistor of the strip 110-2A2. In addition, referring to FIG. 1 and FIG. 8, in some embodiments, in addition to the second capping layer 110-2, a third compound semiconductor capping layer (hereinafter referred to as the third capping layer) may be formed on the substrate 101 of the passive element region 100B to form another resistor, wherein the top view shape of the second capping layer 110-2 is, for example, a strip 110-2A1 as shown in FIG. 8, and the top view shape of the third capping layer is, for example, a strip 110-2A2 as shown in FIG. 8, so that the third capping layer and the second capping layer 110-2 have different resistance values.

In some embodiments, the third capping layer and the second capping layer 110-2 in the passive device region 100B and the first capping layer 110-1 in the active device region 100A may have the same material composition, and these capping layers may be formed simultaneously through the same epitaxial growth process and the same patterning process. In addition, as shown in FIG. 8 , multiple contacts 120 can be formed directly above the third cover layer of the strip 110-2A2 and the second cover layer 110-2 of the strip 110-2A1, and the third cover layer of the strip 110-2A2 is electrically connected to the second cover layer 110-2 of the strip 110-2A1 via the wire layer 130 and the contacts 120, so that multiple resistors located in the passive element region 100B are connected in series or in parallel to achieve the required resistance value of the resistor R of the semiconductor device 100.

FIG. 9 is a schematic top view of a resistor R according to some embodiments of the present disclosure. As shown in FIG. 9 , the top view shape of the resistor R of the semiconductor device 100 may be a continuous bend shape 110-2B or a spiral shape 110-2C. Resistors of these shapes may replace the long strip-shaped resistor R in FIG. 1 , and the resistance value of the resistor R may be adjusted by the winding method and length of the continuous bend shape 110-2B or the spiral shape 110-2C to obtain resistors with different resistance values. For example, the longer the winding length, the higher the resistance value of the resistor can be obtained, and the more bends the winding has, the higher the resistance value of the resistor can be obtained in a smaller area. In some embodiments, the material composition of the resistor of the continuous bend shape 110-2B or the spiral shape 110-2C is the same as the material composition of the first cap layer 110-1 in FIG. 1, and can be formed simultaneously through the same epitaxial growth process and the same patterning process. In addition, multiple contacts of the resistor R can be formed directly above the resistor of the continuous bend shape 110-2B or the spiral shape 110-2C, and through multiple contacts and multiple wire layers, the resistor of the continuous bend shape 110-2B or the spiral shape 110-2C can be electrically connected to other components, such as high electron mobility transistors HEMT, Zener diodes and/or other components.

FIG. 10 is a graph of the current Id versus the voltage Vd of the resistor R of the semiconductor device 100 according to some embodiments of the present disclosure, wherein the unit of the current Id is ampere (A), and the unit of the voltage Vd is volt (V). The top view shape of the resistor R of embodiments 1-1, 1-2, and 1-3 is a long strip, and its length is approximately 23.25 micrometers (μm), and its width is approximately 6 micrometers (μm). The resistors R of the three embodiments 1-1, 1-2 and 1-3 are manufactured on the same wafer at the same time and have the same size. As shown in FIG. 10, the characteristic curves of the current Id corresponding to the voltage Vd of the resistors of the embodiments 1-1, 1-2 and 1-3 are all linear, and the resistance values of the three embodiments 1-1, 1-2 and 1-3 are substantially the same. At high voltages (e.g., greater than 75V), the resistance values of the three embodiments 1-1, 1-2 and 1-3 are even closer, which indicates that the resistance value of the resistor R of the semiconductor device 100 manufactured according to the embodiments of the present disclosure is stable, and the resistance value of the resistor is linear when the voltage changes.

According to the embodiments disclosed herein, the high resistance characteristics of the compound semiconductor material forming the capping layer of the high electron mobility transistor can be utilized to form a resistor in the passive element region, and a semiconductor device integrating a resistor and a high electron mobility transistor can be completed without the need for additional processes and masks. Compared to the known semiconductor devices using polysilicon resistors, the manufacture of the resistor of the semiconductor device disclosed herein can be compatible with the process of the high electron mobility transistor, thereby achieving the benefits of saving process steps and manufacturing costs.

In addition, according to the embodiments disclosed herein, resistors with different resistance values can be obtained by adjusting the aspect ratio or the winding shape of the compound semiconductor cap layer in the passive device region, and the resistance value of the resistor manufactured by the embodiments disclosed herein can be controlled by the high resistance characteristics of the material of the compound semiconductor cap layer. Compared with the conventional polycrystalline silicon resistor, it is less affected by the intensity of the two-dimensional electron gas (2DEG) in the channel layer of the high electron mobility transistor. Its resistance value is stable and easy to control, and the resistance value is linear when the voltage changes, which is beneficial to the application of high voltage and high power components. In addition, the resistor of the semiconductor device disclosed herein can be connected in series and/or in parallel with a high electron mobility transistor, a Zener diode and/or other components, and is suitable for application in high voltage and high power AC/DC power conversion circuits and other digital logic circuits.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:Semiconductor devices

100A: Active component area

100B: Passive component area

101: Base

106: Compound semiconductor channel layer

108: Compound semiconductor barrier layer

109: Isolation area

110-1: The first compound semiconductor capping layer

110-2: Second compound semiconductor capping layer

112: Gate electrode

113: Patterned conductive layer

113-1: The first part of the patterned conductive layer

113-2: The second part of the patterned conductive layer

114: Source electrode

116: Drain electrode

120-1: First contact

120-2: Second contact

130: Conductor layer

132: Source contact

133: Drain contact

HEMT: High Electron Mobility Transistor

R: Resistor

Claims (20)

A semiconductor device includes: a substrate having an active device region and a passive device region; a compound semiconductor channel layer, a compound semiconductor barrier layer, and a first compound semiconductor cap layer, which are sequentially arranged on the substrate and located in the active device region; a gate electrode, which is arranged on the first compound semiconductor cap layer; a source electrode and a drain electrode, which are arranged on the compound semiconductor barrier layer and are respectively located on both sides of the gate electrode to form a high electron mobility transistor; and a second compound semiconductor cap layer, which is arranged on the substrate and located in the passive device region to form a resistor. A semiconductor device as described in claim 1, wherein the first compound semiconductor capping layer extends along a first direction, the second compound semiconductor capping layer extends along a second direction, and the first direction and the second direction are different. A semiconductor device as described in claim 1, wherein the composition of the first compound semiconductor cap layer includes p-type gallium nitride (GaN), and the composition of the second compound semiconductor cap layer includes gallium nitride, p-type gallium nitride or n-type gallium nitride. A semiconductor device as described in claim 1, wherein the first compound semiconductor cap layer and the second compound semiconductor cap layer include p-type gallium nitride (GaN) with different doping concentrations. The semiconductor device as described in claim 1 further comprises: a patterned conductive layer disposed directly above the second compound semiconductor cap layer; a first contact disposed directly above a first portion of the patterned conductive layer and electrically connected to the second compound semiconductor cap layer and the source electrode; and a second contact disposed directly above a second portion of the patterned conductive layer and electrically connected to the second compound semiconductor cap layer and the drain electrode. A semiconductor device as described in claim 1, wherein the top view shape of the second compound semiconductor cap layer includes a strip, a continuous bend or a spiral. A semiconductor device as described in claim 1, wherein the compound semiconductor channel layer and the compound semiconductor barrier layer extend continuously from the active device region to the passive device region, and the semiconductor device further comprises an isolation region disposed in the compound semiconductor channel layer, directly below the second compound semiconductor cap layer, and the bottom surface of the isolation region is higher than the bottom surface of the compound semiconductor channel layer, or is flush with the bottom surface of the compound semiconductor channel layer. A semiconductor device as described in claim 7, wherein the isolation region includes an inert ion implantation region or a shallow trench isolation region. A semiconductor device as described in claim 1, wherein the compound semiconductor channel layer and the compound semiconductor barrier layer have a recess in the passive device region, and the second compound semiconductor cap layer is disposed in the recess. A semiconductor device as described in claim 9, wherein the bottom surface of the recess is higher than the bottom surface of the compound semiconductor channel layer, or is flush with the bottom surface of the compound semiconductor channel layer. The semiconductor device as described in claim 1 further includes an epitaxial stack disposed between the substrate and the compound semiconductor channel layer and located in the active device region and the passive device region. A semiconductor device as described in claim 11, wherein the bottom surface of the second compound semiconductor cap layer contacts the top surface of the epitaxial stack. The semiconductor device as described in claim 1 further includes a third compound semiconductor cap layer disposed on the substrate and located in the passive device region, wherein the second compound semiconductor cap layer and the third compound semiconductor cap layer have different resistance values, and the third compound semiconductor cap layer is electrically connected to the second compound semiconductor cap layer. A semiconductor device as described in claim 13, wherein the first compound semiconductor cap layer, the second compound semiconductor cap layer, and the third compound semiconductor cap layer have the same composition. A method for manufacturing a semiconductor device includes: providing a substrate having an active device region and a passive device region; sequentially forming a compound semiconductor channel layer, a compound semiconductor barrier layer, and a compound semiconductor cap layer in the active device region and the passive device region on the substrate; forming an isolation region in the compound semiconductor channel layer in the passive device region; patterning the compound semiconductor cap layer to form an isolation region in the active device region; A first compound semiconductor capping layer is formed in the active element region, and a second compound semiconductor capping layer is formed in the passive element region, wherein the second compound semiconductor capping layer constitutes a resistor; a gate electrode is formed on the first compound semiconductor capping layer; and a source electrode and a drain electrode are formed on the compound semiconductor barrier layer, respectively located on both sides of the gate electrode, to constitute a high electron mobility transistor. The method for manufacturing a semiconductor device as described in claim 15 further includes: forming a patterned conductive layer directly above the second compound semiconductor cap layer; and forming a first contact and a second contact respectively directly above a first portion and a second portion of the patterned conductive layer, and the first contact is electrically connected to the second compound semiconductor cap layer and the source electrode, and the second contact is electrically connected to the second compound semiconductor cap layer and the drain electrode, wherein the patterned conductive layer and the gate electrode are formed by patterning the same conductive material layer. A method for manufacturing a semiconductor device as described in claim 15, wherein forming the isolation region includes implanting inert ions in the compound semiconductor channel layer of the passive device region to form an inert ion implantation region located directly below the second compound semiconductor cap layer. The method for manufacturing a semiconductor device as described in claim 15, wherein forming the isolation region includes etching and removing the compound semiconductor channel layer and the compound semiconductor barrier layer in the passive device region to form a recess, and the second compound semiconductor cap layer is formed in the recess. A method for manufacturing a semiconductor device as described in claim 15, wherein forming the isolation region includes forming a shallow trench isolation region in the compound semiconductor channel layer and the compound semiconductor barrier layer in the passive device region, located directly below the second compound semiconductor cap layer. A method for manufacturing a semiconductor device as described in claim 15, wherein patterning the compound semiconductor capping layer further includes forming a third compound semiconductor capping layer in the passive element region, the second compound semiconductor capping layer and the third compound semiconductor capping layer have different resistance values, and the third compound semiconductor capping layer is electrically connected to the second compound semiconductor capping layer.

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