TWI820979B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a high electron mobility transistor disposed in an annular active element region, and a resistor disposed in a passive element region surrounded by the annular active element region. The high electron mobility transistor includes a first portion of a compound semiconductor barrier layer stacked on a first portion of a compound semiconductor channel layer, and a source electrode, a gate electrode, and a drain electrode disposed on the first portion of the compound semiconductor barrier layer. The resistor includes a second portion of the compound semiconductor barrier layer stacked on a second portion of the compound semiconductor channel layer, and an input terminal electrode disposed on the second portion of the compound semiconductor barrier layer and located at the center of the passive element region.

Description

Semiconductor device

The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices integrating high electron mobility transistors and resistors.

In semiconductor technology, III-V compound semiconductors can be used to form various integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors or high electron mobility transistors (HEMT). HEMT is a transistor with a two-dimensional electron gas (2DEG), and its 2DEG is adjacent to the joint surface between two materials with different energy gaps (that is, a heterogeneous joint surface). Since HEMT does not use a doped region as the carrier channel of the transistor, but uses 2DEG as the carrier channel of the transistor, compared with the conventional metal oxide semi-field effect transistor (MOSFET), HEMT has a variety of attractive features. Properties such as: high electron mobility, ability to transmit signals at high frequencies, high breakdown voltage, and low on-resistance.

In recent years, HEMTs have been used in many applications due to their high breakdown voltage and low on-resistance, such as battery monitoring and management systems, three-phase motor control circuits, etc. In these applications, accurate sensing of the high-voltage side current is required, such as using a current sensing resistor, which is usually a separate component from the HEMT that is electrically connected to the HEMT to form an electronic circuit. However, a separate current-sensing resistor separate from the HEMT would require a larger footprint for the electronic circuit and increase manufacturing costs.

In view of this, the present disclosure proposes a semiconductor device that integrates a resistor in a region where a high electron mobility transistor is formed. Therefore, the resistor electrically connected to the high electron mobility transistor does not occupy additional area and can save The layout area of electronic circuits. In addition, the resistor of the embodiment of the present disclosure is a resistor using two-dimensional electron gas (2DEG). Compared with the silicon-based resistor, the resistor of the embodiment of the present disclosure is more accurate in sensing current, and in Electrically more robust and durable. At the same time, the manufacturing processes of the resistor and the high electron mobility transistor according to the embodiment of the present disclosure can be integrated together, and the manufacturing is relatively simple.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a high electron mobility transistor and a resistor. The high electron mobility transistor is disposed in the annular active element region, and the resistor is disposed in the passive element region surrounded by the annular active element region. The high electron mobility transistor includes a first portion of a compound semiconductor barrier layer stacked on a first portion of a compound semiconductor channel layer, and a source electrode, a gate electrode, and a drain electrode disposed on the compound semiconductor barrier layer. On to the first part. The resistor includes a second portion of the compound semiconductor barrier layer stacked on a second portion of the compound semiconductor channel layer, and an input terminal electrode is disposed on the second portion of the compound semiconductor barrier layer and located in the passive component region. center.

In order to make the features of the present disclosure clear and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

100:Semiconductor device

100A: Ring-shaped active component area

100R: Passive component area

101: Base

103:Buffer layer

105: Compound semiconductor channel layer

105-1: The first part of the compound semiconductor channel

105-2: The second part of the compound semiconductor channel

107: Compound semiconductor barrier layer

107-1: The first part of the compound semiconductor barrier layer

107-2: The second part of the compound semiconductor barrier layer

109:Insulating materials

110: Input terminal electrode

120. D: Drain electrode

130. G: Gate electrode

140. S: Source electrode

150: Conductive ring

160: Spiral conductive material

VH: high voltage terminal voltage

VD: drain voltage

VG: gate voltage

VL: low voltage terminal voltage

R: resistor

HEMT: high electron mobility transistor

In order to make the following easier to understand, the drawings and their detailed text descriptions may be referred to simultaneously when reading this disclosure. Through the specific embodiments in this article and with reference to the corresponding drawings, the present disclosure will be explained in detail. Specific embodiments are used to illustrate the working principles of the specific embodiments of the present disclosure. In addition, features in the drawings may not be drawn to actual scale for the sake of clarity, and therefore the dimensions of some features in some drawings may be intentionally exaggerated or reduced.

FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a circuit diagram of a semiconductor device according to some embodiments of the present disclosure.

FIG. 3 is a schematic cross-sectional view of a semiconductor device along the cross-sectional tangent line A-A' in FIG. 1 according to an embodiment of the present disclosure.

FIG. 4 is a schematic top view of a semiconductor device according to another embodiment of the present disclosure.

FIG. 5 is a schematic cross-sectional view of a semiconductor device along the cross-sectional tangent line B-B' in FIG. 4 according to another embodiment of the present disclosure.

FIG. 6 is a schematic top view of a semiconductor device according to yet another embodiment of the present disclosure.

FIG. 7 is a schematic cross-sectional view of a semiconductor device along the cross-sectional tangent line C-C' in FIG. 6 according to yet another embodiment of the present disclosure.

FIG. 8 is a schematic top view of a semiconductor device according to yet another embodiment of the present disclosure.

FIG. 9 is a schematic cross-sectional view of a semiconductor device along the cross-sectional tangent line D-D' in FIG. 8 according to yet another embodiment of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the disclosure. To simplify explanation, examples of specific components and arrangements are also described in this disclosure. These examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of "the first feature is formed on or above the second feature" may mean "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". "There are other features between the features", so that the first feature and the second feature are not in direct contact. Additionally, various embodiments in the present disclosure may use repeated references Symbols and/or textual annotations. These repeated reference symbols and notations are used to make the description more concise and clear, but are not used to indicate the correlation between different embodiments and/or configurations.

In addition, for the space-related descriptive words mentioned in this disclosure, such as: "under", "low", "lower", "above", "above", "upper", "top" ", "bottom" and similar words are used to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings for the convenience of description. In addition to the orientations shown in the drawings, these spatially related terms are also used to describe possible orientations of the semiconductor device during use and operation. As the semiconductor device is oriented differently (rotated 90 degrees or other orientations), the spatially related description used to describe its orientation should be interpreted in a similar manner.

Although this disclosure uses terms such as first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not themselves imply or represent the element. There is no previous serial number, nor does it represent the order of arrangement of one component with another component, or the order of the manufacturing method. Therefore, a first element, component, region, layer, or block discussed below may also be termed a second element, component, region, layer, or block without departing from the scope of the specific embodiments of the disclosure. Of.

The terms "about" or "substantially" used in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specifically stating "approximately" or "substantially", the meaning of "approximately" or "substantially" may still be implied.

The terms "coupling", "coupling" and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if a first component is described as being coupled to a second component, then It means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

In this disclosure, "compound semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element. Among them, the third group element can be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the fifth group element can be nitrogen (N), phosphorus (P), arsenic (As) or Antimony (Sb). Furthermore, "compound semiconductor" can be a binary compound semiconductor, a ternary compound semiconductor or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), arsenide Gallium (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide ( AlGaAs), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), their analogs or combinations of the above compounds, but are not limited thereto. In addition, depending on the requirements, the compound semiconductor may also include a dopant, which is a compound semiconductor with a specific conductivity type, such as an n-type or p-type compound semiconductor. Hereinafter, compound semiconductors may also be referred to as III-V semiconductors.

Although the invention of the present disclosure is described below through specific embodiments, the inventive principles of the present disclosure can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, specific details will be omitted, and these omitted details fall within the scope of knowledge of those with ordinary skill in the art.

The present disclosure relates to a semiconductor device integrating a high electron mobility transistor and a resistor, which integrates the resistor in a region where the high electron mobility transistor is formed, the resistor is electrically connected to the high electron mobility transistor, and does not Occupying additional area, it can save the layout area of electronic circuits. In addition, the resistor in the embodiment of the present disclosure is a two-dimensional electron gas (2DEG) resistor, which is more accurate in sensing current and is electrically more robust and durable than a silicon-based resistor. At the same time, the processes of the resistor and the high electron mobility transistor according to the embodiment of the present disclosure can be integrated, and there is no need to form an additional photoresist layer to manufacture the resistor. Therefore, the process steps are simple and the manufacturing cost can be reduced.

1 is a schematic top view of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes an annular active device region 100A and a passive device region 100R surrounded by the annular active device region 100A. The semiconductor device 100 A high electron mobility transistor (HEMT) is disposed in the annular active component region 100A, and a resistor of the semiconductor device 100 is disposed in the passive component region 100R. A high electron mobility transistor (HEMT) includes a first portion 107-1 of a compound semiconductor barrier layer stacked on a first portion 105-1 of a compound semiconductor channel layer. As shown in Figure 1, in one embodiment, the first part 107-1 of the compound semiconductor barrier layer and the first part 105-1 of the compound semiconductor channel layer are vertically aligned, and their top view shape is a circular ring. shape, that is, the top view shape of the annular active device region 100A is a circular annular shape. In other embodiments, the top view shape of the annular active component region 100A may be an elliptical annular shape, a rectangular annular shape, a polygonal annular shape, or annular regions of other geometric shapes. In addition, the high electron mobility transistor (HEMT) further includes a source electrode 140, a gate electrode 130 and a drain electrode 120 disposed on the first portion 107-1 of the compound semiconductor barrier layer. As shown in FIG. 1 , in one embodiment, the top view shapes of the source electrode 140 , the gate electrode 130 and the drain electrode 120 are circular annulus shapes that are separated from each other, but are not limited thereto. The top view shape of the pole electrode 130 and the drain electrode 120 can also be an elliptical ring shape, a rectangular ring shape or a polygonal ring shape, which can be adjusted according to the top view shape of the ring-shaped active device region 100A. In addition, the drain electrode 120 is adjacent to the passive component region 100R, the source electrode 140 is far away from the passive component region 100R, and the gate electrode 130 is located between the source electrode 140 and the drain electrode 120 . In some embodiments, the distance between the drain electrode 120 and the gate electrode 130 may be greater than the distance between the source electrode 140 and the gate electrode 130 .

In addition, the resistor of the semiconductor device 100 includes the second portion 107-2 of the compound semiconductor barrier layer stacked on the second portion 105-2 of the compound semiconductor channel layer, and the input terminal electrode 110 is disposed on the compound semiconductor barrier layer. on the second part 107-2 and located in the center of the passive component area 100R. As shown in Figure 1, in one embodiment, the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer are vertically aligned, and their top view shape is from the input terminal to The electrode 110 radiates radially toward the drain electrode 120 , and the gaps between the radials can be filled with insulating material 109 . In some practical In the embodiment, the compound semiconductor channel layer is composed of, for example, gallium nitride (GaN), the compound semiconductor barrier layer is composed of, for example, aluminum gallium nitride (AlGaN), and the second part of the compound semiconductor barrier layer in the passive element region 100R The stacked structure of part 107-2 and the second part 105-2 of the compound semiconductor channel layer can generate two-dimensional electron gas (2DEG), that is, two-dimensional electrons, adjacent to the junction between two materials with different energy gaps. Gas (2DEG) is generated in the second portion 105-2 of the compound semiconductor channel layer and is close to the second portion 107-2 of the compound semiconductor barrier layer. Therefore, the resistor of the semiconductor device 100 can also be called a two-dimensional electron. gas (2DEG) resistor. In this embodiment, the area proportions occupied by the second part 107-2 of the radial compound semiconductor barrier layer and the second part 105-2 of the compound semiconductor channel layer in the passive device region 100R can be adjusted. To change the resistance value of the resistor, when the area ratio occupied by the radial pattern is higher, the resistance value of the resistor is lower.

FIG. 2 is a circuit diagram of a semiconductor device 100 according to some embodiments of the present disclosure. One end of the resistor R in the passive component region 100R of the semiconductor device 100 is electrically coupled to the input terminal electrode 110 to receive the high-voltage terminal voltage VH. , the other end of the resistor R is electrically coupled to the drain electrode D of the high electron mobility transistor HEMT in the ring-shaped active element area 100A, and the high-voltage terminal voltage VH is stepped down through the resistor R to obtain the drain voltage VD is transmitted to the drain electrode D, where the potential of the input terminal electrode 110 is higher than the potential of the drain electrode D. The gate electrode G of the high electron mobility transistor HEMT receives the gate voltage VG, and the source electrode S of the high electron mobility transistor HEMT is electrically coupled to the low voltage terminal voltage VL, such as the ground terminal. According to an embodiment of the present disclosure, the resistor R of the semiconductor device 100 is disposed at the high-voltage end of the circuit and is connected in series with a high electron mobility transistor (HEMT). The resistor R can thereby be used to monitor the high-voltage end current to protect the High electron mobility transistor HEMT.

Figure 3 is a schematic cross-sectional view of the semiconductor device 100 along the cross-sectional tangent line AA' in Figure 1 according to an embodiment of the present disclosure. The semiconductor device 100 includes a substrate 101. In some embodiments, the substrate 101 Materials may include ceramics, silicon carbide (SiC), aluminum nitride (AlN), sapphire, or silicon. When the substrate 101 is made of a material with high hardness, high thermal conductivity and low electrical conductivity, such as a ceramic substrate, it is more suitable for high-voltage semiconductor devices. Among them, the above-mentioned high hardness, high thermal conductivity and low electrical conductivity are compared with single crystal For silicon substrates, high-voltage semiconductor devices refer to semiconductor devices with operating voltages higher than 50V. In some embodiments, the substrate 101 may be a semiconductor on insulator (SOI) substrate. In other embodiments, the substrate 101 may be provided by a composite substrate (also known as a QST substrate) composed of a core substrate wrapped by a composite material layer, where the core substrate includes ceramic, silicon carbide, aluminum nitride, sapphire or silicon, The composite material layer includes an insulating material layer and a semiconductor material layer. The insulating material layer can be a single or multi-layer silicon oxide, silicon nitride or silicon oxynitride. The semiconductor material layer can be silicon or polycrystalline silicon, and is located on the back of the core substrate. The composite material layer is removed through a thinning process, such as grinding or etching, so that the backside of the core substrate is exposed.

In addition, the semiconductor device 100 also includes a buffer layer 103, a compound semiconductor channel layer 105, and a compound semiconductor barrier layer 107 stacked on the substrate 101 from bottom to top. The buffer layer 103 can be used to reduce the amount of water present in the substrate 101 and the compound semiconductor channel layer. The degree of stress or lattice mismatch between 105. In some embodiments, a nucleation layer may be disposed between the buffer layer 103 and the substrate 101 , and a high resistance layer may be disposed between the buffer layer 103 and the compound semiconductor channel layer 105 . (or called electrical isolation layer). The materials of the seed layer, buffer layer 103 and high resistance layer include compound semiconductors. In some embodiments, the seed layer is, for example, an aluminum nitride (AlN) layer, and the buffer layer 103 may be a superlattice (SL) structure. , for example, it includes a plurality of alternately stacked aluminum gallium nitride (AlGaN) layers and aluminum nitride (AlN) layers, and the high resistance layer is, for example, a carbon-doped gallium nitride (c-GaN) layer, but is not limited thereto. In addition, in some embodiments, the compound semiconductor channel layer 105 is, for example, an undoped gallium nitride (u-GaN) layer, and the compound semiconductor barrier layer 107 is a compound semiconductor layer with an energy gap larger than that of the compound semiconductor channel layer 105 , for example Aluminum gallium nitride (AlGaN) layer, but not limited to this. The composition and structural configuration of each compound semiconductor layer of the semiconductor device 100 can be determined according to the requirements of various semiconductor devices.

Still referring to Figure 3, the compound semiconductor channel layer 105 of the semiconductor device 100 includes a first portion 105-1 located in the annular active device region 100A, and a second portion 105-2 located in the passive device region 100R, and a compound semiconductor barrier Layer 107 also includes a first portion 107-1 located in annular active device region 100A, and The second part 107-2 is located in the passive component area 100R. In addition, a source electrode 140, a gate electrode 130 and a drain electrode 120 are provided on the first part 107-1 of the compound semiconductor barrier layer 107 in the annular active device region 100A to form a high electron mobility transistor. . In some embodiments, the high electron mobility transistor (HEMT) is an enhanced mode HEMT, and a compound is disposed between the gate electrode 130 and the first portion 107 - 1 of the compound semiconductor barrier layer 107 Semiconductor capping layer (not shown). In other embodiments, the high electron mobility transistor (HEMT) is a depletion mode HEMT, and the gate electrode 130 may be disposed in the recess of the first portion 107 - 1 of the compound semiconductor barrier layer 107 . In addition, an input terminal electrode 110 is provided on the second part 107-2 of the compound semiconductor barrier layer 107 in the passive component region 100R. The voltage (for example, a high voltage terminal voltage) is received by the input terminal electrode 110, and the compound semiconductor channel layer 105 The stacked structure of the second part 105-2 and the second part 107-2 of the compound semiconductor barrier layer 107 serves as a resistive material. In some embodiments, the input terminal electrode 110 may have the same composition as the source electrode 140 and the drain electrode 120 , such as titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or the aforementioned The source electrode 140 , the drain electrode 120 and the input terminal electrode 110 can be formed simultaneously using the same process steps.

FIG. 4 is a schematic top view of a semiconductor device 100 according to another embodiment of the present disclosure. The difference between the semiconductor device 100 in FIG. 4 and FIG. 1 lies in the compound of the passive component region 100R of the semiconductor device 100 in FIG. 4 The stacked structure of the second part 105-2 of the semiconductor channel layer 105 and the second part 107-2 of the compound semiconductor barrier layer 107 is spiral in plan view, and one end of the spiral is connected to the input terminal electrode 110 , the other end of the spiral is connected to the drain electrode 120 , that is, the spiral is connected from the input terminal electrode 110 to the drain electrode 120 , and the gaps between the spirals can be filled with insulating material 109 . This embodiment also uses the two-dimensional electron gas (2DEG) generated by the stacked structure of the second part 105-2 of the compound semiconductor channel layer and the second part 107-2 of the compound semiconductor barrier layer as a resistor, so it can Called a two-dimensional electron gas (2DEG) resistor. In this embodiment, the resistance value of the resistor can be changed by adjusting the number of spiral turns. When the number of spiral turns is greater, the path of the current from the input terminal electrode 110 to the drain electrode 120 is longer, then The higher the resistance value of the resistor.

FIG. 5 is a schematic cross-sectional view of the semiconductor device 100 along the cross-sectional tangent line BB′ in FIG. 4 according to another embodiment of the present disclosure. In the semiconductor device 100 in FIG. 5 , the passive component region 100R The stacked structure of the second part 105-2 of the compound semiconductor channel layer 105 and the second part 107-2 of the compound semiconductor barrier layer 107 has a spiral shape in plan view, and the gaps between the spiral shapes are filled with insulating material 109. For example, silicon oxide, silicon nitride or silicon oxynitride, but are not limited thereto. In addition, the input terminal electrode 110 is provided on the second portion 107-2 of the compound semiconductor barrier layer 107 in the passive device region 100R. In one embodiment, when viewed from above, the input terminal electrode 110 overlaps with a partial section of one end of the spiral shape and a part of the insulating material 109 .

Figure 6 is a schematic top view of a semiconductor device 100 according to yet another embodiment of the present disclosure. In the semiconductor device 100 of Figure 6 , the second portion 105-2 of the compound semiconductor channel layer in the passive device region 100R The top view shape of the stacked structure of the second part 107-2 of the compound semiconductor barrier layer is a plurality of mutually separated rings. These mutually separated rings are arranged concentrically between the input terminal electrode 110 and the drain electrode. arranged between 120. In addition, the resistor in the passive component region 100R also includes a plurality of conductive rings 150 that are separated from each other, which are disposed on the second part 107-2 of the compound semiconductor barrier layer. When viewed from above, these conductive rings 150 that are separated from each other are between a plurality of mutually separated rings formed by the second part 105-2 of the compound semiconductor channel layer and the second part 107-2 of the compound semiconductor barrier layer, to electrically connect these mutually separated rings in series shape object. Furthermore, these mutually separated conductive rings 150 are laterally separated from the input terminal electrode 110 of the resistor. This embodiment also uses the two-dimensional electron gas (2DEG) generated by the stacked structure of the second part 105-2 of the compound semiconductor channel layer and the second part 107-2 of the compound semiconductor barrier layer as a resistor, so it can be called It is a two-dimensional electron gas (2DEG) resistor, in which a plurality of mutually separated conductive rings 150 are used to electrically connect those mutually separated rings that generate two-dimensional electron gas (2DEG). In this embodiment, the resistance value of the resistor can be changed by adjusting the number of rings that are separated from each other. When the number of rings is greater, the path of the current from the input electrode 110 to the drain electrode 120 The longer it is, the higher the resistance value of the resistor.

FIG. 7 is a schematic cross-sectional view of the semiconductor device 100 along the cross-sectional tangent line CC' of FIG. 6 according to yet another embodiment of the present disclosure. In the semiconductor device 100 of FIG. 7 , the passive component region 100R The top view shape of the stacked structure of the second portion 105-2 of the compound semiconductor channel layer 105 and the second portion 107-2 of the compound semiconductor barrier layer 107 is a plurality of rings separated from each other. Among these rings The gaps between are filled with insulating material 109, such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. In addition, on the second part 107-2 of the compound semiconductor barrier layer 107 in the passive device region 100R, an input terminal electrode 110 is provided in the center of the passive device region 100R, and between the input terminal electrode 110 and the drain electrode 120 A plurality of conductive rings 150 that are separated from each other are provided. When viewed from above, these conductive rings 150 partially overlap with the aforementioned plurality of separated rings, and the input terminal electrode 110 is located directly above a part of the insulating material 109. These conductive rings 150 is located directly above another portion of insulating material 109 . In some embodiments, the composition of the input terminal electrode 110 and these conductive rings 150 may be the same as the composition of the source electrode 140 and the drain electrode 120 , such as titanium (Ti), aluminum (Al), nickel (Ni), gold. (Au) or a multi-layer stack structure of the aforementioned metal layers, and the same process steps can be used to simultaneously form the source electrode 140, the drain electrode 120, the input terminal electrode 110 and these conductive rings 150.

FIG. 8 is a schematic top view of a semiconductor device 100 according to another embodiment of the present disclosure. In the semiconductor device 100 of FIG. 8 , the second portion 105 - 2 of the compound semiconductor channel layer in the passive device region 100R The stacked structure of the second portion 107-2 of the compound semiconductor barrier layer is circular in plan view, and the input terminal electrode 110 is located at the center of the circle. In addition, the resistor in the passive component region 100R also includes a spiral conductor 160 connected from the input terminal electrode 110 to the drain electrode 120, which is disposed on the second part 107-2 of the compound semiconductor barrier layer. This embodiment can also utilize the two-dimensional electron gas (2DEG) generated by the stacked structure of the second part 105-2 of the compound semiconductor channel layer and the second part 107-2 of the compound semiconductor barrier layer as a resistor, so it can It is called a two-dimensional electron gas (2DEG) resistor, in which the spiral conductor 160 connected from the input electrode 110 to the drain electrode 120 can be used as one of the paths of the current, whereby the resistance value of the resistor can be adjusted, for example Increase the number of turns of the spiral conductor 160 to increase the resistance of the resistor value.

In some embodiments, an insulating doped region is formed on the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer to form the input terminal electrode 110 in a top view. Two-dimensional electron gas (2DEG) is radiated toward the drain electrode 120 in a radial shape, spirally connected from the input terminal electrode 110 to the drain electrode 120 , or concentrically arranged from the input terminal electrode 110 to the drain electrode 120 . resistor. The insulating doped region may be formed, for example, by applying external energy to destroy the crystal lattice of the second part 105-2 of the compound semiconductor channel layer and the second part 107-2 of the compound semiconductor barrier layer, or by An ion implantation process is performed to implant specific non-conductor dopants into the second portion 105-2 of the compound semiconductor channel layer and the second portion 107-2 of the compound semiconductor barrier layer.

FIG. 9 is a schematic cross-sectional view of the semiconductor device 100 along the cross-sectional tangent line DD' in FIG. 8 according to yet another embodiment of the present disclosure. In the semiconductor device 100 in FIG. 9 , the input terminal electrode 110 The spiral conductor 160 and the spiral conductor 160 are both disposed on the second part 107-2 of the compound semiconductor barrier layer in the passive device region 100R, and the input terminal electrode 110 is in contact with a partial section of one end of the spiral conductor 160 and connected to each other. . In one embodiment, the input electrode 110 and the spiral conductor 160 can be formed from the same conductive layer, for example, by depositing and patterning the same metal layer to simultaneously form the input electrode 110 and the spiral conductor 160. The composition of the electrode 110 and the spiral conductor 160 is, for example, metal or polycrystalline silicon.

The semiconductor device of the embodiment of the present disclosure integrates a resistor and a high electron mobility transistor, wherein the resistor is a two-dimensional electron gas (2DEG) resistor, and the resistor is disposed in a region where the high electron mobility transistor is formed, Therefore, the resistor does not occupy additional area, saving the layout area of the electronic circuit. In addition, compared with silicon-based resistors, the two-dimensional electron gas (2DEG) resistors of embodiments of the present disclosure are more accurate in sensing current and are electrically more robust and durable. In addition, one end of the resistor in the embodiment of the present disclosure can be electrically coupled to the high-voltage end of the circuit, and the other end of the resistor can be electrically coupled to the drain electrode of the high electron mobility transistor, whereby the resistor can be used to conduct high-voltage terminal current monitoring to protect high electron mobility transistors. In addition, the resistors and high electron mobility transistors of the embodiments of the present disclosure The processes can be integrated together without the need to form additional photoresist layers, nor to perform additional photolithography and etching processes, to produce resistors and high electron mobility transistors at the same time. Therefore, the semiconductors of the embodiments of the present disclosure The device has simple manufacturing steps and can reduce manufacturing costs.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

100:Semiconductor device

100A: Ring-shaped active component area

100R: Passive component area

105-1: The first part of the compound semiconductor channel

105-2: The second part of the compound semiconductor channel

107-1: The first part of the compound semiconductor barrier layer

107-2: The second part of the compound semiconductor barrier layer

109:Insulating materials

110: Input terminal electrode

120. D: Drain electrode

130. G: Gate electrode

140. S: Source electrode

Claims (13)

A semiconductor device, including: a high electron mobility transistor, disposed in a ring-shaped active element region, including: a first part of a compound semiconductor channel layer; a first part of a compound semiconductor barrier layer , stacked on the first portion of the compound semiconductor channel layer; and a source electrode, a gate electrode and a drain electrode disposed on the first portion of the compound semiconductor barrier layer; and a The resistor is disposed in a passive element area surrounded by the annular active element area, including: a second part of the compound semiconductor channel layer; a second part of the compound semiconductor barrier layer, stacked on the on the second part of the compound semiconductor channel layer; and an input terminal electrode disposed on the second part of the compound semiconductor barrier layer and located in the center of the passive component region. The semiconductor device of claim 1, wherein the resistor is a two-dimensional electron gas and its top view shape includes a radial shape, a spiral shape or a concentric circle shape from the input terminal electrode toward the drain electrode. The semiconductor device of claim 1, wherein one end of the resistor is electrically coupled to the input electrode, and the other end of the resistor is electrically coupled to the drain electrode. The semiconductor device of claim 1, wherein the second portion of the compound semiconductor channel layer of the resistor and the second portion of the compound semiconductor barrier layer are vertically aligned, and their top view The shape includes a radial shape or a spiral shape from the input terminal electrode toward the drain electrode. The semiconductor device of claim 4, wherein the gaps between the radial shapes or the spiral shapes are filled with an insulating material. The semiconductor device of claim 1, wherein the second portion of the compound semiconductor channel layer of the resistor and the second portion of the compound semiconductor barrier layer are vertically aligned, and their top view shape includes a plurality of mutual Separate rings are arranged concentrically between the input electrode and the drain electrode. The semiconductor device of claim 6, wherein the resistor further includes a plurality of conductive rings separated from each other, disposed on the second part of the compound semiconductor barrier layer, and viewed from above, the plurality of conductive rings separated from each other The conductive ring is located between the plurality of mutually separated rings to electrically connect the plurality of mutually separated rings in series. The semiconductor device as claimed in claim 7, wherein the gaps between the plurality of mutually separated rings are filled with an insulating material. The semiconductor device of claim 8, wherein the input terminal electrode is located above a part of the insulating material, and the plurality of conductive rings separated from each other is located above another part of the insulating material. The semiconductor device of claim 1, wherein the second portion of the compound semiconductor channel layer of the resistor and the second portion of the compound semiconductor barrier layer are vertically aligned, and their top view shape includes a circle. , the input terminal electrode is located at the center of the circle. The semiconductor device of claim 10, wherein the resistor further includes a spiral conductor connected from the input electrode to the drain electrode and disposed on the second portion of the compound semiconductor barrier layer. The semiconductor device according to claim 1, wherein the top view shape of the source electrode, the gate electrode and the drain electrode includes three mutually separated ring shapes. The semiconductor device of claim 1, wherein the potential of the input terminal electrode is higher than the potential of the drain electrode.

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