TWI783830B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes an insulating layer, a semiconductor layer, and a compound semiconductor stacked layer disposed on a substrate in sequence, a first transistor, a second transistor, an isolation structure, and a conductive structure. The first transistor is disposed in a first element region and includes a first gate, a first source and a first drain disposed on the compound semiconductor stacked layer. The second transistor is disposed in a second element region, and includes a second gate, a second source, and a second drain disposed on the compound semiconductor stacked layer. The isolation structure is disposed between the first transistor and the second transistor. The conductive structure is disposed in the second element region, penetrates the compound semiconductor stacked layer, and electrically connects the semiconductor layer to the second source. There is no electrical connection between the semiconductor layer in the first element region and the first source.

Description

Semiconductor device

The present disclosure relates to semiconductor devices, and more particularly to a semiconductor device including high electron mobility transistors.

In semiconductor technology, III-V compound semiconductors can be used to form various integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors, or high electron mobility transistors (high electron mobility transistors, HEMTs). HEMT is a type of transistor with two dimensional electron gas (2-DEG), and its 2-DEG will be adjacent to the junction between two materials with different energy gaps (ie, heterogeneous junction) . Since HEMT does not use the doped region as the carrier channel of the transistor, but uses 2-DEG as the carrier channel of the transistor, compared with the conventional metal oxide half field effect transistor (MOSFET), HEMT has many attractive features. Human characteristics such as high electron mobility and the ability to transmit signals at high frequencies.

Half-bridge circuits (half-bridge circuits) are widely used in the field of power electronics. When the high-side switching elements and low-side switching elements of the half-bridge circuit share the same substrate, they are vulnerable to series connection. Due to the influence of cross talk, it is difficult to implement a half-bridge circuit of a System on a Chip (SoC). HEMT can be applied in a half-bridge circuit as the upper-bridge switching element and lower-bridge switching element of the half-bridge circuit to achieve the benefits of a system on a chip (SoC). However, when HEMT is applied in a half-bridge circuit, there are still some problems to be overcome. question.

In view of this, the present disclosure proposes a semiconductor device including a high electron mobility transistor with an improved back electrode to solve the problems faced when the high electron mobility transistor is applied in a half-bridge circuit.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a substrate, an insulating layer, a semiconductor layer, a compound semiconductor stack, a first transistor, a second transistor, an isolation structure, and a conductive structure. The insulating layer, the semiconductor layer and the compound semiconductor stack are sequentially arranged on the substrate, the first transistor is located in the first element region, and includes a first gate, a first source and a first drain arranged on the compound semiconductor stack layer, the second transistor is located in the second element region, and includes a second gate, a second source, and a second drain disposed on the compound semiconductor stack, and an isolation structure is disposed between the first transistor and the second transistor Between the crystals, the conductive structure is located in the second element region, runs through the compound semiconductor stack, and electrically connects the semiconductor layer to the second source, wherein there is no electrical connection between the semiconductor layer in the first element region and the first source. sexual connection.

In order to make the features of the present disclosure more comprehensible, the following specifically cites the embodiments, together with the accompanying drawings, for a detailed description as follows.

The present disclosure provides several different embodiments, which can be used to realize different features of the present disclosure. For simplicity of illustration, the present disclosure also describes examples of certain components and arrangements. These examples are provided for the purpose of illustration only, without any limitation. For example, the following description of "the first feature is formed on or over the second feature" may refer to "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". There are other features between the features", so that the first feature is not in direct contact with the second feature. In addition, various embodiments in the present disclosure may use repeated reference characters and/or textual notations. The use of these repeated reference signs and notations is to make the description more concise and clear, but not to indicate the relationship between different embodiments and/or configurations.

In addition, for the space-related narrative vocabulary mentioned in this disclosure, for example: "below", "low", "below", "above", "above", "on", "top "," "bottom" and similar words, for the convenience of description, are used to describe the relative relationship between one element or feature and another (or more) elements or features in the drawing. In addition to the orientations shown in the drawings, these space-related terms are also used to describe possible orientations of semiconductor devices during use and operation. Depending on the orientation of the semiconductor device (rotated by 90 degrees or other orientations), the spatially relative descriptions used to describe its orientation should be interpreted in a similar manner.

Although the present disclosure uses terms such as first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not imply or represent the element The presence of any preceding ordinal number does not imply an order of arrangement of one element over another, or an order in method of manufacture. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or block discussed below may also be referred to as the second element, component, region, layer, or block Of.

The terms "about" or "substantially" mentioned in this disclosure usually mean within 20%, preferably within 10%, and more preferably within 5%, of a given value or range Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the description are approximate quantities, that is, the meaning of "about" or "substantial" may still be implied if "about" or "substantial" is not specified.

The words "coupling", "coupling" and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if it is described that a first component is coupled to a second component, it means that the first component may be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

In this disclosure, "group III-V semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element. Among them, the third group element can be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the fifth group element can be nitrogen (N), phosphorus (P), arsenic (As) or Antimony (Sb). Further, "three and five group semiconductors" can be binary compound semiconductors, ternary compound semiconductors or quaternary compound semiconductors, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), Gallium Arsenide (GaAs), Aluminum Gallium Nitride (AlGaN), Indium Aluminum Gallium Nitride (InAlGaN), Indium Gallium Nitride (InGaN), Aluminum Nitride (AlN), Gallium Indium Phosphide (GaInP), Aluminum Arsenide Gallium (AlGaAs), Aluminum Indium Arsenide (InAlAs), Aluminum Indium Arsenide (InGaAs), Aluminum Nitride (AlN), Gallium Indium Phosphide (GaInP), Aluminum Gallium Arsenide (AlGaAs), Aluminum Indium Arsenide (InAlAs) ), indium gallium arsenide (InGaAs), its analogs, or a combination of the above compounds, but not limited thereto. In addition, depending on the requirements, dopants may also be included in the III-V semiconductor, and it is a III-V semiconductor with a specific conductivity type, such as an n-type or a p-type III-V semiconductor. Hereinafter, III-V semiconductors may also be referred to as III-V semiconductors.

Although the invention disclosed in the present disclosure is described below through specific embodiments, the principles of the invention disclosed in the present disclosure can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those having ordinary skill in the art.

The present disclosure relates to a semiconductor device including a high electron mobility transistor (HEMT), which can be used as a high voltage (high voltage) switching element (or called a high voltage switching element) and a low voltage (low voltage) switching element ( or called the lower bridge switching element), according to the embodiment of the present disclosure, there is no electrical connection between the back pole and the source of the HEMT as the upper bridge switching element, but the back pole of the HEMT of the upper bridge switching element Electrically connected to the ground terminal, or make the back of the HEMT of the high-side switching element an electrically floating layer (electrically floating layer), so that there will be no parasitic capacitance between the back of the high-side switching element and the substrate of the semiconductor device , thereby preventing the input/output voltage of the semiconductor device from being affected, and preventing the thickness between the back electrode and the substrate of the semiconductor device from limiting the capability of the device supply voltage (Vbus).

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosure. As shown in FIG. 1 , in one embodiment, the semiconductor device 100 includes a substrate 101 , an insulating layer 103 , a semiconductor layer 105 and a compound semiconductor stack 110 sequentially arranged from bottom to top. According to some embodiments, the material of the substrate 101 may include ceramics, silicon carbide (SiC), aluminum nitride (AlN), sapphire or silicon. When the substrate 101 is made of a material with high hardness, high thermal conductivity, and low conductivity, such as a ceramic substrate, it is more suitable for high-voltage semiconductor devices. Wherein, the above-mentioned high hardness, high thermal conductivity, and low electrical conductivity are compared with single crystal silicon substrates, and the high-voltage semiconductor device refers to a semiconductor device with an operating voltage higher than 50V. The material of the insulating layer 103 may include silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, and the material of the semiconductor layer 105 may include silicon or polysilicon. In one embodiment, the substrate 101 is, for example, silicon, the insulating layer 103 is, for example, silicon oxide, and the semiconductor layer 105 is, for example, silicon, and the substrate 101, the insulating layer 103 and the semiconductor layer 105 constitute a semiconductor on insulator (SOI) ) substrate, that is, the substrate 101, the insulating layer 103 and the semiconductor layer 105 of an embodiment of the present disclosure may be provided by an SOI substrate. In another embodiment, the substrate 101, the insulating layer 103 and the semiconductor layer 105 can be provided by a composite substrate (also called a QST substrate) composed of a core substrate wrapped by a composite material layer, wherein the core substrate includes ceramics, silicon carbide, Aluminum nitride, sapphire or silicon, the composite material layer includes an insulating material layer and a semiconductor material layer, the insulating material layer can be single-layer or multi-layer silicon oxide, silicon nitride or silicon oxynitride, and the semiconductor material layer can be silicon or polysilicon, Moreover, during the fabrication of the semiconductor device, the composite material layer on the back of the core substrate is removed through a thinning process, such as grinding or etching, so that the back of the core substrate is exposed. In some embodiments, the thickness of the insulating layer 103 may range from about 1 micron (µm) to 3 microns (µm), such as about 2 microns (µm), and the thickness of the semiconductor layer 105 may range from about 5 nanometers (nm). The thickness of the semiconductor layer 105 can be moderately adjusted to 350 nanometers (nm), so that no cracks will occur. In some embodiments, the substrate 101 is an insulating substrate, and its material includes ceramics, aluminum nitride or sapphire. In other embodiments, the substrate 101 is electrically connected to the ground.

According to an embodiment of the present disclosure, the compound semiconductor stack 110 is disposed on the semiconductor layer 105 to form a high electron mobility transistor. The compound semiconductor stack 110 can be formed on the semiconductor layer 105 by epitaxial growth, and the semiconductor layer 105 can serve as a nucleation layer of the compound semiconductor stack 110 . According to some embodiments, the compound semiconductor stack 110 may include a buffer layer (buffer layer) 106, a high resistance layer (high resistance layer) (or called an electrical isolation layer) 107, a channel layer (channel layer) 108 and a barrier layer ( The barrier layer) 109 is sequentially stacked on the semiconductor layer 105 from bottom to top, and the materials of each layer of the compound semiconductor stack 110 include group III and five compound semiconductors (also called III-V group semiconductors). In one embodiment, the buffer layer 106 may be a superlattice (superlattice, SL) structure, for example, including a plurality of alternately stacked aluminum gallium nitride (AlGaN) layers and aluminum nitride (AlN) layers, the high resistance layer 107, for example is a carbon-doped gallium nitride (c-GaN) layer, the channel layer 108 is, for example, an undoped gallium nitride (u-GaN) layer, and the barrier layer 109 is, for example, an aluminum gallium nitride (AlGaN) layer, but Not limited to this. In addition, the compound semiconductor stack 110 may further include other layers, such as an epitaxial layer (for example: AlN) for reducing lattice defects, and the epitaxial layer may be disposed between the buffer layer 106 and the semiconductor layer 105 . The composition and structural configuration of each layer of the compound semiconductor stack 110 can be determined according to the requirements of various semiconductor devices.

According to an embodiment of the present disclosure, the semiconductor device 100 further includes a first transistor 100-1 and a second transistor 100-2, the first transistor 100-1 is located in the first element region 101-1, and includes a first gate The electrode G1 , the first source S1 and the first drain D1 are disposed on the compound semiconductor stack 110 . The second transistor 100 - 2 is located in the second element region 101 - 2 and includes a second gate G2 , a second source S2 and a second drain D2 disposed on the compound semiconductor stack 110 . In addition, the first transistor 100-1 further includes a first capping layer 111 disposed between the first gate G1 and the barrier layer 109, and the second transistor 100-2 further includes a second capping layer 112 disposed between the second gate Between pole G2 and barrier layer 109. In one embodiment, the first capping layer 111 and the second capping layer 112 are, for example, p-type gallium nitride (p-GaN) layers, but are not limited thereto. Since there is a discontinuous energy gap between the channel layer 108 and the barrier layer 109, by stacking the channel layer 108 and the barrier layer 109, electrons will be gathered in the channel layer 108 and the barrier layer 109 due to the piezoelectric effect. The heterojunction between them produces a thin layer of high electron mobility, that is, the two-dimensional electron gas region 2DEG. For normally off (normally off) elements, when no voltage is applied to the first gate G1 and the second gate G2, the area covered by the first capping layer 111 and the second capping layer 112 will not form two Dimensional electron gas (as shown in Figure 1), can be regarded as a 2DEG cut-off region, at this time there will be no conduction. When a positive voltage is applied to the first gate G1 and the second gate G2, the area covered by the first capping layer 111 and the second capping layer 112 will form a two-dimensional electron gas, so that the first source S1 and the first A continuous two-dimensional electron gas region is generated between the drains D1 and between the second source S2 and the second drain D2, and between the first source S1 and the first drain D1, the second source S2 and the The second drain D2 is turned on. In the embodiment of the present disclosure, the first transistor 100-1 and the second transistor 100-2 are high electron mobility transistors (HEMT).

In addition, the semiconductor device 100 further includes an isolation structure 120 disposed between the first transistor 100-1 and the second transistor 100-2. In some embodiments, the isolation structure 120 penetrates the compound semiconductor stack 110 and the semiconductor layer 105 , and further extends down to a depth position of the insulating layer 103 . The bottom surface of the isolation structure 120 may be lower than the top surface of the insulating layer 103 . A deep trench can be etched in the compound semiconductor stack 110, the semiconductor layer 105, and the insulating layer 103, and the deep trench can be filled with a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof, and undergo chemical mechanical planarization ( The isolation structure 120 is formed by a chemical-mechanical planarization (CMP) process. In some embodiments, the isolation structure 120 can be one or more ring-shaped insulating column structures surrounding the first transistor 100-1 and the second transistor 100-2. In the embodiment of the present disclosure, the semiconductor layer 105 can serve as the backside electrodes of the first transistor 100-1 and the second transistor 100-2, and penetrate through the isolation structure of the compound semiconductor stack 110 and the semiconductor layer 105 120 can provide good electrical isolation between the first transistor 100-1 and the second transistor 100-2.

FIG. 2 is a half-bridge circuit 130 according to an embodiment of the present disclosure. As shown in FIG. 2 , the first transistor 100-1 can be a high voltage switching element (or called is the upper bridge switching element), the second transistor 100-2 can be a low voltage (low voltage) switching element (or called the lower bridge switching element) of the half bridge circuit 130, wherein the first drain D1 of the upper bridge switching element connected to an input voltage node Vin, the second source S2 of the switch element of the lower bridge is electrically connected to the ground terminal GND, the first source S1 of the switch element of the upper bridge is electrically connected to the second drain D2 of the switch element of the lower bridge, and It can also be further electrically connected to an output voltage node (not shown). Please refer to FIG. 1 and FIG. 2 at the same time, the semiconductor device 100 further includes a conductive structure 113 disposed in the second element region 101-2, the conductive structure 113 penetrates the compound semiconductor stack 110 in the second element region 101-2, and The semiconductor layer 105 in the second element region 101-2 is electrically connected to the second source S2. Since the semiconductor layer 105 can be used as the back electrode B1 of the first transistor 100-1 and the back electrode B2 of the second transistor 100-2, the conductive structure 113 can connect the second transistor 100-2 (also called the lower bridge switch) The back electrode B2 of the element) is electrically connected to the second source S2, and the second source S2 of the lower bridge switching element is usually electrically connected to the ground node, so the back electrode B2 of the second transistor 100-2 can be connected through the conductive structure 113 and the second source S2 are electrically grounded.

In addition, according to the embodiment of the present disclosure, there is no electrical connection between the semiconductor layer 105 located in the first element region 101-1 and the first source S1, that is, the first transistor 100-1 (also referred to as the upper The back electrode B1 of the bridge switching element) is not directly electrically connected to the first source S1, and there is no conductive structure penetrating through the compound semiconductor stack 110 and connected to the semiconductor layer 105 in the vertical projection area of the first source S1. Since the first source S1 of the upper bridge switching element is electrically connected to the second drain D2 of the lower bridge switching element through the interconnection structure 117, and has the potential of the output voltage, the first element region of the embodiment of the present disclosure The semiconductor layer 105 in 101-1 will not be electrically connected to the first source S1, so the semiconductor layer 105 in the first element region 101-1 will not have the potential of the output voltage, thereby preventing the first element region 101-1 from A parasitic capacitance is generated between the inner semiconductor layer 105 and the substrate 101 , thereby preventing the input/output voltage of the semiconductor device 100 from being affected and maintaining a normal operating voltage.

According to an embodiment of the present disclosure, please refer to FIG. 1 and FIG. 2 at the same time, the semiconductor layer 105 in the first element region 101-1 (the back electrode B1 of the upper bridge switching element) can be arranged on the first gate G1, Another conductive structure 115 outside the first source S1 and the first drain D1 is electrically connected to the ground terminal. As shown in FIG. 2, in one embodiment, the back pole B1 of the upper bridge switching element and the lower bridge switching element Both of the second sources S2 are electrically connected to the same ground node. As shown in FIG. 1, in an embodiment, another conductive structure 115 is disposed in an area other than the vertical projection area of the first gate G1, the first source S1, and the first drain D1, and the conductive structure 115 Through the compound semiconductor stack 110, electrically connected to the semiconductor layer 105, the conductive structure 115 can be electrically connected to the ground terminal through the conductive pad (conductive pad) 116 disposed above it, so that the back electrode B1 of the upper bridge switching element is connected to the ground through the conductive structure. 115, conductive pads 116 and other connecting structures are electrically connected to the ground terminal.

FIG. 3 is a schematic top view of a semiconductor device according to an embodiment of the disclosure. As shown in FIG. 3 , in one embodiment, the periphery of the first device region 101 - 1 and/or the second device region 101 - 2 is surrounded by a conductive sealing ring 140 . The conductive pad 116 in the first element region 101-1 can be electrically connected to a sealing ring (seal ring) 140 provided on the periphery of the element region of the semiconductor device 100 via a wire 118, and electrically connected to a ground terminal through the sealing ring 140, so that the first The conductive structure 115 located under the conductive pad 116 in a device region 101-1 is electrically connected to the ground terminal, thereby allowing the semiconductor layer 105 in the first device region 101-1 to be electrically grounded. The aforementioned wires 118 may be disposed in a dielectric layer (not shown) above the conductive pads 116 , but is not limited thereto. Although only two first element regions 101-1 and two second element regions 101-2 are shown surrounded by the sealing ring 140 in Fig. 3, there may be more element regions surrounded by the sealing ring 140, And each device area is surrounded by the isolation structure 120 , in one embodiment, the isolation structures 120 can be interconnected to form a network structure. In addition, the isolation structure 120 can be an insulating column structure, surrounding the conductive structure 115 below the conductive pad 116, so as to avoid unnecessary electrical connection between the adjacent first device region 101-1 and the second device region 101-2.

FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the disclosure. The difference between the semiconductor device 100 in FIG. 4 and the semiconductor device 100 in FIG. 1 lies in the first source S1 and the first drain D1 of the first transistor 100-1, and the second source of the second transistor 100-2. Both the electrode S2 and the second drain electrode D2 extend downwards through the barrier layer 109 to reach the top surface of the channel layer 108, and the conductive structure 113 in the second element region 101-2 is arranged directly under the second source electrode S2, and runs through the entire channel layer 108 , high resistance layer 107 and buffer layer 106 , but does not penetrate the barrier layer 109 . In another embodiment, the first source S1, the first drain D1, the second source S2, and the second drain D2 may further extend downwards to a depth position of the channel layer 108, and communicate with the second source The conductive structure 113 in contact with the pole S2 may penetrate part of the channel layer 108 , the high resistance layer 107 and the buffer layer 106 .

In addition, in the semiconductor device 100 shown in FIG. 4, the isolation structure 120 penetrates the compound semiconductor stack 110 and the semiconductor layer 105, and reaches the top surface of the insulating layer 103, that is, the bottom surface of the isolation structure 120 is on the same level as the top surface of the insulating layer 103. flat. In some embodiments, the substrate 101 is an insulating substrate, and its material includes ceramics, aluminum nitride or sapphire. In other embodiments, the substrate 101 is electrically connected to the ground. In addition, in the semiconductor device 100 in FIG. 4, the semiconductor layer 105 in the first element region 101-1 can be an electrically floating layer, that is, the semiconductor layer 105 in the first element region 101-1 does not see through the semiconductor layer 105 in FIG. 1. The other conductive structure 115 shown is electrically connected to the ground terminal, but the semiconductor layer 105 in the first element region 101-1 has a floating potential close to 0V. Since the substrate 101 has a ground potential or is an insulating substrate, the There is no parasitic capacitance between the semiconductor layer 105 and the substrate 101 in the device region 101 - 1 .

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the disclosure. As shown in FIG. 5, the difference between the semiconductor device 200 of this embodiment and the semiconductor device 100 in FIG. 1 and FIG. The semiconductor layers 105 in the first element region 101 - 1 are electrically connected through the conductive structure 113 . FIG. 6 is a half-bridge circuit 230 according to another embodiment of the present disclosure. Please refer to FIG. 5 and FIG. 6 at the same time. Layer 105, that is, the back electrode B1 of the first transistor 200-1 is electrically connected to the first source S1, and the first source S1 is electrically connected to the second drain D2, and is further electrically connected to the output voltage node (not shown), therefore, the semiconductor layer 105 in the first element region 101-1 of the semiconductor device 200 of this embodiment will have a floating potential from 0V to the output voltage, resulting in the first element region 101-1 of the semiconductor device 200 A parasitic capacitance Cox is generated between the inner semiconductor layer 105 and the substrate 101 , which affects the input/output voltage of the semiconductor device 200 and causes the power supply to fail to maintain a normal working voltage.

In addition, the parasitic capacitance Cox of the semiconductor device 200 of this embodiment will be affected by the thickness of the insulating layer 103. To reduce the parasitic capacitance Cox, the thickness of the insulating layer 103 of the semiconductor device 200 must be increased. However, when the thickness of the insulating layer 103 is greater If it is thicker, the heat dissipation capability of the semiconductor device 200 will also deteriorate, resulting in a decrease in the performance of the semiconductor device 200 .

In contrast, for the semiconductor device 100 illustrated in FIGS. 1 to 4, since the semiconductor layer 105 in the first device region 101-1 of the semiconductor device 100 of the embodiment of the present disclosure, that is, the upper bridge switching device The back electrode B1 of the first transistor 100-1 is electrically connected to the ground node, or is an electrically floating layer with a potential close to 0V, so there is no gap between the semiconductor layer 105 and the substrate 101 in the first element region 101-1. There will be parasitic capacitance, and the thickness of the insulating layer 103 will not be limited, that is, the thickness of the insulating layer 103 can be relatively thin, so as to maintain the heat dissipation capability of the semiconductor device 100 . In addition, according to some embodiments of the present disclosure, the substrate 101 is an electrically insulating and thermally conductive substrate, such as made of highly insulating and highly thermally conductive aluminum nitride (AlN), whose thermal conductivity is higher than that of the insulating layer 103 . At this time, the base 101 can not only increase the heat dissipation capability of the semiconductor device 100, but also increase the thickness of the overall insulation constituting the parasitic capacitance (that is, the thickness of the insulating layer 103 plus the thickness of the base 101), thereby greatly reducing the parasitic capacitance. The parasitic capacitance can be substantially eliminated and neglected, so that the limitation of the device supply voltage (Vbus) by the thickness of the insulating layer (thickness in the vertical direction) under the back electrode of the semiconductor device 100 can be avoided.

Therefore, the semiconductor device of the embodiment of the present disclosure can use high electron mobility transistors as the upper-bridge switching element and the lower-bridge switching element of the half-bridge circuit, so as to achieve the benefits of a system on a chip (SoC) and avoid the gap between the upper and lower bridge switching elements. The parasitic inductance and capacitance effects caused by wire bonding can also eliminate the parasitic capacitance between the back electrode and the substrate of the upper bridge switching element, avoiding the limitation of the thickness of the insulating layer under the back electrode on the power supply voltage (Vbus) of the device to maintain The heat dissipation function of the semiconductor device improves the efficiency of the semiconductor device. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Semiconductor device 100-1: The first transistor 100-2: The first transistor 101: Base 101-1: The first component area 101-2: Second component area 103: insulation layer 105: Semiconductor layer 106: buffer layer 107: High resistance layer 108: Channel layer 109: Barrier layer 110:Compound semiconductor stack 111: The first cover layer 112: Second cover layer 113: Conductive structure 115: Conductive structure 116: Conductive pad 117:Interconnect structure 118: wire 120: Isolation structure 130: Half bridge circuit 140: sealing ring 200: Semiconductor device 200-1: The first transistor 200-2: The first transistor 230: Half bridge circuit G1: the first gate G2: the second gate S1: first source S2: second source D1: the first drain D2: the second drain 2DEG: two-dimensional electron gas region B1, B2: back pole Vin: input voltage node GND: ground terminal Cox: parasitic capacitance

In order to make the following easier to understand, you can refer to the drawings and their detailed descriptions at the same time when reading this disclosure. Through the specific embodiments herein and referring to the corresponding drawings, the specific embodiments of the present disclosure are explained in detail, and the working principle of the specific embodiments of the present disclosure is explained. In addition, for the sake of clarity, the various features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be intentionally enlarged or reduced. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosure. FIG. 2 is a half-bridge circuit according to an embodiment of the disclosure. FIG. 3 is a schematic top view of a semiconductor device according to an embodiment of the disclosure. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the disclosure. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the disclosure. FIG. 6 is a half-bridge circuit according to another embodiment of the disclosure.

100: Semiconductor device

100-1: The first transistor

100-2: The first transistor

101: Base

101-1: The first component area

101-2: Second component area

103: insulation layer

105: Semiconductor layer

106: buffer layer

107: High resistance layer

108: Channel layer

109: Barrier layer

110:Compound semiconductor stack

111: The first cover layer

112: Second cover layer

113: Conductive structure

115: Conductive structure

116: Conductive pad

117:Interconnect structure

120: Isolation structure

G1: the first gate

G2: the second gate

S1: first source

S2: second source

D1: the first drain

D2: the second drain

2DEG: two-dimensional electron gas region

Claims (20)

A semiconductor device comprising: An insulating layer, a semiconductor layer and a compound semiconductor stack are sequentially arranged on a substrate; A first transistor, located in a first element region, and including a first gate, a first source and a first drain disposed on the compound semiconductor stack; A second transistor, located in a second element region, and including a second gate, a second source and a second drain disposed on the compound semiconductor stack; an isolation structure disposed between the first transistor and the second transistor; and a conductive structure, located in the second element region, passing through the compound semiconductor stack, and electrically connecting the semiconductor layer to the second source, There is no electrical connection between the semiconductor layer located in the first element region and the first source. The semiconductor device according to claim 1, wherein the semiconductor layer located in the first element region is an electrically floating layer, or is arranged to be electrically connected to a ground node. The semiconductor device according to claim 1, wherein the semiconductor layer located in the first element region is electrically connected to a ground terminal through a sealing ring. The semiconductor device according to claim 3, further comprising another conductive structure located in the first element region and penetrating through the compound semiconductor stack, wherein the another conductive structure electrically connects the sealing ring to the semiconductor layer. The semiconductor device according to claim 4, wherein the other conductive structure is disposed outside the vertical projection area of the first gate, the first source, and the first drain of the first transistor. The semiconductor device as claimed in claim 1, wherein the first transistor and the second transistor include high electron mobility transistors, the first transistor is a high-voltage switching element of a half-bridge circuit, and the second transistor It is a low-voltage switching element of the half-bridge circuit. The semiconductor device as claimed in claim 1, wherein the semiconductor layer located in the first element region and the second source are electrically connected to the same ground node. The semiconductor device as claimed in claim 1, wherein the substrate is electrically connected to a ground terminal. The semiconductor device as claimed in claim 1, wherein the substrate, the insulating layer and the semiconductor layer form a semiconductor on insulator (SOI) substrate. The semiconductor device according to claim 1, wherein the substrate is an insulating substrate. The semiconductor device according to claim 1, wherein the semiconductor layer is a seed layer. The semiconductor device according to claim 1, wherein the semiconductor layer has a thickness of 5 nm to 350 nm. The semiconductor device according to claim 1, wherein the insulating layer has a thickness of 1 micron to 3 microns. The semiconductor device according to claim 1, wherein the substrate includes ceramics, silicon carbide, aluminum nitride, sapphire or silicon, the insulating layer includes silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, and the semiconductor layer includes silicon or polysilicon. The semiconductor device according to claim 1, wherein the compound semiconductor stack includes a buffer layer, a high resistance layer, a channel layer, and a barrier layer, which are sequentially arranged on the semiconductor layer, and the compound semiconductor stack The materials include III-V compound semiconductors. The semiconductor device as claimed in claim 15, wherein the first source, the first drain, the second source, and the second drain are disposed on the barrier layer, or pass through the barrier layer to the channel layer. The semiconductor device as claimed in claim 15, further comprising a first capping layer disposed between the first gate and the barrier layer, and a second capping layer disposed between the second gate and the barrier layer between. The semiconductor device as claimed in claim 1, wherein the isolation structure penetrates the compound semiconductor stack and the semiconductor layer, and the bottom surface of the isolation structure is lower than the top surface of the insulating layer, or the bottom surface of the isolation structure is closer to the insulating layer tops are on the same plane. The semiconductor device according to claim 1, wherein the isolation structure is an insulating column structure, which penetrates the compound semiconductor stack and the semiconductor layer, and surrounds the first transistor and the second transistor. The semiconductor device according to claim 19, further comprising another conductive structure located in the first element region and penetrating through the compound semiconductor stack, wherein the insulating column structure surrounds the other conductive structure, and the other The conductive structure is electrically connected to the ground terminal.

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