JP2006351691A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including a hetero junction field effect transistor operating equivalently to a normally-off and having excellent characteristics of an original semiconductor element with high reliability and with a small package size. <P>SOLUTION: The semiconductor device includes a normally-on hetero junction field effect transistor 100 having high withstand voltage; and a hetero junction field effect transistor 100 operating equally to that of a normally-off type, by forming a normally-off insulating gate type field effect transistor 200 into monolithic and connecting them in cascode. Further, an avalanche diode 300 is connected in parallel to the insulating gate type field effect transistor 200 to prevent the same transistor 200 from being destroyed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a power semiconductor device in which a breakdown voltage maintaining portion is formed of a semiconductor material having a wider band gap than silicon (Si) (hereinafter referred to as a wide band gap semiconductor).

Conventionally, gallium nitride (GaN) -based compound semiconductors have been used as semiconductor materials in semiconductor elements for high-frequency devices. For example, on a p-type conductive substrate made of silicon, in order, a buffer layer made of high-resistance aluminum gallium nitride (Al _x Ga _1-x N, 0 <x ≦ 1), a carrier traveling layer made of undoped gallium nitride, And a surface barrier layer (carrier supply layer) made of n-type aluminum gallium nitride (Al _y Ga _1-y N, 0 <y ≦ 1) is stacked, and a gate electrode having a Schottky property is formed on the surface barrier layer. A heterojunction field effect transistor (hereinafter referred to as HFET) having a selectively formed structure is known (for example, see Patent Document 1).

  Recently, in the field of power semiconductor devices, attempts have been made to use wide band gap semiconductors such as gallium nitride compound semiconductors. For example, in the semiconductor element disclosed in Patent Document 1, a source electrode and a drain electrode are selectively formed on the surface barrier layer, and any one of the electrodes includes a buffer layer, a carrier travel layer, and a surface. By being filled in a hole penetrating the barrier layer, it is configured to be electrically connected to the conductive substrate.

  However, in the semiconductor device disclosed in Patent Document 1 and the conventional HFET, when the signal is not input to the gate, the source and the drain are in a conductive state (hereinafter referred to as normally-on) and short-circuited. It becomes a state. When such a normally-on type semiconductor device is used in a power facility, when a failure occurs in an electric circuit and a signal cannot be sent to the gate, that is, a signal is not input to the gate. The power supply to the load cannot be stopped. Therefore, there is a risk that a large current flows through the load, resulting in destruction of the load.

  In order to avoid such a problem, the semiconductor element must be in an off state (hereinafter referred to as normally off) when no signal is input to the gate. In view of this, a semiconductor device has been reported in which an external circuit is added to a normally-on type semiconductor element so as to operate as a normally-off type semiconductor element when viewed from the outside (for example, non-onset type). (See Patent Document 1).

  In the semiconductor device disclosed in Non-Patent Document 1, a normally-on semiconductor element made of silicon carbide (SiC) and a low breakdown voltage MOSFET made of silicon (insulation having a metal-oxide-semiconductor structure). A gate type field effect transistor) is cascode-connected. Since the MOSFET operates normally-off, the semiconductor device operates as an insulated gate normally-off semiconductor element with respect to the outside.

  By the way, a voltage is applied to at least one terminal of a silicon-based transistor, a group III-V compound semiconductor element integrally formed on a silicon substrate via a group III-V compound buffer layer, and a group III-V compound semiconductor element. A semiconductor device including a DC-DC converter that applies a voltage is known (for example, see Patent Document 2). In this semiconductor device, at least a part of the DC-DC converter is composed of the silicon transistor.

JP 2004-363563 A JP 2004-281454 A Dr. Ilia Zverev, 3 others, "Silicon Carbide questions the settled hierarchy of converter topologies", International Exhibition & Conference for Power Electronics (PCIM Europe) ) (International Exhigition & Conference for Power Electronics (PCIM Europe)), Nuremberg, Germany, May 20-22, 2003, p. 73-78

  However, in the semiconductor device disclosed in Non-Patent Document 1, since it is necessary to mount a silicon chip in addition to the silicon carbide chip, there is a problem that the size of a package enclosing these chips becomes large. Further, since the two chips are electrically connected by the wire electrode, there are problems such as an increase in the number of processes and a decrease in reliability due to the wire bonding process. When these problems occur, the excellent characteristics of the original semiconductor element are impaired.

  The present invention has an HFET that operates in the same manner as a normally-off type in order to eliminate the above-described problems caused by the prior art, and has a small package size, high reliability, and excellent characteristics of the original semiconductor element. An object of the present invention is to provide a semiconductor device provided with

  In order to solve the above-described problems and achieve the object, a semiconductor device according to claim 1 is formed on a first semiconductor layer made of silicon or silicon carbide and a part of the first semiconductor layer. A second semiconductor layer made of a semiconductor material having a wider band gap than silicon, and a normally-off insulated gate field effect transistor is formed in the first semiconductor layer, and the second semiconductor In the layer, a heterojunction field effect transistor capable of current control by a gate electrode is formed, and the gate of the heterojunction field effect transistor is electrically short-circuited with the source electrode of the insulated gate field effect transistor, The source of the heterojunction field effect transistor is electrically short-circuited with the drain of the insulated gate field effect transistor, That.

  A semiconductor device according to a second aspect of the present invention includes a first semiconductor layer made of silicon, silicon carbide, or sapphire, and a semiconductor material having a wider band gap than silicon formed on the first semiconductor layer. A second semiconductor layer; and a third semiconductor layer made of silicon or silicon carbide formed on a part of the second semiconductor layer with an oxide film interposed therebetween, wherein the third semiconductor layer includes: A lateral and normally-off insulated gate field effect transistor is formed, and a heterojunction field effect transistor capable of current control by a gate electrode is formed in the second semiconductor layer, the heterojunction field effect transistor Is electrically short-circuited with the source electrode of the insulated gate field effect transistor, and the source of the heterojunction field effect transistor is Characterized in that it is a drain electrically shorted type field effect transistor.

  A semiconductor device according to a third aspect of the present invention includes a first semiconductor layer made of silicon, silicon carbide, or sapphire, and a semiconductor material having a wider band gap than silicon formed on the first semiconductor layer. A second semiconductor layer; and a third semiconductor layer made of silicon or silicon carbide formed on a part of the second semiconductor layer, wherein the third semiconductor layer has a vertical and normally-off state Type insulated gate field effect transistor is formed, and in the second semiconductor layer, a heterojunction field effect transistor capable of current control by a gate electrode is formed, and the gate of the heterojunction field effect transistor is The source of the insulated gate field effect transistor is electrically short-circuited, and the source of the heterojunction field effect transistor is connected to the insulated gate field effect transistor. Characterized in that it is a drain electrically shorting Njisuta.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein a diode having a withstand voltage smaller than that of the insulated gate field effect transistor is formed in the first semiconductor layer. The anode is electrically short-circuited with the source electrode of the insulated gate field effect transistor, and the cathode of the diode is electrically shorted with the drain of the insulated gate field effect transistor.

  A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the third aspect, wherein a diode having a breakdown voltage smaller than that of the insulated gate field effect transistor is formed in the third semiconductor layer. The anode is electrically short-circuited with the source electrode of the insulated gate field effect transistor, and the cathode of the diode is electrically shorted with the drain of the insulated gate field effect transistor.

  According to the first to third aspects of the invention, since the portion that maintains the high breakdown voltage is made of the wide band gap semiconductor, a low element resistance can be realized. Further, since the HFET and the normally-off type MOSFET are formed on the same substrate, a semiconductor device having an HFET and having a normally-off operation characteristic can be realized with a monolithic structure. Accordingly, it is possible to reduce the size and improve the reliability of the semiconductor device. According to the invention of claim 4 or 5, since the avalanche diode is connected in parallel to the normally-off type MOSFET, the destruction of the MOSFET can be suppressed, so that a semiconductor device that is not easily destroyed is realized. be able to.

  The semiconductor device according to the present invention has an effect of having an HFET that operates in the same manner as a normally-off type, having a small package size, high reliability, and excellent characteristics of the original semiconductor element. .

Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. In addition, a layer or region having n ⁺ is higher in impurity concentration than a layer or region having n. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, a high-resistance aluminum gallium nitride (Al _x Ga _1-x N, 0 <x ≦ 1) layer 2 serving as a buffer layer is sequentially formed on a part of a p-type single crystal silicon substrate 1. , An undoped or n-type gallium nitride (GaN) layer 3 serving as a carrier traveling layer, and an n-type aluminum gallium nitride (Al _y Ga _1-y N, 0 <y ≦ 1) serving as a surface barrier layer (carrier supply layer) ) Layer 4 is laminated.

The silicon substrate 1 corresponds to a first semiconductor layer. The first semiconductor layer may be made of silicon carbide instead of single crystal silicon. The Al _x Ga _{1 -x} N 2, the GaN layer 3, and the Al _y Ga _{1 -y} N layer 4 stacked on the silicon substrate 1 constitute a second semiconductor layer. In the second semiconductor layer, an HFET 100 that can be controlled by a gate electrode is formed.

The drain electrode 5 and the gate electrode 6 of the HFET 100 are selectively formed on the surface of the Al _y Ga _1-y N layer 4. The drain electrode 5 is in ohmic contact with the Al _y Ga _1-y N layer 4. The gate electrode 6 is in ohmic contact with the Al _y Ga _1-y N layer 4.

A normally-off type MOSFET 200 is formed in a region of the silicon substrate 1 where the second semiconductor layers (Al _x Ga _{1 -x} N 2, GaN layer 3 and Al _y Ga _{1 -y} N layer 4) are not stacked. Yes. On the surface layer of the region where the MOSFET 200 is formed on the silicon substrate 1, an n ⁺ region 7 serving as a drain region of the MOSFET and an n ⁺ region 8 serving as a source region of the MOSFET are formed apart from each other.

An oxide film 9 is formed on the surface of the silicon substrate 1 between the n ⁺ region 7 and the n ⁺ region 8, and a MOSFET gate electrode 10 is formed on the oxide film 9. The source electrode 11 of the MOSFET is in ohmic contact with the silicon substrate 1 and the n ⁺ region 8 serving as the source region of the MOSFET. Further, the source electrode 11 of the MOSFET is short-circuited to the gate electrode 6 of the HFET.

The n ⁺ region 7 serving as the drain region of the MOSFET is short-circuited to the Al _y Ga _1-y N layer 4 serving as the surface barrier layer (carrier supply layer) of the HFET via the short-circuit electrode 12. The source electrode 11 of the MOSFET, the gate electrode 10 of the MOSFET, and the drain electrode 5 of the HFET are connected to the source terminal 13, the gate terminal 14 and the drain terminal 15 of the semiconductor device of the first embodiment, respectively. FIG. 2 shows an equivalent circuit diagram.

  In the semiconductor device of the first embodiment, a high breakdown voltage is maintained in the HFET 100 portion. The HFET 100 is a normally-on type. However, according to the first embodiment, since the HFET 100 and the normally-off type MOSFET 200 are cascode-connected, when the signal is not input to the gate terminal 14, that is, the gate electrode 10 of the MOSFET is in a zero bias state. Sometimes, the MOSFET 200 is turned off. As a result, the source terminal 13 and the drain terminal 15 are turned off, so that a high breakdown voltage can be maintained.

  Here, the MOSFET 200 only needs to have a breakdown voltage of about the gate threshold value of the HFET 100, for example, about 10 to 30 V, and therefore may be a low resistance element. Therefore, there is no need to increase the chip size. As a result, the excellent characteristics of the HFET 100 having a low on-resistance can be enjoyed. Compared to the configuration in which the HFET and the MOSFET are configured as separate chips and connected to each other by wire electrodes, the effect of reducing the number of processes by eliminating the wire bonding process and the reliability by not using the wire electrodes are achieved. Improvement effect is obtained. Thus, by sharing the role in different semiconductor materials existing on the same substrate, a power semiconductor element having excellent characteristics as a whole can be obtained.

Embodiment 2. FIG.
FIG. 3 is a sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. As shown in FIG. 3, in the second embodiment, a region other than the region where the HFET 100 is formed in the second semiconductor layer composed of the Al _x Ga _{1 -x} N 2, the GaN layer 3 and the Al _y Ga _{1 -y} N layer 4. An SOI (silicon-on-insulator) structure composed of an oxide film 16 and a p-type silicon or silicon carbide semiconductor thin film 17 formed thereon is formed on the region of the MOSFET. A MOSFET 200 is formed in this SOI structure portion. Is formed.

The SOI structure semiconductor thin film 17 corresponds to a third semiconductor layer. The n ⁺ region 7 serving as the drain region and the n ⁺ region 8 serving as the source region of the MOSFET 200 are formed apart from each other on the surface layer of the semiconductor thin film 17, and the MOSFET is interposed on the surface between them via the oxide film 9. A gate electrode 10 is formed. Other configurations are the same as those in the first embodiment. In Embodiment 2, sapphire can be used in addition to single crystal silicon or silicon carbide as the substrate to be the first semiconductor layer.

  According to the second embodiment, in addition to the same effects as those of the first embodiment, when manufacturing this semiconductor device, there is an advantage that crystal growth of aluminum gallium nitride or the like can be performed relatively easily. . In addition, since the SOI structure is formed after the epitaxial growth of aluminum gallium nitride, there is an advantage that the influence of heat treatment and contamination on the crystal of the semiconductor thin film 17 having the SOI structure is reduced.

Embodiment 3 FIG.
FIG. 4 is a sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention. As shown in FIG. 4, in the third embodiment, the second semiconductor layer including the Al _x Ga _{1 -x} N 2, the GaN layer 3 and the Al _y Ga _{1 -y} N layer 4 other than the region where the HFET 100 is formed. An epitaxial growth layer of silicon or silicon carbide is formed on this region, and MOSFET 200 is formed in this epitaxial growth layer portion.

In this epitaxial growth layer, the n ⁺ region 7 that becomes the drain region of the MOSFET is provided in contact with the Al _y Ga _{1 -y} N layer 4. A region above the n ⁺ region 7 is an n region 18 that becomes a drift region of the MOSFET, and a region above the n region 18 is a p region 19.

The n ⁺ region 8 serving as the source region of the MOSFET 200 is formed in the surface layer of the p region 19. The source electrode 11 of the MOSFET is in contact with both the n ⁺ region 8 and the p region 19. In the third embodiment, since the n ⁺ region 7 is electrically connected to the Al _y Ga _1-y N layer 4, the electrode to short-circuit the n ⁺ region 7 and the Al _y Ga _1-y N layer 4 (Working The short-circuit electrode 12) of Form 1 is not necessary.

A trench that reaches n region 18 through n ⁺ region 8 and p region 19 on the surface is formed, and gate electrode 10 is buried inside this trench through oxide film 9 that becomes a gate insulating film. . Therefore, in the third embodiment, the MOSFET 200 is a vertical element that allows current to flow in the depth direction of the element. Other configurations are the same as those in the first embodiment. In Embodiment 3, sapphire can be used in addition to single crystal silicon or silicon carbide as the substrate to be the first semiconductor layer. The MOSFET 200 may be an element having a so-called planar type DMOS structure.

  According to the third embodiment, in addition to the same effects as those of the first embodiment, a short-circuit electrode that connects the source of the HFET 100 and the drain of the MOSFET 200 is unnecessary. Has the advantage of being good. Further, since the MOSFET 200 is vertical, the current density can be increased, so that the area efficiency is further improved.

Embodiment 4 FIG.
FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 5, in the semiconductor device of the first embodiment, the fourth embodiment is such that an avalanche diode 300 having a smaller breakdown voltage than that of the MOSFET 200 is connected in parallel between the source and drain of the MOSFET 200.

The p-type substrate 1 also serves as the anode region of the avalanche diode 300. A region of the silicon substrate 1 excluding a region where the second semiconductor layers (Al _x Ga _{1 -x} N 2, GaN layer 3 and Al _y Ga _{1 -y} N layer 4) are stacked and a region where the MOSFET 200 is formed. A p region 20 for controlling the avalanche voltage is selectively formed in the surface layer. An n ⁺ region 21 that becomes the cathode region of the avalanche diode 300 is formed in a part of the surface layer of the p region 20.

The n ⁺ region 21 is in contact with the cathode electrode 22. The cathode electrode 22 is connected to the short-circuit electrode 12. That is, the cathode of the avalanche diode 300 is short-circuited to the n ⁺ region 7 that becomes the drain region of the MOSFET 200. The anode of the avalanche diode 300 is electrically connected to the source terminal 13 via the source electrode 11 of the MOSFET. FIG. 6 shows an equivalent circuit diagram.

  According to the fourth embodiment, in addition to the same effects as those of the first embodiment, a current flows through the avalanche diode 300 when a voltage exceeding the withstand voltage is instantaneously applied to the MOSFET 200 at one timing of the switching operation. Thus, it is possible to prevent the MOSFET 200 from being damaged by applying a voltage higher than that to the MOSFET 200. Therefore, a highly reliable semiconductor device can be obtained.

Embodiment 5. FIG.
FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment of the present invention. As shown in FIG. 7, in the semiconductor device according to the third embodiment, an avalanche diode 300 having a breakdown voltage smaller than that of the MOSFET 200 is connected in parallel between the source and drain of the MOSFET 200 in the fifth embodiment.

The p region 19 of the MOSFET 200 also serves as the anode region of the avalanche diode 300. A p region 20 for controlling the avalanche voltage is selectively formed in the surface layer of the p region 19 except for the region where the MOSFET 200 is formed. An n ⁺ region 21 that becomes the cathode region of the avalanche diode 300 is formed in a part of the surface layer of the p region 20.

The n ⁺ region 21 is short-circuited to the Al _y Ga _1-y N layer 4 serving as a surface barrier layer (carrier supply layer) of the HFET through the short-circuit electrode 23. Therefore, the cathode of the avalanche diode 300 is short-circuited to the n ⁺ region 7 that becomes the drain region of the MOSFET 200. The anode of the avalanche diode 300 is electrically connected to the source terminal 13 via the source electrode 11 of the MOSFET.

  According to the fifth embodiment, in addition to the same effects as in the third embodiment, the MOSFET 200 can be prevented from being destroyed as in the fourth embodiment, so that a highly reliable semiconductor device can be obtained. As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made.

  As described above, the semiconductor device according to the present invention is useful for a power semiconductor device used for a power conversion device such as an inverter, a power supply device for various industrial machines, an automobile igniter and the like as described above. .

It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 1 of this invention. 1 is a circuit diagram showing an equivalent circuit of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 4 of this invention. FIG. 6 is a circuit diagram showing an equivalent circuit of a semiconductor device according to a fourth embodiment of the present invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st semiconductor layer 2, 3, 4 2nd semiconductor layer 6 Gate electrode of HFET 7, 17, 18, 19 Third semiconductor layer 11 Source electrode of MOSFET 16 Oxide film 100 HFET
200 MOSFET
300 diodes

Claims (5)

  A first semiconductor layer made of silicon or silicon carbide, and a second semiconductor layer formed on a part of the first semiconductor layer and made of a semiconductor material having a wider band gap than silicon, In the first semiconductor layer, a normally-off type insulated gate field effect transistor is formed, and in the second semiconductor layer, a heterojunction field effect transistor capable of current control by a gate electrode is formed, The gate of the heterojunction field effect transistor is electrically short-circuited with the source electrode of the insulated gate field effect transistor, and the source of the heterojunction field effect transistor is electrically shorted with the drain of the insulated gate field effect transistor. A semiconductor device characterized by comprising:   A first semiconductor layer made of silicon, silicon carbide, or sapphire; a second semiconductor layer made of a semiconductor material having a wider band gap than silicon formed on the first semiconductor layer; and A third semiconductor layer made of silicon or silicon carbide is formed on a part of the semiconductor layer with an oxide film interposed therebetween, and the third semiconductor layer has a lateral and normally-off insulated gate field effect. A transistor is formed, and the second semiconductor layer is formed with a heterojunction field effect transistor whose current can be controlled by a gate electrode. The gate of the heterojunction field effect transistor is connected to the insulated gate field effect transistor. Electrically connected to the source electrode, and the source of the heterojunction field effect transistor is connected to the drain of the insulated gate field effect transistor. Wherein a being air shorted.   A first semiconductor layer made of silicon, silicon carbide, or sapphire; a second semiconductor layer made of a semiconductor material having a wider band gap than silicon formed on the first semiconductor layer; and A third semiconductor layer made of silicon or silicon carbide is formed on a part of the semiconductor layer, and a vertical and normally-off insulated gate field effect transistor is formed in the third semiconductor layer. In the second semiconductor layer, a heterojunction field effect transistor capable of current control by a gate electrode is formed, and the gate of the heterojunction field effect transistor is electrically connected to the source electrode of the insulated gate field effect transistor. The source of the heterojunction field effect transistor is electrically shorted with the drain of the insulated gate field effect transistor. Wherein a is.   A diode having a lower withstand voltage than the insulated gate field effect transistor is formed in the first semiconductor layer, and an anode of the diode is electrically short-circuited with a source electrode of the insulated gate field effect transistor, 2. The semiconductor device according to claim 1, wherein a cathode of the diode is electrically short-circuited with a drain of the insulated gate field effect transistor. In the third semiconductor layer, a diode having a lower withstand voltage than the insulated gate field effect transistor is formed, and an anode of the diode is electrically short-circuited with a source electrode of the insulated gate field effect transistor, 4. The semiconductor device according to claim 3, wherein a cathode of the diode is electrically short-circuited with a drain of the insulated gate field effect transistor.

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