JPH08186249A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain a high-performance complementary semiconductor circuit device having a higher-speed characteristic than a silicon complementary circuit device, by simple manufacturing processes and with good reproducibility. CONSTITUTION: A grated Si1-x Gex layer 2 having an increasing Ge composition, an active layer 3 composed mainly of germanium, and a grated Si1-y Gey layer 4 having a reducing Ge composition are provided on a silicon germanium substrate 1, and in its one part region a p-type transistor 7 having a silicon germanium active layer 3 as a channel layer is formed. Along with it, in an adjacent region an n-type transistor 8 is formed in a III-V compound semiconductor active layer 6 provided through the medium of a high-resistance III-V compound semiconductor layer 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a complementary type using a germanium transistor as a p-type transistor and a III-V group compound semiconductor transistor as an n-type transistor. And a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, the basis of silicon semiconductor integrated circuit devices
High-speed performance of complementary circuits that compose this element (basic gate)
Is the characteristic of a p-type transistor with low carrier mobility.
It was limited. For example, the hole mobility of silicon is 50
0 cm²/ V · sec, 1450 cm ²/ V · sec
This is about 1/3 of the electron mobility of
Specifies the characteristics of complementary semiconductor devices using silicon
I was there.

In order to improve the operating speed characteristics in such a silicon semiconductor device, a high-speed semiconductor device using a III-V group compound semiconductor such as HEMT having GaAs as a carrier transit layer has been developed. The electron mobility is 8800 cm ² / V · sec, while the hole mobility is 400 cm ² / V · sec, which is smaller than that of silicon. Therefore, even when GaAs is used, a high-speed complementary circuit is used. I couldn't get it.

On the other hand, germanium is known as a semiconductor having a high hole mobility, and its hole mobility is 180.
It is 0 cm ² / V · sec, which is about four times the hole mobility of silicon. The electron mobility of germanium is 38.
It is 00 cm ² / V · sec.

However, since germanium has various drawbacks such as no stable oxide film, it is not practical to construct a complementary semiconductor device using only germanium. It has also been proposed to use GaAs, which has a large electron mobility, as the type transistor and germanium as the p-type transistor to form a complementary circuit. According to such a proposal, since the driving system in the compound semiconductor integrated circuit device in which the optical element such as OEIC is incorporated in the same substrate is basically the n-type transistor, when the complementary circuit is incorporated in the compound semiconductor integrated circuit device. Is very useful because only the p-type transistor needs to be made of germanium.

In this case, germanium (lattice constant: 5.
6461Å) and GaAs (lattice constant: 5.6533Å)
Has an advantage that the problem of lattice mismatch does not occur when a heterojunction is formed, on the other hand, germanium (Ge) and gallium (Ga) or arsenic (As) has the advantage.
And GaAs act as impurities that determine the conductivity type.
When a germanium layer is epitaxially grown on the substrate, Ga in GaAs is segregated in the germanium layer and p
It is difficult to form an n-type germanium layer having good crystallinity for forming a p-type transistor because it tends to form a p-type transistor, while inter-diffusion occurs when a GaAs layer is grown on a Ge substrate. It was difficult to form a steep heterojunction.

In order to solve the problem of segregation and mutual diffusion, it has been proposed to interpose a silicon layer between germanium and GaAs. (Japanese Patent Publication 5-17514
However, silicon (lattice constant: 5.4309Å) is germanium (lattice constant: 5.6461Å) and GaAs.
Since the lattice constant is significantly different from (lattice constant: 5.6533Å), the problem of lattice mismatch occurs, and the thickness that can be grown on germanium or GaAs without misfit transition, that is, the critical film thickness becomes small. It was not possible to sufficiently suppress interdiffusion and segregation in a silicon layer having a thickness less than the critical thickness.

Further, since the oxide of germanium is water-soluble, when a germanium substrate is used, it is necessary to avoid exposing the germanium to the air in the manufacturing process, and the manufactured semiconductor device is not affected. Since it is necessary to prevent an unstable germanium oxide film from existing, a semiconductor device using only germanium is no longer used except for a special purpose.

Furthermore, as another possibility, silicon germanium (Si) which is a mixed crystal of silicon and germanium is used.
_1-z Ge _z ) has also been studied for a long time, and Si _1-z Ge _z
Proposed to form _z mixed crystal by zone leveling technology (JP Dismukes et al., The Jour.
nal of Physical Chemistry
pvol. 68, No. 10, pp. 3021-302
7, Oct. 1964), and in recent years, this Si _1-z Ge _z mixed crystal was grown by the molecular beam epitaxial growth method (M
Although growing by the BE method) has been studied, no specific proposal has been made. This Si _1-z G
The lattice constant of e _z mixed crystal in the middle of the silicon and germanium, depending on the composition ratio.

[0010]

However, in any case, a high-performance complementary circuit device having higher speed characteristics than the conventional silicon complementary circuit device can be manufactured with a simple manufacturing process and with good reproducibility. It was difficult. Therefore, it is an object of the present invention to obtain a high-performance complementary semiconductor circuit device which has a simple manufacturing process and has high reproducibility and higher speed characteristics than a silicon complementary circuit device.

[0011]

FIG. 1 is a sectional view of a semiconductor device for explaining the principle structure of the present invention. Referring to FIG. 1, the semiconductor device of the present invention comprises a graded Si _1-x Ge _x layer 2 having an increased Ge composition, an active layer 3 containing germanium as a main component, and a Ge on a silicon germanium substrate 1.
A graded Si _1-y Ge _y layer 4 having a reduced composition is provided, and a p-type transistor 7 having the silicon germanium active layer 3 as a channel layer is formed in a partial region thereof, and
At least in a region adjacent to the region where the p-type transistor 7 is provided, a high resistance III-V compound semiconductor layer 5 containing a group V element in an amount of 1 to 2% with respect to the stoichiometric ratio, and a III-V compound A semiconductor active layer 6 is provided, and an n-type transistor 8 having the III-V group compound semiconductor active layer 6 as a channel layer is provided.

The present invention also provides a silicon germanium substrate 1 and graded Si _1-x Ge with an increased Ge composition.
_x layer 2, active layer 3 containing germanium as a main component, and G
e With the graded Si _1-y Ge _y layer 4 whose composition decreases, a misfit transition due to lattice mismatch does not occur G
e compositional relationship.

Further, the present invention is characterized in that the Ge composition of the silicon germanium substrate is set to 0.3 to 0.7. Further, the present invention is characterized in that at least the channel layer of the p-type transistor is germanium, and at least the channel layer of the n-type transistor is GaAs.

Further, the present invention is characterized in that an insulated gate field effect transistor (IGFET) is used as the p-type transistor and a high electron mobility transistor (HEMT) is used as the n-type transistor.

The method of manufacturing a semiconductor device according to the present invention is
On the silicon germanium substrate 1, a graded Si _1-x Ge _x layer 2 having an increased Ge composition, an active layer 3 containing germanium as a main component, and a graded Si _1-y Ge _y layer 4 having a reduced Ge composition. , A high resistance III-V group compound semiconductor layer 5 and a III-V group compound semiconductor active layer 6 in which the group V element is 1 to 2% more than the stoichiometric ratio are provided.
The graded Si in which the Ge composition is reduced by selectively removing the group III compound semiconductor active layer 6 and the high resistance group III-V compound semiconductor layer 5 in which the group V element is 1 to 2% larger than the stoichiometric ratio.
_{The 1-y} Ge _y layer 4 is exposed, the p-type transistor 7 is provided on the exposed region side, and the n-type transistor 8 is provided on the III-V group compound semiconductor active layer 6 side.

[0016]

[Function] FIG. 2 shows the structure of silicon germanium (Si _1-z Ge
It is a figure which shows the correlation of Ge composition z in ( _z ) and a lattice constant, and an effect | action is demonstrated with reference to FIG. See FIG. 2. As shown in FIG. 2, the lattice constant of Si _1-z Ge _z linearly increases with an increase in the composition z of Ge, and pure germanium of x = 1.0 (lattice constant: 5.6461Å) , The lattice constant of GaAs (lattice constant: 5.6533Å)
Almost matches.

Since the present invention uses a silicon-germanium mixed crystal having a lattice constant closer to germanium or GaAs than silicon as a substrate, an active layer containing germanium as a main component and a III-V group compound grown thereon. The problem of lattice mismatch of the semiconductor active layer does not occur, and there is no unstable germanium oxide film as compared with the case where a germanium substrate is used, so that reliability is improved. Further, since the group III element compound semiconductor layer having a high resistance in which the group V element is 1 to 2% larger than the stoichiometric ratio is interposed, the electrical separation between the p-type transistor and the n-type transistor is surely performed. Become.

Further, a graded Si having an increased Ge composition between the substrate and the active layer containing germanium as a main component.
_{Since the 1-x} Ge _x layer is provided, the misfitto transition due to the lattice mismatch does not occur in the active layer containing germanium as a main component and the graded Si _1-y Ge _y layer on which the Ge composition is reduced.

The substrate has a Ge composition of 0.3 to
Since 0.7 germanium is used, the graded Si _{1- y} Ge _y layer for reducing the Ge composition for preventing the interdiffusion can be formed thickly, so that the interdiffusion between Ge and Ga or As can be prevented. This is effectively suppressed, and the crystallinity of the III-V group compound semiconductor layer provided thereon is improved.

An insulated gate field effect transistor (IGFET) is used as the p-type transistor, and a high electron mobility transistor (HEM) is used as the n-type transistor.
By using T), it is possible to form a complementary circuit with a transistor having an established process as a single body and with the same unipolar transistor.

Further, the manufacturing method of the present invention is a high resistance III-element in which the group V element produced by low temperature growth is 1 to 2% larger than the stoichiometric ratio by the conventionally known standardized manufacturing process.
Since the group V compound semiconductor layer growth step is combined, it is possible to manufacture a complementary semiconductor device with a simple manufacturing process and with high reproducibility and faster than the silicon complementary semiconductor device.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 3 to 9 show the manufacturing process of an embodiment of the present invention.
It is a figure explaining. See FIG. 3 (a). First, Si_0.5Ge_0.510 nm Ge on the substrate 11
Graded Si with composition x increasing from 0.5 to 1.0
_1-xGe_xLayer 12, a 30 nm Ge active layer 13, and
The Ge composition y of 30 nm decreases from 1.0 to 0.5
Raised Si _1-yGe_yLayer 14 sequentially, molecular beam epitaxy
It is deposited by the axial growth method (MBE method). this
If the graded Si_1-xGe_xLayer 12 is the same as substrate 1
The lattice mismatch of the Ge active layer 13 and the like provided on the
Acts as a buffer layer.

The Ge composition ratio of the substrate 11 is not limited to 0.5, but may be in the range of 0.3 to 0.7, and the composition x of the graded Si _1-x Ge _x layer 12 may be x.
Can be changed from the composition ratio of the substrate 11 to the composition ratio of the active layer 13, and the layer thickness can be 0 to 100 n.
It may be in the range of m. Further, the Ge active layer 13 is formed of Ge.
The composition may be 90% or more of silicon germanium, and the thickness of the layer may be sufficient to form an active layer, that is, 100 nm or less. Furthermore, the graded Si _1-y Ge _y layer 14 The Ge composition of the surface opposite to the Ge active layer 13 may be 0.3 to 0.7, and the layer thickness may be 100 nm or less.

Next, MBE with a growth temperature of 250 ° C.
After the high resistance GaAs layer 15 is grown by using the
Heat treatment is performed at 600 ° C. for 10 minutes. When such a III-V group compound semiconductor is grown at a temperature lower than the normal growth temperature, a semiconductor layer in which the group V element is 1 to 2% larger than the stoichiometric ratio is obtained. As a result, excessive group V elements are aggregated into particles to form metal particles, and a metal-semiconductor junction (Schottky junction) is formed around the metal particles in the semiconductor layer.
Carriers are depleted to high resistance (Smith et al., IEEE
E ELECTRON DEVICE LETTER
S, EDL9, p. 77, 1988).

In the case of this GaAs layer 15, GaAs
-A metal As Schottky junction is formed and its resistivity is
10^Five-10⁷Ω · cm, p-type transistor and n
Element isolation layer that electrically separates the
It The growth temperature of this GaAs layer is 150 ° C. or higher.
The temperature may be in the range of 450 ° C, and the layer thickness is 100 to 5
It may be in the range of 00 nm. Also, this GaAs layer 1
No. 5 shows that the group V element is 1 to 2% more than the stoichiometric ratio.
It may be a III-V group compound semiconductor layer, for example, AlGaA.
10 for s layer ¹¹It has a resistivity of Ω · cm.

Next, a 50 nm high-purity GaAs layer 1
An n-type Al _0.3 Ga _0.7 As carrier supply layer 17 of 6 and 20 nm and an n-type In _0.3 Ga _0.7 As ohmic contact layer 18 of 10 nm are deposited by the MBE method. In these deposition processes, graded Si _1-y
Since the Ge _y layer 14 acts as an interdiffusion prevention layer that prevents the mutual diffusion of Ge with Ga and As, the quality of the high-purity GaAs layer 6 provided thereon can be kept high.

The layer thickness of the high-purity GaAs layer 16 is 1
It is sufficient if it is about 00 nm, and n-type Al _0.3 Ga _0.7 As
The Al composition ratio a of the carrier supply layer 17 is 0.0 <a ≦ 1.
0 by weight, and its thickness is as long 40nm or less, further, In composition ratio b of the n-type In _{0. 3} Ga _0.7 As ohmic contact layer 18 is 0.0 ≦ b ≦ 1.0
And the layer thickness may be about 100 nm.

Next, as shown in FIG. 3B, H is used with the photoresist pattern 19 as a mask.
_The n-type In _0.3 Ga _0.7 As ohmic contact layer 18 to the high-resistance GaAs layer 15 are selectively etched using a phosphoric acid-based etching solution of ₃ PO ₄ : H ₂ O ₂ : H ₂ O = 1: 1: 25. Remove.

Next, as shown in FIG. 4C, after removing the photoresist pattern, a new
By applying a different photoresist and patterning
Then, a second photoresist pattern 20 is formed.
Oxygen ions are used with the photoresist pattern 20 as a mask.
1 × 10^Fifteencm ^-2Element isolation by ion implantation with a dose of
A region 21 is formed.

Next, as shown in FIG. 4D, after removing the photoresist pattern, a silicon oxynitride film (SiON film) 22 is formed on the entire surface by plasma C.
A third photoresist pattern 23 having an opening corresponding to the gate of the p-type IGFET is formed by depositing by the VD method and then applying and patterning a photoresist.

Next, as shown in FIG. 5E, the third photoresist pattern is used as a mask.
CF_FourAnd O of 3.9% ₂CF consisting of gas_FourUse system gas
The silicon nitride oxide film 2 was formed by dry etching.
2 and graded Si_1-yGe_ySelectively remove layer 14
Then, the Ge active layer 13 is exposed.

Next, referring to FIG. 5F, using the silicon oxynitride film 22 as a mask.
By performing heat treatment for 20 minutes at a substrate temperature of 550 ° C. in an atmosphere of O ₂ : N ₂ = 1: 3, nitriding and oxidation are performed simultaneously, and the Ge active layer 13 and the graded Si _1-y Ge are formed.
_On the exposed surface of the _y- layer 14, a 10-nm-thick nitrided oxide (Ge
_A gate insulating film 24 made of ₂ N ₂ O) is formed. (Note that this nitriding / oxidation process is described in Journal
of Electrochemical Societ
y, vol. 135-4, p. See 961, 1988. The gate insulating film 24 has a layer thickness of 3 to 50 nm.
It should be in the range of.

Next, referring to FIG. 6 (g), Cr and Au are vapor-deposited on the entire surface to form a p-type IGFET.
A Cr / Au layer 25 to be the gate electrode of is formed.

Next, as shown in FIG. 6H, the silicon oxynitride film 22 is HF: H ₂ O = 1: 1.
Then, the Cr / Au layer 25 on the silicon oxynitride film 22 is lifted off to form a gate electrode 26 by removing the second silicon oxynitride film 27 on the entire surface. The second silicon oxynitride is deposited by the plasma CVD method and dry-etched using a CF ₄ gas with a photoresist (not shown) as a mask on the source / drain formation region of the p-type IGFET and on the gate electrode 26. The film 27 is removed.

Next, referring to FIG. 7I, using the second silicon oxynitride film 27 as a mask, B (boron) with a dose amount of 2 × 10 ¹⁴ cm ⁻² is ion-implanted and heat-treated at a temperature of 350 ° C. By p
⁺ Type source / drain regions 28 and 29 are formed.

Next, referring to FIG. 7 (j), a photoresist is applied to the entire surface and patterned to form a fourth photoresist pattern 30 having openings for forming source / drain electrodes, and then Pd (palladium). , Cr, and Au are vapor-deposited to form a Pd / Cr / Au layer 31 to be source / drain electrodes.

Next, referring to FIG. 8 (k), the fourth photoresist pattern is removed to remove Pd / Cr on the fourth photoresist pattern.
/ Au layer is lifted off to source / drain electrodes 32,
After forming 33, a photoresist is applied to the entire surface and patterned to form a fifth photoresist pattern 34 having an opening for forming the gate electrode of the n-type HEMT.

Then, using the fifth photoresist pattern 34 as a mask, the second silicon oxynitride film 27,
Also, the n-type In _0.3 Ga _0.7 As ohmic contact layer 18 is removed by etching to remove n-type Al _0.3 Ga _0.7 As.
After exposing the carrier supply layer 17, n-type HE is formed on the entire surface.
An Al layer 35 to be the MT gate electrode is deposited.

Then, the fifth photoresist pattern is removed to lift off the Al layer on the fifth photoresist pattern to form the gate electrode 36 of the n-type HEMT, and then a new photoresist is formed. A photoresist is applied to the entire surface and patterned to form a sixth photoresist pattern 37 having openings for forming source / drain electrodes of the n-type HEMT, and then Au.Ge, Ni, and Au to be source / drain electrodes by vapor deposition of Au
A Ge / Ni / Au layer 38 is formed.

Next, by removing the sixth photoresist pattern, Au.G on the sixth photoresist pattern is removed.
The e / Ni / Au layer is lifted off to form the source / drain electrodes 39 and 40, and then 1 at a substrate temperature of 450 ° C.
By performing the heat treatment for 0 minutes, the ohmic properties of the source / drain electrodes 32, 33, 39, 40 are enhanced,
A complementary semiconductor device including a p-type germanium IGFET and an n-type GaAs HEMT is completed. The heat treatment temperature in this case may be in the range of 400 ° C to 450 ° C.

Although the n-type HEMT is used as the n-type transistor in the above embodiment, the present invention is not limited to this, and for example, a GaAs MESFET (Schottky barrier gate type field effect transistor) may be used. Further, the material of the n-type transistor is not limited to GaAs, and other III-V group compound semiconductors having high electron mobility may be used.

[0042]

According to the present invention, a p-type silicon germanium transistor having a Ge composition of 90% or more and an n-type III-V transistor are used.
A silicon germanium substrate is used as a growth substrate for forming a group compound semiconductor transistor, and a graded silicon germanium layer having a reduced Ge composition is interposed between an active layer of a p-type transistor and an active layer of an n-type transistor. As a result, misfit transition and mutual diffusion are suppressed, so that a high-quality semiconductor active layer can be obtained, and thereby, a semiconductor device including a complementary circuit excellent in high-speed characteristics can be manufactured with high manufacturing yield. .

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing the basic configuration of the present invention.

FIG. 2 is a diagram showing a correlation between a composition ratio of silicon germanium (Si _1-z Ge _z ) and a lattice constant.

FIG. 3 is a diagram illustrating a manufacturing process up to the middle of an example of the present invention.

FIG. 4 is a drawing for explaining the manufacturing process up to the middle of FIG. 3 and subsequent steps of the embodiment of the present invention.

FIG. 5 is a diagram illustrating a manufacturing process up to the middle of FIG. 4 and subsequent steps of the embodiment of the present invention.

FIG. 6 is a diagram illustrating a manufacturing process up to the middle of FIG. 5 and subsequent steps of the embodiment of the present invention.

FIG. 7 is a diagram illustrating a manufacturing process up to the middle of FIG. 6 and subsequent steps of the embodiment of the present invention.

FIG. 8 is a diagram illustrating a manufacturing process up to the middle of FIG. 7 and subsequent steps of the embodiment of the present invention.

FIG. 9 is a diagram for explaining the manufacturing steps after FIG. 8 of the embodiment of the present invention.

[Explanation of symbols]

1 Silicon-germanium substrate 2 Graded Si _1-x Ge _x layer with increased Ge composition 3 Active layer mainly containing germanium 4 Graded Si _1-y Ge _y layer with reduced Ge composition 5 High resistance III-V group Compound semiconductor layer 6 III-V group compound semiconductor active layer 7 p-type transistor 8 n-type transistor 11 Si _0.5 Ge _0.5 substrate 12 Ge graded Si _1-x Ge _x with increasing composition
Layer 13 Ge Active layer 14 Ge Graded Si _1-y Ge _y with reduced composition
Layer 15 High-resistance GaAs layer 16 High-purity GaAs active layer 17 Al _0.3 Ga _0.7 As layer 18 In _0.3 Ga _0.7 As layer 19 Photoresist pattern 20 Second photoresist pattern 21 Element isolation region 22 Silicon oxynitride film 23 Third layer Photoresist pattern 24 Gate insulating film 25 Cr / Au layer 26 Gate electrode 27 Second silicon oxynitride film 28 Source region 29 Drain region 30 Fourth photoresist pattern 31 Pd / Cr / Au layer 32 Source electrode 33 Drain electrode 34 Fifth photoresist pattern 35 Al layer 36 Gate electrode 37 Sixth photoresist pattern 38 Au.Ge/Ni/Au layer 39 Drain electrode 40 Source electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8238 27/092 27/095 7376-4M H01L 29/80 E

Claims (6)

[Claims] 1. A graded silicon germanium layer having an increased germanium composition, an active layer containing germanium as a main component, and a graded silicon germanium layer having a reduced germanium composition are provided on a silicon germanium substrate, and a partial region thereof is provided. And a p-type transistor having the silicon germanium active layer as a channel layer is formed, and at least the region adjacent to the region where the p-type transistor is provided contains a group V element in a stoichiometric ratio of 1 to 2%. Many III-V compound semiconductor layers and III-V
A semiconductor device comprising a group compound semiconductor active layer, and an n-type transistor having the group III-V compound semiconductor active layer as a channel layer. 2. The silicon germanium substrate, the graded silicon germanium layer having an increased germanium composition, the active layer containing germanium as a main component, and the graded silicon germanium layer having a decreased germanium composition, a lattice. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a Ge composition that does not cause misfit transition due to mismatch. 3. The semiconductor device according to claim 1, wherein the germanium composition of the silicon germanium substrate is 0.3 to 0.7. 4. The germanium-based active layer is a germanium active layer having a germanium composition of 100%, and the III-V compound semiconductor active layer is Ga.
4. The semiconductor device according to claim 1, wherein the semiconductor device is an As active layer. 5. The p-type transistor is an insulated gate field effect transistor, and the n-type transistor is a high electron mobility transistor, according to any one of claims 1 to 4. Semiconductor device. 6. A stoichiometric ratio of a graded silicon germanium layer having an increased germanium composition, an active layer containing germanium as a main component, a graded silicon germanium layer having a decreased germanium composition, and a group V element on a silicon germanium substrate. 1-2% more than III-V
A group III compound semiconductor active layer and a group III-V compound semiconductor active layer are provided, and the group III-V compound semiconductor active layer and the group V element are added by 1 to 2% relative to the stoichiometric ratio. After selectively removing the semiconductor layer to expose the graded silicon germanium layer in which the germanium composition is reduced, a p-type transistor is formed on the exposed region side and an n-type on the III-V group compound semiconductor active layer side is formed. A method of manufacturing a semiconductor device, which comprises forming a transistor.