JP2002134525A - Hetero junction bipolar transistor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed hetero junction bipolar transistor(HBT) of high productivity as well as its manufacturing method. SOLUTION: The hetero junction bipolar transistor comprises an emitter layer 4, a base layer 5, and a collector layer 6. At least one of the emitter layer 4 and the collector layer 6 comprises a semiconductor layer containing aluminum, and a selective oxidation region 3 containing aluminum and a semiconductor region 4 surrounded with it are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a heterojunction bipolar transistor used for ultra-high-speed LSI, ultra-high-speed optical communication, and the like.

[0002]

2. Description of the Related Art A heterojunction bipolar transistor (hereinafter abbreviated as HBT) using a group III-V compound semiconductor has a large current gain and a small base resistance, and can be said to be a transistor suitable for an ultrahigh-speed circuit. In recent reports of optical communication ICs, there are many cases in which HBT is adopted in consideration of the increase in communication speed.

[0003] In order to improve the high-frequency characteristics of the HBT, it is essential to reduce the parasitic junction capacitance and the base resistance between the respective layers, and various measures have been tried so far. For example, as shown in FIG. 9, by increasing the resistance of the external emitter layer 21 by ion implantation, the emitter (4) / base (5) parasitic junction capacitance and base
(5) Collector (6) A collector-up structure with reduced parasitic junction capacitance is widely known.

[0004] Further, this is an improvement of the collector-up structure HBT. As shown in FIG. 10, after selectively increasing the resistance of the emitter layer 4 (23), the external base layer 24 is made to have a high resistance. A structure regrown on the emitter layer 23 is proposed in Japanese Patent Application Laid-Open No. 5-175225.

[0005]

However, these measures have manufacturing problems as described below. Figure
In the ninth example, when the resistance of the external emitter layer 21 is increased by ion implantation, it is performed through the external base layer 22. At this time, a defect occurs in the outer base layer 22 due to the radiation damage, and the base resistance is significantly increased in this state. For this reason, conventionally, after ion implantation, diffusion treatment was performed to increase the surface concentration of the external base layer, or as shown in the example of FIG. 10, the resistance of the emitter layer was increased after removing the external base layer. The base resistance has been reduced by growing the outer base layer 24 again.

However, in these methods, it is difficult to control the diffusion for increasing the surface concentration of the external base layer 22, or the production becomes complicated due to the additional step of regrowing the external base layer 24. There was a problem.

Therefore, the present invention has been made in view of the above problems, and has as its object to provide a high-productivity, high-speed HBT and a method for manufacturing the same.

[0008]

In order to achieve the above object, the HBT of the present invention employs a structure in which an emitter layer or a collector layer is selectively oxidized and has a high resistance from a portion including a mesa side wall. I do. That is, the HBT of the present invention
Is a heterojunction bipolar transistor having an emitter layer, a base layer, and a collector layer, wherein at least one of the emitter layer and the collector layer is made of a semiconductor layer containing aluminum, and has a selective oxidation region containing aluminum. And a semiconductor region surrounded by the selective oxidation region.

[0009] Based on the above basic configuration, the following forms can be adopted. Typically, only the emitter layer is made of a semiconductor layer containing aluminum, and has a selective oxidation region containing aluminum and a semiconductor region surrounded by the selective oxidation region. It also has a collector-up structure. Such a structure can sufficiently exhibit the effect of a structure in which the emitter layer or the collector layer is selectively oxidized from the portion including the mesa side wall to increase the resistance.

[0010] Typically, a structure formed of a III-V group semiconductor is employed. In this case, the base layer and the collector layer
GaAs layer and emitter layer are Al _x Ga _1-x As layer (however, 0 <x ≦ 1)
Alternatively, the base layer and the collector layer can be a GaInAs layer, and the emitter layer can be an AlInAs layer. Further, the Al composition in the vicinity where the emitter layer or the collector layer is in contact with the base layer,
A structure in which carriers are gradually increased from zero in the direction opposite to the base layer can be a structure in which carriers hardly accumulate on the way.

[0011] Further, in order to achieve the above object, the present invention
An HBT manufacturing method is an HBT manufacturing method including an emitter layer, a base layer, and a collector layer, on a semi-insulating semiconductor substrate, an emitter layer containing aluminum of the first conductivity type,
A step of sequentially growing a base layer of the second conductivity type, and a collector layer of the first conductivity type, and partially etching the collector layer by a first mesa etching, thereby forming a collector mesa portion; Exposing the side wall of the collector mesa portion, covering the side wall of the collector mesa with a protective film, and partially etching the base layer and the emitter layer below the collector layer by a second mesa etching. Forming a base mesa portion, exposing at least a sidewall of the base mesa portion, and selectively oxidizing the emitter layer containing aluminum from a portion including the sidewall of the base mesa portion. Or a collector layer containing aluminum of the first conductivity type on a semi-insulating semiconductor substrate. Second conductivity type base layer, and a step of sequentially growing an emitter layer of a first conductivity type, the first
A step of partially etching the emitter layer by a second mesa etching, thereby forming an emitter mesa portion and exposing a side wall of the emitter mesa portion; a step of covering the side wall of the emitter mesa with a protective film; A step of partially etching the base layer and the collector layer below the emitter layer by etching to form a base mesa portion and exposing a side wall of the base mesa portion; And selectively oxidizing the collector layer containing aluminum from a portion containing aluminum (in the case of a method for manufacturing an emitter-up type HBT).

In the above structure, since ion implantation is not used to partially increase the resistance of the emitter layer or the collector layer, a diffusion step and a regrowth step which are difficult to control and increase the number of steps become unnecessary. .

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1, FIG. 2, FIG.
The description will be made based on FIGS. 3, 4, 5, 6, and 7. However, the proportions of the dimensions in the drawings do not always match those described.

First, a manufacturing method will be described. Semi-insulating GaAs base
For the plate 1, Si-doped n
-GaAs emitter contact layer 2 (Si doping concentration: 5 × 10
¹⁸cm^-3) At 600 nm and Si-doped n-AlGaAs emitter layer 4 (Si-doped
Ping concentration: 5 × 10¹⁷cm^-3) At 300 nm, C-doped p-GaAs base
Layer 5 (C doping concentration: 3 × 10¹⁸cm^-3) To 100 nm, Si
N-GaAs collector layer 6 (Si doping concentration: 3 × 10¹⁷cm^-3)
300 nm, Si-doped n-GaAs collector contact layer 7 (Si
Concentration: 5 × 10¹⁸cm^-3) Are sequentially laminated 100 nm, and HBT
Form the structure (FIG. 2).

The Al composition of AlGaAs used for the emitter layer 4 is almost matched in the entire range of composition 0 to 1 in terms of lattice matching with GaAs as the substrate 1. However, the oxidation rate in the selective oxidation performed in the subsequent step largely depends on the Al composition, and the higher the Al composition, the faster the oxidation rate. In this regard, for example, a paper by KDChoquette et al.
[Low threshold voltage vertical-cavity lasers
fabricated by selective oxidation] (Electron.
Lett., 30, 2043, 1994). Therefore, from the viewpoint of productivity, the Al composition of the AlGaAs emitter layer 4 is desirably set to 0.80 or more.

In the above HBT structure, the AlGaAs emitter layer 4 has an Al composition in the vicinity of the base layer 5 in contact with the base layer 5.
The structure may be such that it is gradually increased from zero in the opposite direction. This makes it difficult for carriers to accumulate in this vicinity, which is convenient.

Next, the collector contact layer 7 and the collector layer 6 are removed up to the surface of the base layer 6 by photolithography and wet etching except for a portion to be a collector region, thereby forming a collector mesa (FIG. 3).

Further, the entire semiconductor is subjected to plasma CVD,
A silicon nitride film 25 is deposited to a thickness of 100 nm. Then, the silicon nitride film 25 is removed by lithography and dry etching, leaving the region including the emitter region and the region where the base region and the base electrode 9 are formed. Furthermore, the base layer 5 and the emitter layer 4 are selectively etched by wet etching using the silicon nitride film 25 as a mask.
Remove up to two surfaces to form a base mesa (FIG. 4).

Subsequently, the emitter layer 4 containing aluminum is selectively oxidized from the side wall of the base mesa in a high-temperature steam atmosphere while leaving a portion where the emitter is formed (see the selective oxide layer 3 in FIG. 5). .

After the silicon nitride film 25 is removed, the collector region 6 and the base region 5 are included by photolithography and wet etching for isolation between adjacent elements (adjacent elements are not shown in the drawing), and Except for the portion where the emitter electrode 8 is formed, the emitter contact layer 2
And a part of the substrate 1 is removed. Then, silicon nitride 25 as an element protection film is deposited on the entire surface of the semiconductor by a plasma CVD method (FIG. 6).

Finally, the silicon nitride 25 where the emitter electrode 8, base electrode 9, and collector electrode 10 are to be formed is removed by photolithography and dry etching, and AuGe / Ni / Ti / Pt / Au is deposited by evaporation. After forming the emitter electrode 8, the Ti / Pt / Au base electrode 9, and the AuGe / Ni / Ti / Pt / Au collector electrode 10, an ohmic treatment is performed at 400 ° C. (FIG. 7).

In the step of FIG. 5, only the side wall of the emitter layer is exposed. However, the space between the base layer and the base layer is stepped to expose a part of the upper surface of the emitter layer. The emitter layer may be selectively oxidized. Also, the collector layer may contain Al, the side walls of this layer may be exposed, and an external collector layer having high resistance by selective oxidation may be provided around the collector region.

Thus, the emitter-base parasitic junction capacitance and the base-collector parasitic junction capacitance are reduced, and the base resistance is reduced.
Is produced.

Although the effect of the collector-up HBT is considerably inferior to that of the collector-up HBT, the emitter-up structure HBT also has a high resistance AlGaAs around the collector region on the substrate side by selective oxidation.
By providing the external collector layer, the base-collector parasitic junction capacitance and the emitter-base parasitic junction capacitance are reduced, and an HBT having an emitter-up structure with reduced base resistance can be realized.

(Embodiment 2) FIG. 8 shows Embodiment 2 of the present invention. Again, the proportions of the dimensions in the figures do not always correspond to those described. Further, the manufacturing method is the same as in the first embodiment.

That is, the Si-doped n-GaInAs emitter contact layer 12 (Si doping concentration: 4 × 10 ¹⁸ cm ^-3 ) is formed on the semi-insulating InP substrate 11 by the ordinary metal organic chemical vapor deposition method for 600 n.
m, Si-doped n-AlInAs emitter layer 14 (Si doping concentration: 5
× 10 ¹⁷ cm ^-3 ) to 300 nm, Zn-doped p-GaInAs base layer 15 (Zn
Doping concentration: 8 × 10 ¹⁸ cm ^-3 ) 100 nm, Si-doped n-GaIn
300 n of As collector layer 16 (Si doping concentration: 5 × 10 ¹⁶ cm ⁻³ )
m, a 100 nm thick Si-doped n-GaInAs collector contact layer 17 (Si doping concentration: 1 × 10 ¹⁹ cm ⁻³ ) is sequentially laminated to form an HBT structure. Here, the Al composition of the AlInAs emitter layer 14 is set to 0.47 so as to be lattice-matched to InP as the substrate 11.

Next, the collector contact layer 17 and the collector layer 16 are removed up to the surface of the base layer 15 by photolithography and wet etching except for a portion serving as a collector region, thereby forming a collector mesa. And for the whole semiconductor,
A 100 nm silicon nitride film is deposited by a plasma CVD method. Further, the silicon nitride film is removed by lithography and dry etching, leaving the region including the emitter region and the region where the base region and the base electrode 19 are formed. By wet etching using the silicon nitride film as a mask,
The base layer 15 and the emitter layer 14 are selectively removed to the surface of the emitter contact layer 12 to form a base mesa.

Thereafter, the emitter layer 14 containing aluminum is selectively oxidized from the side wall of the base mesa in a high-temperature steam atmosphere except for a portion where the emitter is formed. After removing the silicon nitride film, the emitter contact layer 12 and the substrate 11 are removed by photolithography and wet etching except for the portion including the collector region and the base region and the portion where the emitter electrode 18 is formed, for isolation between adjacent devices. Remove some of the. Then, silicon nitride as an element protection film is deposited on the entire surface of the semiconductor by a plasma CVD method. Finally, by photolithography and dry etching,
The silicon nitride at the portion where the emitter electrode 18, base electrode 19 and collector electrode 20 are formed is removed, and Ti / Pt /
Au emitter electrode 18, Ti / Pt / Au base electrode 19 and Ti / Pt /
After forming the Au collector electrode 20, an ohmic treatment is performed at 400 ° C.

In this embodiment, the same changes as in the first embodiment can be made.

[0031]

As described above, according to the present invention, by providing a structure in which the emitter layer (or the collector layer) is formed by selective oxidation, a high-productivity, high-speed HBT can be realized. Such an HBT exhibits excellent effects in fields such as ultra-high-speed LSI and high-speed optical communication.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of an HBT according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a process of manufacturing the HBT according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a process of manufacturing the HBT according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a process of manufacturing the HBT according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a process of manufacturing the HBT according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a process of manufacturing the HBT according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a process of manufacturing the HBT according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a structure of an HBT according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view of a conventional collector-up type HBT.

FIG. 10 is a sectional view of a conventional collector-up type HBT.

[Explanation of symbols]

1: Semi-insulating GaAs substrate 2: n ⁺ -GaAs emitter contact layer 3: AlGaAs external emitter layer with high resistance by selective oxidation 4: n-AlGaAs emitter layer 5: p-GaAs base layer 6: n-GaAs Collector layer 7: n ⁺ -GaAs collector contact layer 8, 18: emitter electrode 9, 19: base electrode 10, 20: collector electrode 11: semi-insulating InP substrate 12: n ⁺ -GaInAs emitter contact layer 13: selection AlInAs external emitter layer with high resistance due to oxidation 14: n-AlInAs emitter layer 15: p-GaInAs base layer 16: n-GaInAs collector layer 17: n ⁺ -GaInAs collector contact layer 21: high resistance by oxygen ion implantation AlGaAs external emitter layer 22: Zn diffused p ⁺ -GaAs external base layer 23: AlGaAs external emitter layer with high resistance by oxygen ion implantation 24: Regrown p ⁺ -GaAs external base layer Layer 25: Silicon nitride antinode

Claims (10)

[Claims] 1. A heterojunction bipolar transistor comprising an emitter layer, a base layer, and a collector layer, wherein at least one of the emitter layer and the collector layer comprises a semiconductor layer containing aluminum and contains aluminum. A heterojunction bipolar transistor having a selective oxidation region and a semiconductor region surrounded by the selective oxidation region. 2. The heterojunction bipolar transistor according to claim 1, wherein only the emitter layer is formed of a semiconductor layer containing aluminum, and has a selective oxidation region containing aluminum and a semiconductor region surrounded by the selective oxidation region. Transistor. 3. The method according to claim 1, which has a collector-up structure.
2. The heterojunction bipolar transistor according to 2. 4. The heterojunction bipolar transistor according to claim 1, wherein the heterojunction bipolar transistor is formed of a III-V group semiconductor. 5. The device according to claim 4, wherein the base layer and the collector layer are GaAs layers, and the emitter layer is an Al _x Ga _{1 -x} As layer (where 0 <x ≦ 1).
A heterojunction bipolar transistor as described in claim 1. 6. The heterojunction bipolar transistor according to claim 5, wherein 0.8 ≦ x. 7. The heterojunction bipolar transistor according to claim 4, wherein the base layer and the collector layer are GaInAs layers, and the emitter layer is an AlInAs layer. 8. The emitter layer or the collector layer has a structure in which the Al composition near the base layer is gradually increased from zero in a direction opposite to the base layer. A heterojunction bipolar transistor according to claim 1. 9. A method of manufacturing a heterojunction bipolar transistor (HBT) including an emitter layer, a base layer, and a collector layer, the method comprising: forming an emitter layer containing aluminum of a first conductivity type on a semi-insulating semiconductor substrate. A step of sequentially growing a base layer of the second conductivity type, and a collector layer of the first conductivity type, and partially etching the collector layer by a first mesa etching, thereby forming a collector mesa portion Exposing a sidewall of the collector mesa portion, covering the sidewall of the collector mesa with a protective film, and partially etching the base layer and the emitter layer below the collector layer by a second mesa etching. Forming a base mesa portion and exposing at least a side wall of the base mesa portion; and forming aluminum from a portion including the side wall of the base mesa portion. Method of manufacturing a heterojunction bipolar transistor, which comprises a step of selectively oxidizing the emitter layer comprising, a. 10. A method for manufacturing a heterojunction bipolar transistor (HBT) including an emitter layer, a base layer, and a collector layer, the method comprising: forming a collector layer containing aluminum of a first conductivity type on a semi-insulating semiconductor substrate. A step of sequentially growing a base layer of the second conductivity type and an emitter layer of the first conductivity type, and partially etching the emitter layer by a first mesa etching, thereby forming an emitter mesa portion. Exposing the side wall of the emitter mesa portion, covering the side wall of the emitter mesa with a protective film, and partially etching the base layer and the collector layer below the emitter layer by a second mesa etching. Forming a base mesa portion and exposing a side wall of the base mesa portion, and including aluminum from a portion including the side wall of the side wall of the base mesa portion. Selectively oxidizing the collector layer.