JP3127863B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly, to a Schottky gate field effect transistor excellent in high frequency performance and a method of manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device excellent in high-frequency performance, for example, a Schottky gate field effect transistor (FET) using a heterojunction of a group III-V compound semiconductor is known.
It is widely used in satellite communication, mobile communication and microwave backbone communication, and is required not only to improve its high-frequency performance but also to have high operation stability.

Recently, GaAs has been lattice-matched to an InP substrate.
In _y Ga _1-y As which is more excellent in high frequency characteristics than material
An FET using a layer (0 <y <1) as a channel layer has been proposed.

The FET described in Japanese Patent Application Laid-Open No. 04-208537 will be described below with reference to FIG. The FET is, In _Z Al _1-Z on a semi-insulating InP substrate 51
A superlattice in which AlAs thin films and InAs thin films are alternately laminated on an In _y Ga _1-y As channel layer 53 formed via an As layer 52 (hereinafter referred to as an AlAs / InAs superlattice. Are also described in the same manner.) 54, and the AlAs /
The current between the source electrode 55 and the drain electrode 56 is controlled by the gate electrode 57 on the InAs superlattice 54. By changing the thickness ratio between the AlAs thin film and the InAs thin film of the AlAs / InAs superlattice, the AlAs / I
The thickness of the AlAs thin film is increased toward the upper layer of the nAs superlattice.
The thickness of the As thin film is set to be thin to reduce the leakage current value of the gate electrode.

[0005]

However, the aforementioned A
In the conventional FET having the lAs / InAs superlattice immediately below the gate electrode, during the manufacturing process of the FET (from the state shown in FIG. 5, a protective film is further formed and a contact hole is formed to form a source wiring, a drain wiring, In the step of forming the gate wiring, the thin InAs thin film on the outermost surface of the AlAs / InAs superlattice between the gate electrode and the source electrode and between the gate electrode and the drain electrode is removed, and the AlAs thin film is exposed and oxidized. Then, oxygen enters the AlAs / InAs superlattice from the surface through the thin InAs thin film, oxidation of the AlAs thin film near the surface progresses, and the variation in element performance becomes large. In addition, during the energization of the device (during operation), the oxidation of the AlAs thin film near the surface of the AlAs / InAs superlattice between the gate electrode and the source electrode and between the gate electrode and the drain electrode progresses, and the long-term There has been a problem that characteristic fluctuation which is a problem in reliability occurs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a field effect transistor which prevents oxidation of an AlAs thin film of an AlAs / InAs superlattice during the manufacturing process and operation, and has a further improved reliability, and a method of manufacturing the same.

[0007]

According to the first field effect transistor of the present invention, an AlAs thin film (or InAs thin film) and an IAs thin film are used.
nAs thin films (or AlAs thin films) are alternately stacked, and the thickness t1 _k (k = 1, 2,...) of the adjacent AlAs thin films
.., n) and the thickness t2 _k (k = 1, 2) of the InAs thin film
(2,..., N) in a field-effect transistor having an AlAs / InAs superlattice having a structure in which the ratio t2 _k / t1 _k is constant or decreased toward the upper layer immediately below the Schottky junction gate electrode. The AlAs / AlAs / excluding portions of the lattice that are in contact with the gate electrode and portions that are in contact with the source and drain electrodes, respectively.
It is that the InAs superlattice surface is nitrided.

According to the first method of manufacturing a field effect transistor of the present invention, a buffer layer, a channel layer and an Al layer are formed on a semiconductor substrate.
As thin film (or InAs thin film) and InAs thin film (or A
1As thin film) alternately, and the adjacent AlAs
The thickness t1 _k (k = 1, 2,..., N) of the thin film and I
An AlAs / InAs superlattice having a structure in which the ratio t2 _k / t1 _k of the thickness t2 _k (k = 1, 2,..., n) of the nAs thin film is constant or decreases toward the upper layer is sequentially formed. Providing a crystal substrate, and the AlAs / InA
selectively forming a predetermined metal film on the surface of the s superlattice, performing a heat treatment to form a source electrode and a drain electrode disposed opposite to each other, and forming AlAs / InAs between the source electrode and the drain electrode. The method includes a step of forming a gate electrode forming a Schottky junction on the surface of the superlattice, and a step of nitriding an AlAs / InAs superlattice surface on which the gate electrode is not provided. In this case, the AlAs / InAs superlattice surface can be nitrided in nitrogen plasma generated using ammonia gas. Further, the semiconductor substrate is a semi-insulating InP substrate, the buffer layer is an In _z Al _{1 -z} As layer (0 <z <1), and the channel layer is an n-type In _y Ga _{1 -y} As layer (0 <y <1). can do.

According to the second field effect transistor of the present invention, A
1As thin films (or InAs thin films) and InAs thin films (or AlAs thin films) are alternately stacked,
s thin film having a film thickness _{t1 k (k = 1,2, ···} , n) and the thickness of the InAs thin film _{t2 k (k = 1,2, ···} , n)
In the field effect transistor having the AlAs / InAs superlattice having a structure in which the ratio t2 _k / t1 _k is constant or decreased toward the upper layer immediately below the Schottky junction gate electrode, the AlAs /
On the InAs superlattice, an In _x Al _1-x As layer (0 <x <
1). In this case, it is preferable that the In composition ratio x be 0.52 ≦ x <1.

According to a second method of manufacturing a field effect transistor of the present invention, a buffer layer, a channel layer and an Al layer are formed on a semiconductor substrate.
As thin film (or InAs thin film) and InAs thin film (or A
1As thin film) alternately, and the adjacent AlAs
The thickness t1 _k (k = 1, 2,..., N) of the thin film and I
An AlAs / InAs superlattice having a structure in which the ratio t2 _k / t1 _k of the thickness t2 _k (k = 1, 2,..., n) of the nAs thin film is constant or decreases toward the upper layer is sequentially formed. Providing a crystal substrate, and the AlAs / InA
An In _x Al _1-x As layer (0 <x <1) and a one conductivity type In _w Ga _1-w As layer (0 <w <1) are sequentially deposited on the s superlattice, and the one conductivity type In _w Ga Selectively removing the _1-w As layer to form a recess exposing the surface of the In _x Al _1-x As layer; and interposing the recess with the one conductivity type In _w Ga _1-w As. Forming a source electrode and a drain electrode in ohmic contact with the respective layers; removing the In _x Al _1-x As layer of the recessed portion by lithography to expose the AlAs / InAs superlattice surface; Forming a gate electrode forming a Schottky junction by a lift-off method. In this case, the semiconductor substrate is a semi-insulating InP substrate, the buffer layer is an In _z Al _1-z As layer (0 <z <1), and the channel layer is an n-type In _y Ga _1-y As layer (0 <y <1). ). Further, it is preferable that the In composition ratio x be set to 0.52 ≦ x <1.

An AlAs thin film (or InAs thin film) and In
Al with alternately laminated As thin film (or AlAs thin film)
After the gate electrode is formed on the As / InAs superlattice, the AlAs thin film and the InAs thin film in the AlAs / InAs superlattice near the crystal surface are nitrided to form a nitride layer. Therefore, oxygen enters from the surface to form the AlAs thin film. Prevent oxidation.

Or, an AlAs thin film (or InAs thin film)
And InAs thin film (or AlAs thin film) are alternately laminated on an AlAs / InAs superlattice and In _x Al _1-x As
A layer (0 <x <1) is formed to prevent the AlAs thin film from coming directly to the surface. The In _x Al _{1 -x} As layer is partially removed by forming a recess, and a gate electrode is formed in the recess.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. 1 (a) and 1 (b).

The FET of this embodiment has a semi-insulating In
Undoped In _z A as a buffer layer on a P substrate 1
l _1-z As layer 2 (0 <z <1), n-type In _y Ga _1-y As layer 3 (0 <y <1) as a channel layer, and an undoped InAs thin film and an AlAs thin film are alternately laminated. Al
It has a semiconductor crystal substrate on which an As / InAs superlattice 4 is formed, and has an n-type In _y Ga _1-y As on this semiconductor crystal substrate.
Source electrode 5 and drain electrode 6 in ohmic contact with layer 3
Between the above-described AlAs / InAs superlattice 4 and the In of the n-type In _y Ga _1-y As layer 3 which is a Schottky channel layer.
A composition ratio y of about 0.53 is usually used, and is lattice-matched with the InP substrate.

The AlAs / InAs superlattice 4 is formed by alternately stacking a large number of AlAs thin films and InAs thin films.
_The first AlAs thin film 11 _{1 in} contact with the _y Ga _1-y As layer 3
Thickness t1 ₁ the ratio t2 ₁ / t1 ₁ of thickness t2 ₁ of InAs thin film 10 ₁ in contact with AlAs film 11 _1, an In _y G
t2 ₁ / t1 ₁ = so as to lattice-match with the a _1-y As layer.
0.52 / 0.48 = 1.08 as close as possible.
Further, t1 ₁ and t2 ₁ are made as small as possible below the critical film thickness so that dislocation defects do not occur at the respective semiconductor heterojunction interfaces. AlAs thin film 11 thereon
₂ (thickness t1 ₂ ) and InAs thin film 10 ₂ (thickness t2 ₂ )
With respect to ( ₂₎ , t2 ₂ / t1 ₂ is made smaller than 1.08. Thus, the ratio t2 _k / t1 _k of the thickness t2 _k thickness t1 _k and InAs thin film of the k-th AlAs films, k
, Becomes larger as 1, 2, 3,..., N and gradually decreases in order. t1 _k + t2 _k is constant, t1 _k , t
_2k is made as small as possible below the critical film thickness so that dislocation defects do not occur at the interface of each semiconductor heterojunction.

The surface of the AlAs / InAs superlattice 4 between the source electrode 5 and the gate electrode 7 and between the drain electrode 6 and the gate electrode 7 is nitrided and covered with a nitride layer 8 of the AlAs / InAs superlattice. . During the nitriding, As escapes from the vicinity of the surface to the outside of the semiconductor and is replaced by N, so that a nitride film (Al—In—N film) mainly composed of aluminum nitride and indium nitride is formed on the surface of the nitride layer 8. Is done. This Al—In—N film is dense and can prevent oxidation from the surface of the AlAs / InAs superlattice 4.

Further, a silicon nitride film or a silicon oxide film is deposited by a CVD method to form a passivation film 9 covering the entire device surface.

In the field effect transistor of the present embodiment, the surface of the AlAs / InAs superlattice 4 other than the electrode portion is nitrided as described above, so that the AlAs
/ InAs superlattice 4 (especially AlAs thin film) is prevented from being oxidized. That is, for example, when the passivation film 9 is formed by the CVD method, the oxidation of the AlAs / InAs superlattice 4 (particularly, the AlAs thin film) is prevented.

Next, a second embodiment of the present invention will be described with reference to FIGS. 3 (a) and 3 (b).

The FET of this embodiment has a semi-insulating In
On the P substrate 1, an undoped an In _Z A as a buffer layer
l _1-Z As layer 2 (0 <z <1), n-type In _y Ga _1-y As layer 3A (0 <y <1) as a channel layer, and undoped AlAs thin film and InAs thin film are alternately laminated. A
a semiconductor crystal substrate on which an lAs / InAs superlattice 4 is formed, and an undoped I
An _nx Al _1-x As layer 31 (0 <z <1) and an n-type In _w Ga _1-w As layer 32 (0 <w <1) as a cap layer are grown epitaxially. Also, n-type In _w Ga
_A source electrode 5A and a drain electrode 6A that form ohmic contact with the _1-w As layer 32 are formed, and a recess 3 is formed therebetween.
3 is formed, and In _x Al _{1 -x} A at the bottom of the recess 33 is formed.
AlAs / In exposed by selectively removing the s layer 31
Gate electrode 7A forming Schottky junction with As superlattice 4
Are formed. Al in areas other than Schottky junction
As / InAs superlattice 4 is undoped In _x Al _1-x
The As layer 31 is covered.

As in the first embodiment, the In composition ratio y of the n-type In _y Ga _{1 -y} As layer 3 which is the channel layer of the FET is usually about 0.53. Lattice matching.

Similarly to the first embodiment, the AlAs / InAs superlattice 4 is also formed by laminating a large number of AlAs thin films and InAs thin films alternately, and the first AlAs thin film in contact with the In _y Ga _1-y As layer 3A. 11 ₁ thickness t1 ₁ and AlA
s film 11 ₁ in contact with the InAs thin film 10 ₁ thickness t2 ₁
The ratio t2 ₁ / t1 ₁ is set to t2 ₁ / t1 ₁ = 0.52 / 0.48 so as to lattice match with the In _y Ga _{1 -y} As layer 3A.
= 1.08 as close as possible. Further, t1 ₁ , t2
_In order to prevent dislocation defects from occurring at the interface between the respective semiconductor heterojunctions, the thickness 1 should be as small as possible below the critical film thickness. The upper layer of AlAs film 11 ₂ (thickness t1 ₂₎ and I
For the nAs thin film 10 ₂ (thickness t2 ₂ ), t2 ₂
/ T1 ₂ is made smaller than 1.08. Thus, the thickness t1 _k of the k-th AlAs thin film and the thickness t1 of the InAs thin film
The ratio t2 _k / t1 _k and 2 _k is, k is 1, 2, 3, ...
, N and gradually decrease gradually.
t1 _k + t2 _k is constant, and t1 _k and t2 _k are made as small as possible below the critical film thickness so as not to generate dislocation defects at the respective semiconductor heterojunction interfaces.

The undoped In _x Al _{1 -x} As layer 31 on the AlAs / InAs superlattice 4 has an In composition ratio x = x
0.52, the In composition ratio of the n-type In _w Ga _{1 -w} As layer 32 is set to about w = 0.53, and lattice matching is performed as much as possible with the InP substrate.

The passivation film 9 has a silicon nitride film or a silicon oxide film formed by a CVD method.

In the field effect transistor of the second embodiment, as described above, the AlAs / I
The nAs superlattice 4 is an undoped In _w Al _{1 -w} As layer 3
1 to prevent the superlattice 4 (especially an AlAs thin film) from being oxidized during the heat treatment during the manufacturing process.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described along with its manufacturing steps.

[0027] First, as shown in FIG. 2 (a), a semi-insulating InP substrate, 0.2Myuemu～2myuemu, the undoped as a buffer layer for example 1μm thick In _Z Al _1-Z As
A layer 2 is formed and a channel layer of the FET is formed to a thickness of 10 nm to 3 nm.
Ge-doped n-type In _{y having} a thickness of 0 nm, for example, 20 nm
Ga _1-y As layer 3 (Ge doping concentration is 2 × 10 ¹⁸ c
m ⁻³ and y are set to 0.53 so as to lattice-match with the InP substrate.
Set to. ) To form an AlAs / InAs superlattice 4
A semiconductor crystal substrate (thickness: 50 nm) epitaxially grown by molecular beam epitaxy (MBE) is prepared. A
The lAs / InAs superlattice 4 is formed by alternately stacking a large number of AlAs thin films and InAs thin films, and has an n-type In _y Ga _1-y
The thickness t1 of the first AlAs thin film 11 _{1 in} contact with the As layer 3
InAs thin film 10 in contact with ₁ and its AlAs thin film 11 ₁
The ratio t2 ₁ / t1 ₁ of thickness t2 ₁ of _1, n-type an In _y Ga
T2 ₁ / t1 ₁ = 5 so as to lattice match with the _1-y As layer.
2 nm / 4.8 nm = 1.08. k-th AlA
The ratio t2 _k / t1 _k of the thickness t1 _k and thickness t2 _k of InAs thin s films, sequentially gradually decreases with k is 1, 2, 3, increases ..., a n, gate 0.06 (n = 5) at the uppermost portion in contact with the electrode, and t1 _k + t2 _k is 1
It was fixed at 0 nm.

Next, as shown in FIG. 2B, a desired resist film pattern (having openings on the source electrode forming region and the drain electrode forming region, respectively) (not shown) is formed by optical exposure lithography. AuGe (150 nm) / Ni (4 nm) is formed on the AlAs / InAs superlattice 4.
0 nm) After lift-off after film formation by vacuum evaporation,
The source region 5 and the drain region 6 forming an ohmic junction with the AlAs / InAs superlattice 4 are formed by alloying by heat treatment at 450 ° C. for 2 minutes in a hydrogen atmosphere.

Then, after forming a resist film pattern (not shown) having an opening on the gate electrode formation region by electron beam lithography, AlAs is deposited and lifted off by AlAs.
A gate electrode 7 forming a Schottky junction with the / InAs superlattice 4 is formed. The gate length was 0.2 μm.

After forming the gate electrode 7, the source electrode 5, and the drain electrode 6, the nitride layer 8 having a thickness of about 3 nm is formed by heating at 300 ° C. for 10 minutes in a nitrogen plasma generated by using an ammonia gas. The resulting AlAs / InAs superlattice 4 is obtained. Between the source electrode 5 and the gate electrode 7,
And AlAs / gap between the gate electrode 7 and the source electrode 5.
The surface of the InAs superlattice 4 is covered with a nitride layer 8 obtained by nitriding the surface of the AlAs / InAs superlattice with nitrogen plasma. When nitriding, As escapes from near the surface to the outside of the semiconductor and N
On the surface of the nitride layer 8, a nitride film (Al—In—) mainly composed of aluminum nitride and indium nitride is formed.
N film) is formed. This Al-In-N film is dense and
Oxidation from the surface of the lAs / InAs superlattice 4 can be prevented.

Further, as in the prior art, a silicon nitride film (not shown) having a thickness of 100 nm is formed as a passivation film by a plasma CVD method, and openings are provided to form a source electrode wiring, a drain electrode wiring, and a gate electrode wiring.

In the field effect transistor of this embodiment, as described above, the AlAs / InAs
The surface is nitrided, and AlAs / In
The oxidation of the As superlattice 4 (especially the AlAs thin film) is prevented.
That is, for example, when the passivation film 9 is formed by the CVD method, the AlAs / InAs superlattice 4 (particularly, Al
(As thin film) is prevented from being oxidized.

In the FET of this embodiment, the gate leakage current is 1 × 10 ⁻¹ to 1 when a gate bias voltage of +0.5 V is applied.
× 10 ⁻² A / cm ^−2, which is about the same as the gate leakage current value of the conventional FET, and the conventional AlAs / In
It has been found that FETs with As superlattices have excellent electrical properties.

In addition, the problem of the conventional FET having the AlAs / InAs superlattice did not occur. That is, during the manufacturing process, the thin IAs on the outermost surface of the AlAs / InAs superlattice
The nAs thin film is removed and the AlAs thin film is exposed and oxidized, or oxygen enters the AlAs / InAs superlattice from the surface through the thin InAs thin film, and the oxidation of the AlAs thin film near the surface proceeds. Did not. In addition, oxidation of the AlAs thin film in the AlAs / InAs superlattice progressed during energization of the device, and there was no problem in device reliability such as long-term fluctuation of drain current.

A second embodiment of the present invention will be described along with its manufacturing steps.

As in the case of the first embodiment, FIG.
As shown in, on a semi-insulating InP substrate 1, to form a thickness of 0.2μm~2μm as a buffer layer, for example, of 0.5μm undoped a In _Z Al _1-Z As layer 2, FET
As a channel layer having a thickness of 10 nm to 30 nm, for example,
Ge-doped n-type In _y Ga _{1-y with} a thickness of about 15 nm
As layer 3A (Ge doping concentration is 2 × 10 ¹⁸ cm ⁻³ ,
y is set to 0.53 so as to lattice-match with the InP substrate. ) To form an AlAs / InAs superlattice 4 (thickness 5
(0 nm) is prepared by the MBE method.

The AlAs / InAs superlattice 4 is made of AlAs
A thin film and a plurality of InAs thin films are alternately laminated, and as shown in FIG. 3B, an n-type In _y Ga _1-y As layer 3A is formed.
Initial thickness tl ₁ the ratio t2 ₁ / t1 ₁ of thickness t2 ₁ of InAs thin film 10 ₁ in which the contact with the AlAs film 11 ₁ of the AlAs film 11 ₁ in contact with the, n-type In _y Ga _1-y As
T2 ₁ / t1 ₁ = 0.52 so as to lattice-match with layer 3A
/0.48=1.08 as close as possible. Further, t
Each of ₁₁ and t2 ₁ is approximately equal to or less than a critical film thickness of 4 nm or less so that dislocation defects do not occur at each semiconductor heterojunction interface.
8 nm and 5.2 nm. Thereafter, the upper layer Al
As thin film 11 _k (k = 2, 3,..., N) and InAs
When the thin film 10 _k (k = 2, 3,..., N) is divided into two adjacent layers in this order, the sum of the thicknesses of the two layers (11 _k +10 _k ) is about 10 nm, and t2 _k /
As t1 _k increases (k increases), it gradually decreases, and finally, at the uppermost portion in contact with the gate electrode, t2 _n /
The AlAs thin film and In are so set that t1 _n = 0.06.
As thin films were laminated. In this embodiment, n = 5.

Further, a thickness of 10 nm to 20 nm, for example,
Undoped I lattice-matched to 15 nm InP substrate 1
n _x Al _1-x As layer 31 and the (x = 0.52), the thickness 20nm~100nm as a cap layer, for example, 30 nm
The n-type In _w Ga _{1 -w} As layer 32 (w = 0.53) is epitaxially grown.

Next, as shown in FIG. 4B, the n-type In _w Ga _{1 -w} As layer 32 is changed to H by i-line lithography.
The recess 33 is removed by plasma etching using Br gas to form a recess 33 having a width of 0.6 μm. Next, FIG.
As shown in FIG. 5, a source electrode 5A and a drain electrode 6A made of an AuGe alloy film and a Ni film are formed. Next, a resist film 34 having an opening 35 having a width of 0.2 μm is formed by electron beam lithography. Next, as shown in FIG. 5A, using the resist film 34 as a mask, the undoped In _x Al _{1 -x} As layer 31 is removed using an aqueous solution of phosphoric acid and hydrogen peroxide. At this time, some side etching occurs.

Next, as shown in FIG. 5B, a Ti film (20 nm), a Pt film (100 nm) and an Au film (20 nm) are formed.
0 nm) in this order to form a gate metal film 36. The above-described opening 35 is partially filled and a gate metal film 36 separated from the surface portion of the resist film 34.
(7A) is formed. Next, the resist film 34 is removed. As described above, the gate electrode 7A forming a Schottky junction with the AlAs / InAs superlattice 4 is formed by the lift-off method as shown in FIG. Here, the gate electrode is formed using the resist film 34 for etching the undoped In _x Al _{1 -x} As layer 31 as it is, but after removing the resist film 34, the exposed A
lAs / InAs superlattice 4 and its surrounding In _x Al
A resist film having an opening may be formed on the _1-x As layer 31 and a gate electrode may be formed by a lift-off method.
Note that the gate electrode is not in contact with the n-type In _w Ga _{1 -w} As layer 32. Next, a silicon oxide film having a thickness of 100 nm is formed as a passivation film 6 by a CVD method, and openings (not shown) reaching the source electrode 5A, the drain electrode 6A, and the gate electrode 7A are provided. A gate electrode wiring is provided.

In the field-effect transistor according to the second embodiment, as described above, AlAs /
Almost the entire surface of the InAs superlattice 4 is undoped In _x Al.
_The AlAs / InAs superlattice 4 (especially an AlAs thin film) is prevented from being oxidized during the heat treatment during the manufacturing process because it is covered by the _1-x As layer 31.

In the FET of this embodiment, the gate leakage current is 1 × 10 ^-1 to 1 when a gate bias voltage of +0.5 V is applied.
× 10 ⁻² A / cm ^−2, which is about the same as the gate leakage current value of the conventional FET.
The effect of the As superlattice was observed.

Further, the problem of the conventional FET having the AlAs / InAs superlattice did not occur. That is, the AlAs / InAs superlattice is oxidized during the manufacturing process, or oxygen enters from the surface into the AlAs / InAs superlattice, and the oxidation of the layer near the AlAs / InAs superlattice surface occurs. Did not. In addition, oxidation of the AlAs thin film in the AlAs / InAs superlattice progressed during energization of the device, and there was no problem in device reliability such as long-term drain current fluctuation.

The case where t2k / t1k is changed has been described above. However, there is an effect even when it is constant at 1.08. Needless to say, when the surface of the AlAs / InAs superlattice is nitrided, In is more stable than a superlattice containing AlAs that is chemically unstable and easily oxidized.
_This is because it is harder to oxidize when coated with the xAl _1-x As layer (mixed crystal).

As described above, in the first embodiment, the second embodiment, the first embodiment, and the second embodiment, the InAs thin film is deposited on the AlAs thin film.
It is apparent that the AlAs thin film may be deposited on the As thin film without further detailed explanation.

[0046]

The effect of the present invention is as follows.
By preventing the oxidation of the AlAs thin film of the lAs / InAs superlattice, suppressing the oxidation of the AlAs thin film during energization, reducing variations in device performance during the device manufacturing process, and obtaining long-term stability of device characteristics. is there.

The reason is that after forming the gate electrode of the conventional FET, the AlAs thin film and the InAs thin film in the AlAs / InAs superlattice near the crystal surface are nitrided to form a nitride film (Al-In-N film). Form and stabilize the crystal surface. This Al—In—N film is stable and dense, and prevents oxygen from entering from the surface to prevent oxidation of the AlAs thin film.

Alternatively, by changing the crystal structure of the conventional FET, forming an In _x Al _{1 -x} As layer lattice-matching with the InP substrate on the AlAs / InAs superlattice so that the AlAs thin film directly comes out on the surface. To prevent This In _x Al
_{The 1-x} As layer is partially removed by forming a recess, and a gate electrode is formed in the opening. In _x Al _1-x As
The layer is usually stable during the device manufacturing process or during device energization, and can prevent oxidation of the AlAs thin film.

[Brief description of the drawings]

FIG. 1 is a sectional view of an FET chip for explaining a first embodiment and a first example of the present invention (FIG. 1);
(A)) and an enlarged sectional view of the AlAs / InAs superlattice portion (FIG. 1 (b)).

FIGS. 2A to 2C are cross-sectional views illustrating a first embodiment of the present invention in the order of steps, which are separately illustrated in FIGS.

FIG. 3 is a sectional view of an FET chip for describing a second embodiment and a second example of the present invention (FIG. 3);
(A)) and an enlarged sectional view of the AlAs / InAs superlattice portion (FIG. 3 (b)).

FIGS. 4A to 4C are cross-sectional views in the order of steps for explaining the second embodiment of the present invention along the manufacturing steps.

FIG. 5 is a sectional view in the order of steps, which is shown separately in FIGS.

FIG. 6 is a sectional view of an FET chip for describing a conventional example.

[EXPLANATION OF SYMBOLS] 1 semi-insulating InP substrate 2 In _Z Al _1-Z As layer (buffer layer) 3, 3A n-type In _y Ga _1-y As layer (channel layer) 4 AlAs / InAs superlattice 5,5A the source electrode 6,6A drain electrode 7,7A gate electrode 8 nitride layer 9 passivation film _{10 1, 10 2, ···,} 10 n InAs thin film _{11 1, 11 2, ···,} 11 n AlAs film 31 undoped in _x Al _{1 -x} As layer 32 n-type In _w Ga _{1 -w} As layer 33 recess 34 resist film 35 opening 36 gate metal film 51 semi-insulating InP substrate 52 In _Z Al _{1 -Z} As layer (buffer layer) 53 In _y Ga _1-y As layer (channel layer) 54 AlAs / InAs superlattice 55 source electrode 56 drain electrode 57 gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/201 H01L 29/812 H01L 29/872

Claims (9)

(57) [Claims] 1. An AlAs thin film (or InAs thin film) and I
nAs thin films (or AlAs thin films) are alternately stacked, and the thickness t1 _k (k = 1, 2,...) of the adjacent AlAs thin films
.., n) and the thickness t2 _k (k = 1, 2) of the InAs thin film
(2,..., N) in a field-effect transistor having an AlAs / InAs superlattice having a structure in which the ratio t2 _k / t1 _k is constant or decreased toward the upper layer immediately below the Schottky junction gate electrode. The AlAs / AlAs / excluding portions of the lattice that are in contact with the gate electrode and portions that are in contact with the source and drain electrodes, respectively.
A field-effect transistor, wherein an InAs superlattice surface is nitrided. 2. A buffer layer, a channel layer and an AlAs thin film (or an InAs thin film) and an InAs thin film (or an AlAs thin film) are alternately stacked on a semiconductor substrate, and a film thickness t1 _k (k = 1) of the adjacent AlAs thin films is stacked. , 2, ..., n)
And the thickness t2 _k (k = 1, 2,...) Of the InAs thin film
., N) a step of sequentially forming an AlAs / InAs superlattice having a structure in which the ratio t2 _k / t1 _k is constant or decreasing toward the upper layer to prepare a semiconductor crystal substrate;
selectively forming a predetermined metal film on the surface of the s / InAs superlattice and performing a heat treatment to form a source electrode and a drain electrode disposed opposite to each other; and forming an AlAs between the source electrode and the drain electrode. Forming a gate electrode forming a Schottky junction on the surface of the / InAs superlattice;
AlAs / InAs without the gate electrode
Nitriding the surface of the superlattice. 3. The Al / As superlattice surface is nitrided in a nitrogen plasma generated using ammonia gas.
A method for manufacturing the field-effect transistor according to the above. 4. A semiconductor substrate is a semi-insulating InP substrate, a buffer layer is an In _z Al _{1 -z} As layer (0 <z <1), and a channel layer is an n-type In _y Ga _{1 -y} As layer (0 <y). 4. The method for manufacturing a field-effect transistor according to claim 2, wherein <1) is satisfied. 5. An AlAs thin film (or InAs thin film) and I
nAs thin films (or AlAs thin films) are alternately stacked, and the thickness t1 _k (k = 1, 2,...) of the adjacent AlAs thin films
.., n) and the thickness t2 _k (k = 1, 2) of the InAs thin film
(2,..., N) in a field-effect transistor having an AlAs / InAs superlattice having a structure in which the ratio t2 _k / t1 _k is constant or decreased toward the upper layer immediately below the Schottky junction gate electrode. On the AlAs / InAs superlattice other than the portion, In _x Al _1-x
A field-effect transistor having an As layer (0 <x <1). 6. The field effect transistor according to claim 5, wherein the In composition ratio x satisfies 0.52 ≦ x <1. 7. A semiconductor substrate in which a buffer layer, a channel layer, and an AlAs thin film (or an InAs thin film) and an InAs thin film (or an AlAs thin film) are alternately laminated, and the thickness t1 _k (k = 1) of the adjacent AlAs thin films is stacked. , 2, ..., n)
And the thickness t2 _k (k = 1, 2,...) Of the InAs thin film
., N) a step of sequentially forming an AlAs / InAs superlattice having a structure in which the ratio t2 _k / t1 _k is constant or decreasing toward the upper layer to prepare a semiconductor crystal substrate;
In _x Al _1-x As layer (0 <x <
1) and one conductivity type In _w Ga _1-w As layer (0 <w <1)
Interposed therebetween sequentially the steps of depositing and selectively removing the one conductivity type In _w Ga _1-w As layer to form a recess that exposes the In _x Al _1-x As layer surface, the recess of the Forming a source electrode and a drain electrode in ohmic contact with the one conductivity type In _w Ga _1-w As layer, respectively;
The In _x Al _{1-x of the} recess is formed by lithography.
Removing the As layer to expose the AlAs / InAs superlattice surface and forming a gate electrode forming a Schottky junction therewith by a lift-off method. 8. A semiconductor substrate is a semi-insulating InP substrate, a buffer layer is an In _z Al _{1 -z} As layer (0 <z <1), and a channel layer is an n-type In _y Ga _{1 -y} As layer (0 <y). The method according to claim 6, wherein <1) is satisfied. 9. The method according to claim 7, wherein the In composition ratio x satisfies 0.52 ≦ x <1.