CN116344576A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDF

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Publication number
CN116344576A
CN116344576A CN202111582957.8A CN202111582957A CN116344576A CN 116344576 A CN116344576 A CN 116344576A CN 202111582957 A CN202111582957 A CN 202111582957A CN 116344576 A CN116344576 A CN 116344576A
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layer
semiconductor
semiconductor device
transistor
substrate
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CN202111582957.8A
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Chinese (zh)
Inventor
华特·吴
林鑫成
黄嘉庆
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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Priority to CN202111582957.8A priority Critical patent/CN116344576A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A semiconductor device includes an insulating layer, a semiconductor layer, and a compound semiconductor stack sequentially disposed on a substrate, and a first transistor, a second transistor, an isolation structure, and a conductive structure. The first transistor is located in the first element region, comprises a first grid electrode, a first source electrode and a first drain electrode, and is arranged on the compound semiconductor lamination layer, the second transistor is located in the second element region, comprises a second grid electrode, a second source electrode and a second drain electrode, is arranged on the compound semiconductor lamination layer, the isolation structure is arranged between the first transistor and the second transistor, the conductive structure is located in the second element region, penetrates through the compound semiconductor lamination layer and electrically connects the semiconductor layer to the second source electrode, and the semiconductor layer located in the first element region is not electrically connected with the first source electrode.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips
Technical Field
The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device including a high electron mobility transistor.
Background
In semiconductor technology, group III-V compound semiconductors may be used to form a variety of integrated circuit devices, such as: high power field effect transistors, high frequency transistors or high electron mobility transistors (high electron mobility transistor, HEMT). HEMTs are a type of transistor with two-dimensional electron gas (two dimensional electron gas, 2-DEG) that is adjacent to a junction (i.e., heterojunction) between two materials that differ in energy gap. Since HEMTs do not use doped regions as the carrier channel of the transistor, but rather use 2-DEG as the carrier channel of the transistor, HEMTs have a variety of attractive characteristics compared to existing Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), such as: high electron mobility and the ability to transmit signals at high frequencies.
Half-bridge circuits (half-bridge circuits) are widely used in the field of power electronics, and when an upper bridge (high side) switching element and a lower bridge (low side) switching element of the half-bridge circuit share the same substrate, they are susceptible to cross talk (cross talk), so that it is difficult to implement a System on a Chip (SoC) half-bridge circuit. HEMTs can be applied to half-bridge circuits as upper and lower bridge switching elements of the half-bridge circuits to achieve the benefits of a system on a chip (SoC), however, when HEMTs are applied to half-bridge circuits, there are still some problems that need to be overcome.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor device including a high electron mobility transistor with an improved back electrode to solve the problems encountered when the high electron mobility transistor is applied to a half bridge circuit.
According to an embodiment of the present invention, there is provided a semiconductor device including a substrate, an insulating layer, a semiconductor layer, a compound semiconductor stack, a first transistor, a second transistor, an isolation structure, and a conductive structure. The insulating layer, the semiconductor layer and the compound semiconductor lamination are sequentially arranged on the substrate, the first transistor is located in the first element area and comprises a first grid electrode, a first source electrode and a first drain electrode which are arranged on the compound semiconductor lamination, the second transistor is located in the second element area and comprises a second grid electrode, a second source electrode and a second drain electrode which are arranged on the compound semiconductor lamination, the isolation structure is arranged between the first transistor and the second transistor, the conductive structure is located in the second element area, penetrates through the compound semiconductor lamination and electrically connects the semiconductor layer to the second source electrode, and electric connection is not arranged between the semiconductor layer located in the first element area and the first source electrode.
In order to make the features of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
For a better understanding of the present invention, reference should be made to the drawings and to the detailed description thereof when read in light of the accompanying drawings. Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein the present embodiments are illustrated in the accompanying drawings. Furthermore, for the sake of clarity, various features in the drawings may not be drawn to actual scale, and therefore the dimensions of some features in some of the drawings may be exaggerated or reduced in size.
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 2 is a half-bridge circuit according to an embodiment of the invention.
Fig. 3 is a schematic top view of a semiconductor device according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present invention.
Fig. 6 is a half-bridge circuit according to another embodiment of the invention.
The reference numerals are explained as follows:
100 semiconductor devices; 100-1 a first transistor; 100-2 first transistor; a 101 substrate; 101-1 a first element region; 101-2 second element region; 103 an insulating layer; 105 semiconductor layers; 106 a buffer layer; 107 a high resistance layer; 108 a channel layer; 109 a barrier layer; 110 a compound semiconductor stack; 111 a first cap layer; 112 a second cap layer; 113 conductive structures; 115 conductive structures; 116 conductive pads; 117 interconnect structure; 118 wires; 120 isolation structures; 130 a half-bridge circuit; 140 sealing rings; 200 semiconductor devices; 200-1 a first transistor; 200-2 a first transistor; 230 half-bridge circuits; g1 first gate; g2 second gate; s1, a first source electrode; s2, a second source electrode; d1 first drain; d2 second drain; a 2DEG two-dimensional electron gas region; b1 and B2 back poles; vin input voltage node; GND ground; cox parasitic capacitance
Detailed Description
The invention provides several different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of "a first feature being formed on or over a second feature" may refer to "the first feature being in direct contact with the second feature" or may refer to "there being other features between the first feature and the second feature" such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference numerals and/or text labels. These repeated reference numerals and marks are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.
In addition, for the spatially related narrative terms mentioned in the present invention, for example: "under," "low," "under," "above," "over," "upper," "top," "bottom," and the like, when used in this specification, are defined as a relative relationship of one element or feature to another element(s) or feature(s) in the drawings. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With the semiconductor device oriented differently (rotated 90 degrees or other orientations), the spatially relative descriptors describing its orientation should be interpreted in a similar manner.
Although the invention has been described in the language of first, second, third, etc., to describe various elements, components, regions, layers and/or sections, it should be understood that these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, which does not itself imply any preceding ordinal number or order of arrangement or method of manufacture of the element. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the embodiments of the present invention.
The term "about" or "substantially" as referred to herein generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are about amounts, i.e., without a specific recitation of "about" or "substantially," what may still be implied by the meaning of "about" or "substantially.
The terms "coupled," "coupled," and "electrically connected" as used herein are intended to encompass any direct or indirect means of electrical connection. For example, if a first element is coupled to a second element, that connection may be directly to the second element or indirectly to the second element through other means of attachment or connection.
In the present invention, "group III-V semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element. Among them, the group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Further, the "group iii-v semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor, or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (inaias), gallium indium arsenide (InGaAs), the like, or a combination of the above compounds, but is not limited thereto. In addition, dopants may also be included in the III-V semiconductor, as desired, as well as III-V semiconductors having a particular conductivity type, such as n-type or p-type III-V semiconductors. Hereinafter, the III-V semiconductor may also be referred to as a III-V semiconductor.
Although the invention is described below by way of specific embodiments, the inventive principles of this patent are applicable to other embodiments as well. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such omitted are within the knowledge of persons of ordinary skill in the art.
The present invention relates to a semiconductor device including a High Electron Mobility Transistor (HEMT), wherein the HEMT can be used as a high voltage (high voltage) switching element (or referred to as an upper bridge switching element) and a low voltage (low voltage) switching element (or referred to as a lower bridge switching element) of a half bridge circuit, and according to the embodiments of the present invention, a back electrode of the HEMT as the upper bridge switching element is not electrically connected to a source electrode, but is electrically connected to a ground terminal, or is made to be an electrically floating layer (electrically floating layer), so that parasitic capacitance is not generated between the back electrode of the upper bridge switching element and a substrate of the semiconductor device, and further, an input/output voltage of the semiconductor device is prevented from being affected, and a thickness between the back electrode of the semiconductor device and the substrate is prevented from limiting a device power supply voltage (Vbus).
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. As shown in fig. 1, in one embodiment, a semiconductor device 100 includes a substrate 101, an insulating layer 103, a semiconductor layer 105, and a compound semiconductor stack 110 sequentially disposed from bottom to top. According to some embodiments, the material of the substrate 101 may include ceramic, silicon carbide (SiC), aluminum nitride (AlN), sapphire (sapphire), or silicon. When the substrate 101 is made of a material having high hardness, high thermal conductivity, and low electrical conductivity, such as a ceramic substrate, it is more suitable for a high-voltage semiconductor device. The high hardness, high thermal conductivity, and low electrical conductivity mentioned above are compared to a single crystal silicon substrate, and the high voltage semiconductor device refers to a semiconductor device having an operating voltage higher than 50V. The material of the insulating layer 103 may comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the material of the semiconductor layer 105 may comprise silicon or polysilicon. In an embodiment, the substrate 101 is, for example, silicon, the insulating layer 103 is, for example, silicon oxide, the semiconductor layer 105 is, for example, silicon, and the substrate 101, the insulating layer 103 and the semiconductor layer 105 constitute a semiconductor-on-insulator (semiconductor on insulator, SOI) substrate, i.e., the substrate 101, the insulating layer 103 and the semiconductor layer 105 of an embodiment of the present invention may be provided by an SOI substrate. In another embodiment, the substrate 101, the insulating layer 103 and the semiconductor layer 105 may be provided by a composite substrate (also referred to as a QST substrate) formed by wrapping a core substrate with a composite material layer, wherein the core substrate comprises ceramic, silicon carbide, aluminum nitride, sapphire or silicon, the composite material layer comprises an insulating material layer and a semiconductor material layer, the insulating material layer may be single-layer or multi-layer silicon oxide, silicon nitride or silicon oxynitride, the semiconductor material layer may be silicon or polysilicon, and the composite material layer on the back surface of the core substrate is removed through a thinning process, such as a grinding or etching process, so that the back surface of the core substrate is exposed. In some embodiments, the thickness of the insulating layer 103 may range from about 1 micrometer (μm) to about 3 micrometers (μm), for example about 2 micrometers (μm), and the thickness of the semiconductor layer 105 may range from about 5 nanometers (nm) to about 350 nanometers (nm), and the thickness of the semiconductor layer 105 may be moderately adjusted so that it does not crack. In some embodiments, the substrate 101 is an insulating substrate, the material of which comprises ceramic, aluminum nitride, or sapphire. In other embodiments, the substrate 101 is electrically connected to ground.
According to an embodiment of the present invention, a compound semiconductor stack 110 is disposed on the semiconductor layer 105 to form a high electron mobility transistor. The compound semiconductor layer 110 may be formed over the semiconductor layer 105 by epitaxial growth, and the semiconductor layer 105 may serve as a seed layer (seed layer) of the compound semiconductor layer 110. According to some embodiments, the compound semiconductor stack 110 may include a buffer layer (buffer layer) 106, a high-resistance layer (high resistance layer) (or referred to as an electrical isolation layer) 107, a channel layer (channel layer) 108, and a barrier layer (barrier layer) 109, which are sequentially stacked on the semiconductor layer 105 from bottom to top, and each layer material of the compound semiconductor stack 110 includes a group III-V compound semiconductor (also referred to as a group III-V semiconductor). In one embodiment, the buffer layer 106 may be a Superlattice (SL) structure, for example, including a plurality of layers of aluminum gallium nitride (AlGaN) and aluminum nitride (AlN) alternately stacked, the high-resistance layer 107 may be a carbon-doped gallium nitride (c-GaN) layer, the channel layer 108 may be an undoped gallium nitride (u-GaN) layer, and the barrier layer 109 may be an aluminum gallium nitride (AlGaN) layer, but is not limited thereto. In addition, the compound semiconductor stack 110 may further include other layers, such as an epitaxial layer (e.g., alN) for reducing lattice defects, which may be provided between the buffer layer 106 and the semiconductor layer 105. The composition and structural arrangement of the layers of the compound semiconductor stack 110 may be dependent on the requirements of various semiconductor devices.
According to an embodiment of the present invention, the semiconductor device 100 further includes a first transistor 100-1 and a second transistor 100-2, the first transistor 100-1 is located in the first element region 101-1, and includes a first gate G1, a first source S1 and a first drain D1 disposed on the compound semiconductor stack 110. The second transistor 100-2 is located in the second element region 101-2 and includes a second gate G2, a second source S2, and a second drain D2 disposed on the compound semiconductor stack 110. In addition, the first transistor 100-1 further includes a first cap layer 111 disposed between the first gate electrode G1 and the barrier layer 109, and the second transistor 100-2 further includes a second cap layer 112 disposed between the second gate electrode G2 and the barrier layer 109. In an embodiment, the first cap layer 111 and the second cap layer 112 are, for example, p-type gallium nitride (p-GaN) layers, but are not limited thereto. By stacking the channel layer 108 and the barrier layer 109 on each other, electrons are accumulated at the heterojunction between the channel layer 108 and the barrier layer 109 due to the piezoelectric effect, thereby generating a thin layer with high electron mobility, i.e., a two-dimensional electron gas region 2DEG. In the normal off (normal off) device, when no voltage is applied to the first gate G1 and the second gate G2, the region covered by the first cap layer 111 and the second cap layer 112 does not form two-dimensional electron gas (as shown in fig. 1), and is regarded as a 2DEG intercepting region, and at this time, conduction is not performed between the first source S1 and the first drain D1 and between the second source S2 and the second drain D2. When a positive voltage is applied to the first gate electrode G1 and the second gate electrode G2, the region covered by the first cover layer 111 and the second cover layer 112 forms a two-dimensional electron gas, so that a continuous two-dimensional electron gas region is generated between the first source electrode S1 and the first drain electrode D1, between the second source electrode S2 and the second drain electrode D2, and conduction is performed between the first source electrode S1 and the first drain electrode D1, and between the second source electrode S2 and the second drain electrode D2. In an embodiment of the present invention, the first transistor 100-1 and the second transistor 100-2 are High Electron Mobility Transistors (HEMTs).
In addition, the semiconductor device 100 further includes an isolation structure 120 disposed between the first transistor 100-1 and the second transistor 100-2. In some embodiments, the isolation structure 120 penetrates the compound semiconductor stack 110 and the semiconductor layer 105 and further extends down to a depth of the insulating layer 103, and a bottom surface of the isolation structure 120 may be lower than a top surface of the insulating layer 103. The isolation structure 120 may be formed by etching deep trenches into the compound semiconductor stack 110, the semiconductor layer 105, and the insulating layer 103, filling the deep trenches with a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof, and performing a chemical-mechanical planarization (CMP) process. In some embodiments, the isolation structure 120 may be a ring-shaped insulating pillar structure surrounding the first transistor 100-1 and the second transistor 100-2. In the embodiment of the present invention, the semiconductor layer 105 may serve as the back electrode (backside electrode) of the first transistor 100-1 and the second transistor 100-2, and the isolation structure 120 penetrating the compound semiconductor layer stack 110 and the semiconductor layer 105 may provide good electrical isolation between the first transistor 100-1 and the second transistor 100-2.
Fig. 2 illustrates a half-bridge circuit 130 according to an embodiment of the invention, as shown in fig. 2, the first transistor 100-1 may be a high voltage (or referred to as an upper-bridge switching element) switching element of the half-bridge circuit 130, the second transistor 100-2 may be a low voltage (or referred to as a lower-bridge switching element) switching element of the half-bridge circuit 130, wherein the first drain D1 of the upper-bridge switching element is electrically connected to an input voltage node Vin, the second source S2 of the lower-bridge switching element is electrically connected to a ground GND, the first source S1 of the upper-bridge switching element is electrically connected to the second drain D2 of the lower-bridge switching element, and may further be electrically connected to an output voltage node (not shown). Referring to fig. 1 and fig. 2, the semiconductor device 100 further includes a conductive structure 113 disposed in the second device region 101-2, wherein the conductive structure 113 penetrates through the compound semiconductor stack 110 in the second device region 101-2 and electrically connects the semiconductor layer 105 in the second device region 101-2 to the second source electrode S2. Since the semiconductor layer 105 can serve as the back electrode B1 of the first transistor 100-1 and the back electrode B2 of the second transistor 100-2, the conductive structure 113 can electrically connect the back electrode B2 of the second transistor 100-2 (also referred to as a lower bridge switching element) to the second source electrode S2, and the second source electrode S2 of the lower bridge switching element is typically electrically connected to the ground node, so that the back electrode B2 of the second transistor 100-2 can be electrically grounded through the conductive structure 113 and the second source electrode S2.
Furthermore, according to the embodiment of the present invention, there is no electrical connection between the semiconductor layer 105 located in the first element region 101-1 and the first source electrode S1, i.e., the back electrode B1 of the first transistor 100-1 (also referred to as an upper bridge switching element) is not directly electrically connected to the first source electrode S1, and there is no conductive structure penetrating the compound semiconductor layer stack 110 and connected to the semiconductor layer 105 in the vertical projection region of the first source electrode S1. Since the first source S1 of the upper bridge switching device is electrically connected to the second drain D2 of the lower bridge switching device through the interconnection structure 117 and has a potential of the output voltage, the semiconductor layer 105 in the first device region 101-1 of the embodiment of the invention is not electrically connected to the first source S1, so that the semiconductor layer 105 in the first device region 101-1 does not have a potential of the output voltage, and parasitic capacitance is avoided between the semiconductor layer 105 and the substrate 101 in the first device region 101-1, thereby avoiding the input/output voltage of the semiconductor device 100 from being affected and maintaining a normal operating voltage.
Referring to fig. 1 and fig. 2, the semiconductor layer 105 (the back electrode B1 of the upper bridge switching element) in the first element region 101-1 may be electrically connected to the ground via another conductive structure 115 disposed outside the first gate G1, the first source S1 and the first drain D1, as shown in fig. 2, and in an embodiment, the back electrode B1 of the upper bridge switching element and the second source S2 of the lower bridge switching element are both electrically connected to the same ground node. As shown in fig. 1, in an embodiment, another conductive structure 115 is disposed in an area other than the vertical projection area of the first gate G1, the first source S1 and the first drain D1, and the conductive structure 115 penetrates through the compound semiconductor stack 110 and is electrically connected to the semiconductor layer 105, and the conductive structure 115 may be electrically connected to a ground via a conductive pad (conductive pad) 116 disposed above the conductive structure 115, so that the back electrode B1 of the upper bridge switching element is electrically connected to the ground via the conductive structure 115, the conductive pad 116 and other connection structures.
Fig. 3 is a schematic top view of a semiconductor device according to an embodiment of the invention. As shown in FIG. 3, in one embodiment, the periphery of the first device region 101-1 and/or the second device region 101-2 is surrounded by a conductive seal ring 140. The conductive pad 116 in the first device region 101-1 may be electrically connected to a seal ring 140 disposed at the periphery of the device region of the semiconductor device 100 through a conductive line 118, and electrically connected to a ground terminal through the seal ring 140, so that the conductive structure 115 under the conductive pad 116 in the first device region 101-1 is electrically connected to the ground terminal, and thus the semiconductor layer 105 in the first device region 101-1 is electrically grounded. The conductive line 118 may be disposed in a dielectric layer (not shown) above the conductive pad 116, but is not limited thereto. Although only two first device regions 101-1 and two second device regions 101-2 are depicted in fig. 3 as being surrounded by the seal ring 140, there may be more device regions actually surrounded by the seal ring 140, and each device region is surrounded by the isolation structures 120, in one embodiment, the isolation structures 120 may be interconnected to form a mesh structure. In addition, the isolation structure 120 may be an insulating pillar structure surrounding the conductive structure 115 under the conductive pad 116 to avoid unnecessary electrical connection between the adjacent first device region 101-1 and second device region 101-2.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. The semiconductor device 100 of fig. 4 differs from the semiconductor device 100 of fig. 1 in that the first source S1 and the first drain D1 of the first transistor 100-1 and the second source S2 and the second drain D2 of the second transistor 100-2 extend downward through the barrier layer 109 to the top surface of the channel layer 108, and the conductive structure 113 in the second element region 101-2 is disposed directly under the second source S2, through all of the channel layer 108, the high resistance layer 107 and the buffer layer 106, but not through the barrier layer 109. In another embodiment, the first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2 may further extend down to a depth of the channel layer 108, and the conductive structure 113 contacting the second source electrode S2 may penetrate a portion of the channel layer 108 and the high-resistance layer 107 and the buffer layer 106.
In the semiconductor device 100 of fig. 4, the isolation structure 120 penetrates the compound semiconductor stack 110 and the semiconductor layer 105 to reach the top surface of the insulating layer 103, that is, the bottom surface of the isolation structure 120 is flush with the top surface of the insulating layer 103. In some embodiments, the substrate 101 is an insulating substrate, the material of which comprises ceramic, aluminum nitride, or sapphire. In other embodiments, the substrate 101 is electrically connected to ground. In addition, in the semiconductor device 100 of fig. 4, the semiconductor layer 105 in the first element region 101-1 may be an electrically floating layer, that is, the semiconductor layer 105 in the first element region 101-1 is not electrically connected to the ground through another conductive structure 115 shown in fig. 1, but the semiconductor layer 105 in the first element region 101-1 has a floating potential close to 0V, and parasitic capacitance is not generated between the semiconductor layer 105 in the first element region 101-1 and the substrate 101 because the substrate 101 has a ground potential or is an insulating substrate.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. As shown in fig. 5, the semiconductor device 200 of this embodiment is different from the semiconductor device 100 of fig. 1 and 4 in that the first source S1 of the first transistor 200-1 as the upper bridge switching element is electrically connected to the semiconductor layer 105 in the first element region 101-1 through the conductive structure 113. Fig. 6 is a schematic diagram of a half-bridge circuit 230 according to another embodiment of the present invention, please refer to fig. 5 and 6, in which, since the semiconductor layer 105 in the first element region 101-1 of the semiconductor device 200 of this embodiment, that is, the back electrode B1 of the first transistor 200-1 is electrically connected to the first source electrode S1, and the first source electrode S1 is electrically connected to the second drain electrode D2, and further electrically connected to a node (not shown) of the output voltage, the semiconductor layer 105 in the first element region 101-1 of the semiconductor device 200 of this embodiment has a floating potential of 0V to the output voltage, so that parasitic capacitance Cox is generated between the semiconductor layer 105 in the first element region 101-1 of the semiconductor device 200 and the substrate 101, which affects the input/output voltage of the semiconductor device 200, and thus the power supply cannot maintain the normal operating voltage.
In addition, the parasitic capacitance Cox of the semiconductor device 200 of this embodiment is affected by the thickness of the insulating layer 103, and the thickness of the insulating layer 103 of the semiconductor device 200 must be increased to reduce the parasitic capacitance Cox, however, when the thickness of the insulating layer 103 is thicker, the heat dissipation capability of the semiconductor device 200 is also degraded, resulting in a decrease in the performance of the semiconductor device 200.
In contrast, with the semiconductor device 100 illustrated in fig. 1 to 4, since the semiconductor layer 105 in the first element region 101-1 of the semiconductor device 100 according to the embodiment of the present invention, that is, the back electrode B1 of the first transistor 100-1 of the upper bridge switching element is electrically connected to the ground node or is an electrically floating layer having a potential close to 0V, no parasitic capacitance is generated between the semiconductor layer 105 and the substrate 101 in the first element region 101-1, and the thickness of the insulating layer 103 is not limited, that is, the thickness of the insulating layer 103 may be relatively thin to maintain the heat dissipation capability of the semiconductor device 100. In addition, according to some embodiments of the present invention, the substrate 101 is an electrically insulating and thermally conductive substrate, for example, made of highly insulating and highly thermally conductive aluminum nitride (AlN), which has a thermal conductivity higher than that of the insulating layer 103. At this time, the substrate 101 can not only increase the heat dissipation capability of the semiconductor device 100, but also increase the thickness of the overall insulation (i.e. the thickness of the insulating layer 103 plus the thickness of the substrate 101) that forms the parasitic capacitance, thereby greatly reducing the parasitic capacitance, and substantially eliminating the parasitic capacitance without being ignored, so that the limitation of the thickness of the insulating layer (vertical thickness) under the back electrode of the semiconductor device 100 on the device power supply voltage (Vbus) can be avoided.
Therefore, the semiconductor device of the embodiment of the invention can use the high electron mobility transistor as the upper bridge switching element and the lower bridge switching element of the half bridge circuit, thereby achieving the benefit of a system on a chip (SoC), avoiding parasitic inductance and capacitance effects caused by wire bonding between the upper bridge switching element and the lower bridge switching element, eliminating parasitic capacitance between the back electrode and the substrate of the upper bridge switching element, avoiding the limitation of the thickness of the insulating layer below the back electrode on the power supply voltage (Vbus) of the device, maintaining the heat dissipation function of the semiconductor device, and further improving the efficiency of the semiconductor device.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (20)

1. A semiconductor device, comprising:
an insulating layer, a semiconductor layer and a compound semiconductor lamination layer are sequentially arranged on a substrate;
a first transistor located in a first element region and including a first gate, a first source and a first drain disposed on the compound semiconductor layer;
a second transistor located in a second element region and including a second gate, a second source and a second drain disposed on the compound semiconductor layer;
an isolation structure disposed between the first transistor and the second transistor; and
a conductive structure located in the second element region, penetrating the compound semiconductor stack, and electrically connecting the semiconductor layer to the second source electrode;
wherein the semiconductor layer located in the first element region and the first source electrode are not electrically connected.
2. The semiconductor device according to claim 1, wherein the semiconductor layer in the first element region is an electrically floating layer or is configured to be electrically connected to a ground node.
3. The semiconductor device according to claim 1, wherein the semiconductor layer in the first element region is electrically connected to a ground terminal via a seal ring.
4. The semiconductor device of claim 3, further comprising another conductive structure located within the first element region and extending through the compound semiconductor stack, wherein the another conductive structure electrically connects the seal ring to the semiconductor layer.
5. The semiconductor device according to claim 4, wherein the other conductive structure is disposed outside a vertical projection region of the first gate, the first source, and the first drain of the first transistor.
6. The semiconductor device according to claim 1, wherein the first transistor and the second transistor comprise high electron mobility transistors, the first transistor is a high voltage switching element of a half-bridge circuit, and the second transistor is a low voltage switching element of the half-bridge circuit.
7. The semiconductor device according to claim 1, wherein the semiconductor layer and the second source electrode located in the first element region are electrically connected to the same ground node.
8. The semiconductor device of claim 1, wherein the substrate is electrically connected to ground.
9. The semiconductor device of claim 1, wherein the substrate, the insulating layer, and the semiconductor layer comprise an insulating layer-on-semiconductor substrate.
10. The semiconductor device according to claim 1, wherein the substrate is an insulating substrate.
11. The semiconductor device according to claim 1, wherein the semiconductor layer is a seed layer.
12. The semiconductor device according to claim 1, wherein a thickness of the semiconductor layer is 5 nm to 350 nm.
13. The semiconductor device according to claim 1, wherein a thickness of the insulating layer is 1 to 3 μm.
14. The semiconductor device of claim 1, wherein the substrate comprises ceramic, silicon carbide, aluminum nitride, sapphire, or silicon, the insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the semiconductor layer comprises silicon or polysilicon.
15. The semiconductor device according to claim 1, wherein the compound semiconductor stack comprises a buffer layer, a high-resistance layer, a channel layer, and a barrier layer, which are sequentially disposed on the semiconductor layer, and wherein the material of the compound semiconductor stack comprises a iii-v compound semiconductor.
16. The semiconductor device of claim 15, wherein the first source, the first drain, the second source, and the second drain are disposed on the barrier layer or pass through the barrier layer to the channel layer.
17. The semiconductor device of claim 15, further comprising a first cap layer disposed between the first gate and the barrier layer, and a second cap layer disposed between the second gate and the barrier layer.
18. The semiconductor device according to claim 1, wherein the isolation structure penetrates through the compound semiconductor stack and the semiconductor layer, and a bottom surface of the isolation structure is lower than a top surface of the insulating layer or the bottom surface of the isolation structure is in the same plane as the top surface of the insulating layer.
19. The semiconductor device according to claim 1, wherein the isolation structure is an insulating column structure penetrating the compound semiconductor stack and the semiconductor layer and surrounding the first transistor and the second transistor.
20. The semiconductor device of claim 19, further comprising another conductive structure within the first device region and extending through the compound semiconductor stack, wherein the insulating pillar structure surrounds the another conductive structure and the another conductive structure is electrically connected to ground.
CN202111582957.8A 2021-12-22 2021-12-22 Semiconductor device with a semiconductor device having a plurality of semiconductor chips Pending CN116344576A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111582957.8A CN116344576A (en) 2021-12-22 2021-12-22 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Publications (1)

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CN116344576A true CN116344576A (en) 2023-06-27

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