JP2006278543A - Switching circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent puncture due to secondary breakdown by preventing concentration of current on one unit element even if the operating current becomes uneven among unit elements. <P>SOLUTION: In the switching circuit device, an HBT 101 and an FET 102 are contiguously arranged through an isolation region, and a plurality of unit elements where the base electrode of the HBT is connected with the source electrode of an MESFET are connected. Consequently, in the switching circuit device connecting a plurality of unit elements in parallel, current does not concentrate on one unit element 100 even if the operating current of each unit element becomes uneven and thereby puncture due to secondary breakdown is prevented. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a switch circuit device using a heterojunction bipolar transistor, and more particularly to a temperature compensation type switch circuit device.

Heterojunction bipolar transistor (Heterojunction Bipolar Transistor: hereinafter HBT) is a base concentration because of the high high current amplification factor _{h FE} emitter efficiency than normal homojunction bipolar transistor can be increased significantly, over the entire base Transistor operation can be made uniform. As a result, the current density is high and the on-resistance is low because of the high current density, low on-resistance, and high efficiency compared with GaAs MESFET (Metal Semiconductor Field Effect Transistor), GaAs JFET (Junction FET), and HEMT (High Electron Mobility Transistor). Are better.

  In mobile communication devices such as mobile phones, highly efficient and small high-frequency switching elements are indispensable. Therefore, as shown in FIG. 11, a switch circuit having a bidirectional heterojunction bipolar transistor as a switching element is known.

  FIG. 11 shows an example of a switch circuit using an HBT as a switching element. FIG. 11A is a circuit diagram, and FIG. 11B is a cross-sectional view showing the structure of an HBT.

  As shown in FIG. 11A, this circuit includes a first HBT 320 whose emitter is connected to the antenna ANT, and a second HBT 321 whose collector is connected to the antenna ANT, and the collector of the first HBT 320 transmits. It is connected to the use side circuit Tx. The emitter of the second HBT 321 is connected to the reception side circuit Rx, and the bases of the HBTs 320 and 321 are connected to the transmission control terminal CtrlTx and the reception control terminal CtrlRx via the resistor 122, respectively.

  As shown in FIG. 11B, an n-type GaAs subcollector layer 311 is formed on a semi-insulating GaAs substrate 310, and an n-type AlGaAs collector layer 312, a p-type GaAs base layer 313, and an n-type are formed on the subcollector layer 311. An AlGaAs emitter layer 314, an n-type GaAs emitter contact layer 315, and the like are stacked in a mesa shape.

A collector electrode 316 is disposed on the surface of the subcollector layer 311 at a position sandwiching the collector layer 312. A base electrode 317 is disposed on the surface of the base layer 313 at a position sandwiching the emitter layer 314. An emitter electrode 318 is disposed on the emitter contact layer 315.
JP 2000-260782 A

  The emitter electrode 318, base electrode 317, and collector electrode 316 of the HBT are formed in a comb shape. The structure shown in FIG. 11B is used as one unit element, and a plurality of unit elements are connected in parallel to form an active element such as a switching element.

  In the HBT, since the base-emitter current has a positive temperature coefficient, the collector current also has a positive temperature coefficient. Accordingly, when the current density is improved by increasing the base current, the current concentrates on one unit element among the plurality of HBT unit elements connected in parallel to cause a secondary breakdown, which easily leads to breakdown. .

  Conventionally, in order to avoid such a problem in reliability, there has been a problem that the current density cannot be sufficiently improved.

  The present invention has been made in view of such a problem. First, a compound semiconductor substrate in which a plurality of semiconductor layers forming at least one heterojunction are stacked, and the semiconductor layer provided on the substrate, each of the semiconductor layers being a collector layer and a base layer. A first transistor having a collector electrode, a base electrode, and an emitter electrode as an emitter layer; a second transistor provided on the substrate and having a gate electrode, a source electrode, and a drain electrode; the first transistor and the second transistor; Are arranged adjacent to each other through an isolation region, a unit element that connects the base electrode of the first transistor and the source electrode of the second transistor, and a plurality of switching elements that connect the unit elements in parallel, A first RF port commonly connected to a collector electrode or an emitter electrode of the plurality of switching elements; A plurality of second RF ports connected to emitter electrodes or collector electrodes of the plurality of switching elements, respectively, and power supply terminals connected to drain electrodes of the plurality of switching elements, respectively, and each of the gate electrodes of the second transistors The problem is solved by applying a control signal, driving the first transistor with a current supplied by conduction of the second transistor, and forming a signal path between the first and second RF ports.

According to this embodiment, an HBT and an FET are arranged adjacent to each other through an isolation region, and a plurality of unit elements each having a source electrode of an MESFET connected to a base electrode of the HBT are connected to form a switching element, and a switch circuit device Is realized. In other words, the unit element has a MESFET connected to each base electrode of the comb-shaped HBT, and the HBT and the MESFET are arranged adjacent to each other via the isolation region. The switching element connects the drain electrode of the MESFET to the power supply terminal V _DD , and changes the collector-emitter current of the HBT by a voltage signal input to the gate electrode of the MESFET. Since the distance between the HBT and the MESFET is close, heat generated by the operation of the HBT is transmitted to the MESFET. However, since the drain current of the MESFET has a negative temperature coefficient, the base current of the HBT of this embodiment also has a negative temperature coefficient. That is, in the present embodiment, the heat generation of the HBT decreases the collector current of the HBT.

  Therefore, in a switching element in which a plurality of such unit elements are connected in parallel, even if the operating current is non-uniform for each unit element, the current does not concentrate on one unit element, and breakdown due to secondary breakdown occurs. do not do. That is, the current density can be greatly improved as compared with the conventional HBT.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  First, referring to FIG. 1, a circuit diagram of a switching circuit device according to a first embodiment is shown. 1A is a schematic diagram of a circuit diagram, and FIG. 1B is an actual circuit diagram.

  The switching circuit device is, for example, an SPDT (Single Pole Double Throw) switch MMIC.

  The SPDT switch MMIC includes a first switching element SW1 and a second switching element SW2. The first switching element SW1 is composed of HBT1 and FET1, and the second switching element SW2 is composed of HBT2 and FET2. Note that FET1 and FET2 are MESFETs (Metal Semiconductor Field Effect Transistors).

  The first and second switching elements SW1 and SW2 have the collectors of HBT1 and HBT2 commonly connected to the first RF port. The first RF port is a common input terminal IN connected to, for example, an antenna.

  Further, the first and second switching elements SW1 and SW2 have the emitters of HBT1 and HBT2 connected to the second RF port, respectively. The second RF port is, for example, a first output terminal OUT1 connected to a transmission side circuit or the like, and a second output terminal OUT2 connected to a reception side circuit or the like.

  The bases of HBT1 and HBT2 are connected to the first control terminal Ctl1 and the second control terminal Ctl2 which are, for example, a transmission control terminal and a reception control terminal via FET1 and FET2, respectively.

Each of FET1 and FET2 has a drain connected to the power supply terminal V _DD and a source connected to the bases of HBT1 and HBT2. The gates are connected to the first control terminal Ctl1 and the second control terminal Ctl2 via the control resistors R1 and R2, respectively. The control resistors R1 and R2 are arranged for the purpose of preventing leakage of a high-frequency signal through the gate with respect to the DC potential of the control terminals Ctl1 and Ctl2 serving as AC grounding. The resistance values of the control resistors R1 and R2 are about 5 KΩ to 10 KΩ.

  A case where the control signals applied to the first control terminal Ctl1 and the second control terminal Ctl2 are complementary signals will be described. In this case, when the signal at the first control terminal Ctl1 is at the H level (eg, 3V), the signal at the second control terminal Ctl2 is at the L level (eg, 0V). Then, the FET on the side to which the H level is applied conducts, and either HBT1 or HBT2 is driven by the current supplied by the FET. One signal path is formed between the first RF port and the second RF port.

For example, when the H level is applied to the first control terminal Ctl1, the source and drain of the FET 1 are conducted. Thus, the base current _{I B} supplied from the power supply terminal _{V DD} as a base bias, HBT 1 is operated. At this time, since an L level signal is applied to the second control terminal Ctl2, the FET2 does not conduct and the HBT2 does not operate. As a result, one signal path is formed between the common input terminal IN and the first output terminal OUT1, and for example, a high-frequency analog signal input to the common input terminal IN is output from the first output terminal OUT1. On the other hand, when an H level signal is applied to the second control terminal Ctl2, one signal path is formed between the common input terminal IN and the second output terminal OUT2.

  A bias point BP is connected to the emitter and collector of HBT1 and HBT2, respectively. The bias point BP applies a bias potential (for example, GND potential) equal to the emitters and collectors of HBT1 and HBT2.

  Then, high-frequency signal separating elements 30 are connected between the emitters of HBT1 and HBT2 and the bias point BP, and between the collectors of HBT1 and HBT2 and the bias point BP, respectively. The separation element 30 is a resistor having a resistance value of 5 KΩ to 10 KΩ, for example, and prevents the high frequency signal from leaking with respect to the bias potential (GND potential).

Further, for the same reason, the high-frequency signal separation element 30 is also connected between the power supply terminal V _DD to which the drain bias is applied and the FET 1 and between the power supply terminal V _DD and the FET 2.

  The circuit operation will be described below.

The on-voltage (base-emitter voltage V _BE ) of HBT1 and HBT2 is, for example, 1.6V. FET1 and FET2 are enhancement type, and the pinch-off voltage Vp is 0V.

  That is, FET1 and HBT1 are turned on for the first time when the potential of the on-side control terminal (for example, the first control terminal Ctl1) becomes 1.6V (= 1.6V + 0V) or more higher than the potential of the emitter and collector of HBT1. .

  Here, the potentials of the emitters and collectors of HBT1 and HBT2 are set to the GND potential (0 V). Since 3V is applied to the first control terminal Ctl1 on the on side, the potential difference between the first control terminal Ctl1 and the potentials of the emitter and collector of the HBT1 is 3V (= 3V-0V). This is sufficiently higher than the potential (1.6 V) at which both FET1 and HBT1 are turned on. That is, even when voltage drop due to the separation element 30 (resistor) connected to the bias point BP is taken into account, the FET 1 and the HBT 1 are sufficiently turned on by the potential applied from the first control terminal Ctl 1, and the emitter-collector of the HBT 1 becomes conductive. .

  On the other hand, on the off side, the second control terminal Ctl2 is 0V with respect to the potential of the emitter and collector of the HBT2 of 0V (GND). Since the FET 2 and the HBT 2 are turned on when the potential of the second control terminal Ctl 2 becomes 1.6 V or higher than the potential of the emitter and collector of the HBT 2, the OFF side can withstand 1.6 V amplitude power.

  An amplitude of 1.6 V corresponds to a power of 20.1 dBm, and can be used for wireless LAN and Bluetooth.

  Thus, for example, in the first switching element SW1, when the potential of the first control terminal Ctl1 with respect to the potential of the emitter and collector of the HBT1 exceeds the value obtained by adding the ON voltage of the HBT1 and the pinch-off voltage of the FET1, It starts to turn on (the same applies to the second switching element SW2 side). In the first embodiment, the potentials of the emitters and collectors of HBT1 and HBT2 are set to GND. Although not shown, the potentials of the emitters and collectors of HBT1 and HBT2 can be set freely by providing a bias circuit such as a resistance divider. Therefore, the value obtained by adding the ON voltage of HBT1 and HBT2 and the pinch-off voltage of FET1 and FET2 is not limited to the above example, and is the same as that of the first embodiment by adjusting the bias circuit. Characteristics can be obtained. That is, FET1 and FET2 may be either enhancement type or depletion type.

  FIG. 1B is a circuit diagram showing an actual connection between HBT1 and FET1 and an actual connection between HBT2 and FET2 shown in FIG.

  The actual pattern of HBT1 and HBT2 constituting the first and second switching elements SW1 and SW2 has a collector, base and emitter arranged in a comb shape, and FET1 and FET2 also have a source, drain and gate arranged in a comb shape. . The base of HBT1 and the source of FET1 and the base of HBT2 and the source of FET2 actually correspond to each comb.

  In FIG. 1B, each comb of HBT1, HBT2, FET1, and FET2 is shown. That is, in this embodiment, the first transistor 101 and the second transistor 102 are connected to form the unit element 100, and a plurality of unit elements 100 are connected in parallel to form the first switching element SW1 and the second switching element SW2. .

  The first transistor 101 is formed by stacking semiconductor layers to be a collector layer, a base layer, and an emitter layer on a compound semiconductor substrate to form at least one heterojunction, and a collector electrode, a base electrode, and an emitter electrode respectively connected to each semiconductor layer. It is HBT which has. The HBT has a mesa structure, and in the present embodiment, the first transistor configured with the minimum unit mesa structure is hereinafter referred to as a unit HBT101.

  The second transistor 102 is a MESFET that is provided on the same substrate as the unit HBT 101, has one of the semiconductor layers as a channel layer, and includes a gate electrode, a source electrode, and a drain electrode. In the present embodiment, the second transistor 102 configured by the minimum unit of each electrode is hereinafter referred to as a unit FET 102.

  One set of unit HBT 101 and unit FET 102 are arranged adjacent to each other via an isolation region described later, and the base of unit HBT 101 and the source of unit FET 102 are connected to form one unit element 100 (broken line). Yes.

  The unit elements 100 are connected in parallel to form the first switching element SW1 and the second switching element SW2. The unit elements 100 are connected in parallel, but the base and source of one unit element 100 are not commonly connected to the base and source of other unit elements 100, respectively.

  Specifically, one unit element 100 commonly connects the emitter and collector of the unit HBT 101 and the drain and gate of the FET 102 to the emitter, collector, drain and gate of the other unit HBT 101, respectively.

In each unit element 100, the drain of the unit FET 102 is connected to the power supply terminal V _DD . Then, the collector-emitter voltage V _CE of the unit HBT 101 is biased to 0 V, and complementary signals are applied to the first and second control terminals Ctl1 and Ctl2. As a result, a predetermined base current is applied to the unit HBT 101 of either the first switching element SW1 or the second switching element SW2 to conduct between the collector and the emitter. Alternatively, the base current is set to 0 and the collector-emitter is cut off. Thereby, a signal path is formed either between the common input terminal IN and the first output terminal OUT1 or between the common input terminal IN and the second output terminal OUT2.

  FIG. 1A schematically shows these, and shows a state in which an HBT1 is configured by the unit HBT101 of the first switching element SW1 and an FET1 is configured by the unit FET102 of the first switching element SW1. Similarly, the HBT2 shown in FIG. 1A is configured by the unit HBT101 of the second switching element SW2, and the FET2 is configured by the unit FET102 of the second switching element SW2.

  As described above, as the operation of the switching circuit device of the first embodiment, the control signals applied to the first control terminal Ctl1 and the second control terminal Ctl2 are complementary signals, and the first switching element SW1 and the second switching element SW2 The case where either of them is conducted is shown.

  However, the control signals applied to the first control terminal Ctl1 and the second control terminal Ctl2 may be both H level or both L level. When both are at the H level, both the first switching element SW1 and the second switching element SW2 are conductive, and when both are at the L level, both SW1 and SW2 are cut off.

  FIG. 2 shows a pattern example of a switch MMIC in which the circuit of FIG. 1B is integrated on a compound semiconductor substrate.

First and second switching elements SW1 and SW2 for switching are arranged on a GaAs substrate. Further, the pads I, O1, O2, C1, which become the common input terminal IN, the first output terminal OUT1, the second output terminal OUT2, the first control terminal Ctl1, the second control terminal Ctl2, the power supply terminal V _DD , and the ground terminal GND, C2, V, and G are provided around the substrate.

  The first switching element SW1, the second switching element SW2, and the pads are arranged symmetrically with respect to the center of the chip. Accordingly, the first switching element SW1 side will be described below, but the same applies to the second switching element SW2 side.

  The first switching element SW1 is configured by connecting a plurality of unit elements 100 in parallel, and each unit element 100 includes a unit HBT 101 and a unit FET 102. The unit HBT 101 and the unit FET 102 are formed by stacking a plurality of semiconductor layers on a substrate and making each semiconductor layer have a predetermined mesa structure. Further, an element constituting the switch MMIC such as a resistor is formed by the impurity region made of the semiconductor layer. As will be described later, the impurity region of this embodiment is formed by providing an isolation region 20 that reaches the substrate.

  The emitter electrode 9, the base electrode 8, and the collector electrode 7 of the first layer of the unit HBT 101 are formed in a comb shape by an ohmic metal layer. The second-layer emitter electrode 15 and the collector electrode 13 are formed of a wiring metal layer, and the emitter electrode 15 is formed in the same comb shape as the first-layer emitter electrode 9. The collector electrode 13 in the second layer is connected to the collector electrode 13 of another unit HBT 101 by the collector wiring 130 and is connected to the common input terminal pad I. An emitter wiring 150 made of a gold plating layer is formed on the second-layer emitter electrode 15, and is connected to the emitter electrode 15 of the other unit HBT 101 and to the first output terminal pad O1. A gold plating layer is also superimposed on the collector wiring 130.

  The unit HBT 101 connects the emitter electrodes 9 and 15 and the collector electrodes 7 and 13 to the GND pad G serving as the bias point BP in order to draw the base current. The emitter electrode 15 is commonly connected to the first output terminal pad O1 by the emitter wiring 150. Therefore, by connecting the output terminal pad O1 and the GND pad G, the emitter electrodes 9 and 15 can be connected to the bias point BP. The collector electrode 13 is commonly connected by a collector wiring 130. Therefore, the collector electrodes 7 and 13 can be connected to the bias point BP by connecting the collector wiring 130 and the GND pad G via the resistance of the separation element 30. The bias point BP (GND pad G) is disposed on the opposite side of the common input terminal pad I between the first output terminal pad O1 and the second output terminal pad O2 as shown in FIG. With this arrangement, a bias potential can be applied to the emitter electrode and the collector electrode of the unit HBT 101 without particularly securing a new space.

  The drain electrode 10 and the source electrode 11 in the first layer of the unit FET 102 are formed in an island shape by an ohmic metal layer. The second drain electrode 16 is formed in an island shape by a wiring metal layer. A drain wiring 160 made of a gold plating layer is formed on the drain electrode 16 of the second layer, and is connected to the drain electrode of another unit FET 102 and connected to the power supply terminal pad V.

  The unit HBT 101 and the unit FET 102 are disposed adjacent to each other via the isolation region 20, and the base electrode 8 of the unit HBT 101 and the source electrode 11 of the unit FET 102 are connected by a connection wiring 17 formed of a wiring metal layer. The unit element 100 is configured.

  A gate electrode 12 made of a gate metal layer is provided in the impurity region 23 between the source electrode 11 and the drain electrode 10. The gate electrode 12 is connected to the gate electrode 12 of another unit FET 102 by a gate wiring 120 made of a wiring metal layer, and is connected to the first control terminal pad C1 via the control resistor R1.

  A resistor serving as a separation element 30 is connected between the first output terminal pad O1 and the ground terminal pad G. In addition, a resistor serving as the separation element 30 is also connected between the power supply terminal pad V and the drain wiring 160 and between the common input terminal pad I and the ground terminal pad G. The separation element prevents leakage of high frequency signals.

  The resistance of the control resistor R1 and the isolation element 30 is the impurity region 23 isolated by the isolation region 20.

  A peripheral impurity region 170 is provided around each pad and around the gate wiring 120 to improve isolation.

  FIG. 3 shows an enlarged plan view of the unit element 100.

  A plurality of semiconductor layers are stacked on a compound semiconductor substrate to form unit HBT 101 and unit FET 102.

  As will be described later, the unit HBT 101 is formed by mesa-etching each semiconductor layer in a desired pattern to form each semiconductor layer that becomes an emitter layer and a base layer in a mesa shape.

  The ohmic metal layer (AuGe / Ni / Au) provides the first emitter electrode 9 and the collector electrode 7 connected to the emitter layer and the collector layer, respectively, and the ohmic metal layer (Pt / Ti / Pt / Au) provides a base. A base electrode 8 connected to the layer is formed. The emitter electrode 9 and the collector electrode 7 are provided in a comb shape. A base electrode 8 is arranged around the emitter electrode 9 in the center as hatched. Two collector electrodes 7 are arranged on the subcollector layer outside the base electrode 8.

  On the emitter electrode 9 and collector electrode 7 of the first layer, the emitter electrode 15 and collector electrode 13 of the second layer are provided by a wiring metal layer (Ti / Pt / Au) overlapping therewith. The second-layer emitter electrode 15 has a comb shape similar to that of the first layer. The second-layer collector electrode 13 is continuous with the collector wiring 130. The base electrode 8 has a single-layer structure with only an ohmic metal layer. On the emitter electrode 15 of the second layer, an emitter wiring 150 is provided by a gold plating layer.

  As will be described later, the unit FET 102 is provided on the same substrate and semiconductor layer as the unit HBT 101. The semiconductor layer is mesa-etched in a desired pattern, and each semiconductor layer to be a contact layer and a channel layer is formed in a mesa shape.

  The ohmic metal layer (AuGe / Ni / Au) provides a first drain electrode 10 and a source electrode 11 that are in contact with each layer. On the surface of the channel layer between the drain electrode 10 and the source electrode 11, a gate electrode 12 is provided by a gate metal layer (Pt / Mo). The gate electrode 12 extends between the island-shaped source electrode 11 and the drain electrode 10 in a direction orthogonal to the extending direction of each electrode of the comb-shaped unit HBT 101.

  The operation region of the unit FET 102 in which the drain electrode 10, the source electrode 11, and the gate electrode 12 are disposed is formed on the impurity region 23 obtained by separating the semiconductor layer by the separation region 20. Since the isolation region 20 is an insulating region by ion implantation of B + or the like, the region other than the isolation region 20 becomes the impurity region 23 in this embodiment.

  On the drain electrode 10 of the first layer, the drain electrode 16 of the second layer is provided by a wiring metal layer (Ti / Pt / Au). On the drain electrode 16 of the second layer, a drain wiring 160 is provided by a gold plating layer.

  The gate electrode 12 extends outside the operation region and is connected to the gate wiring 120 formed of a wiring metal layer. The gate wiring 120 connects the gate electrodes 12 to each other and is connected to the control terminal. An isolation region 20 is also arranged around the gate wiring.

  On the source electrode 11 of the first layer, a connection wiring 17 made of a wiring metal layer is provided. The connection wiring 17 connects the source electrode 11 of the unit FET 102 and the base electrode 8 of the unit HBT 101.

The unit FET 102 and the unit HBT 101 are provided on the same substrate.
Some semiconductor layers are formed in a mesa shape and are separated by a space. A region that is not mesa-etched is separated by a separation region 20 by ion implantation, such as a two-dot chain line. That is, the unit HBT 101 and the unit FET 102 are arranged adjacent to each other via the isolation region 20 provided on the same substrate and semiconductor layer, and the base electrode 8 of the HBT 101 and the source electrode 11 of the FET 102 are connected by the connection wiring 17.

  The unit element 100 of this embodiment includes a unit HBT 101 having a minimum unit mesa structure having an emitter electrode 9, a base electrode 8, and a collector electrode 7 as indicated by a broken line, and a pair of a source electrode 11, a gate electrode 12, and a drain electrode 10. The unit FETs 102 are connected and arranged close to each other. The base layer and the collector layer of the unit HBT 101 are continuous with the corresponding semiconductor layer of the unit FET 102, respectively.

The first switching element SW1 is a unit element 100 connected in parallel. That is, collector electrodes 13 and 7 of each unit HBT 101 are connected to each other by collector wiring 130, and emitter electrodes 15 and 9 of each unit HBT 101 are connected to each other by emitter wiring 150. The collector electrodes 7 and 13 are shared by the adjacent unit elements 100. Further, the gate electrodes 120 of the unit FETs 102 are connected to each other by the gate wiring 120 of the FET 102, and the gate wiring 120 of the FET 102 is connected to the first control terminal Ctl1. The drain electrodes 10 and 16 of the unit FETs 102 are connected to each other by the drain wiring 160 and are connected to the power supply terminal V _DD .

  Here, the base electrode 8 of the unit HBT 101 and the source electrode 11 of the unit FET 102 are connected by the connection wiring 17 in one unit element 100, but in a layout in which a plurality of unit elements 100 are arranged in a comb shape, The base electrodes 8 and the source electrodes 11 of the FET 102 are not directly connected.

  4A and 4B are diagrams illustrating the unit element 100. FIG. 4A is a cross-sectional view taken along the line aa in FIG. 3, FIG. 4B is a perspective view of the unit HBT 101, and FIG. FIG. In FIG. 4, the electrodes of the second and higher layers other than the connection wiring 17 are omitted.

  As shown in FIG. 4A, a plurality of semiconductor layers, that is, an n + GaAs layer 2, an nInGaP layer 3, a p + GaAs layer 4, an nInGaP layer 5, and an n + GaAs layer 6 are stacked on a semi-insulating GaAs substrate 1. A part of the semiconductor layer is removed by etching to form a mesa shape. A separation region 20 reaching the substrate 1 is also provided. The isolation region is an insulating region 20 by ion implantation of B + or the like.

  The unit element 100 is separated into two regions by the mesa-like semiconductor layer and the insulating region 20, the unit HBT 101 is formed in one region, and the unit FET 102 is formed in the other region.

FIG. 4B is a perspective view of the unit HBT 101 when the unit element is cut into the two regions in the cross section indicated by the line cc in FIG. Here, the connection electrode 17 is omitted. The sub-collector layer 2 of the unit HBT 101 is an n + GaAs layer formed on the substrate 1 by an epitaxial growth method and doped with silicon (Si) at a relatively high impurity concentration of ³ to 6E18 cm ⁻³ . Its film thickness is several thousand mm. The collector layer 3 is an nInGaP layer formed on a partial region of the subcollector layer 2 and doped to an impurity concentration of about 1 to 5E17 cm ⁻³ by silicon doping. The film thickness is 1000 to 5000 mm. The base layer 4a is a p + GaAs layer formed on the collector layer 12 and doped to an impurity concentration of about 1 to 50E18 cm ⁻³ by carbon (C) doping. The film thickness is several hundred to 2,000 mm. The emitter layer 5a is an n-type InGaP layer formed on a partial region of the base layer 4a and doped to an impurity concentration of about 1 to 5E17 cm ⁻³ by silicon doping. The film thickness is 1000 to 5000 mm. The emitter layer 5a is lattice-matched with the upper and lower GaAs layers. The emitter contact layer 6a is an n + GaAs layer formed on the emitter layer 5a and doped to an impurity concentration of about ³ to 6E18 cm ⁻³ by silicon doping, and has a film thickness of several thousand Å.

  The unit HBT 101 of this embodiment forms an InGaP / GaAs heterojunction with the collector layer 3 and the base layer 4a in addition to forming an InGaP / GaAs heterojunction with the emitter layer 5a and the base layer 4a. is doing. A transistor is operated in a forward direction in which the emitter layer 5a operates as an emitter (hereinafter referred to as forward transistor operation) and in a reverse direction in which the emitter layer 5a operates as a collector (hereinafter referred to as reverse transistor operation). Each structural parameter is controlled so that the characteristics are substantially the same, and the collector-emitter voltage is operated at 0 V, and the collector-emitter current is operated at a bias around 0 A. In this embodiment, an HBT in which the emitter and the collector are symmetric with respect to the base as described above (hereinafter, symmetric HBT) is employed. The symmetric HBT will be described in detail later.

  The semiconductor layer that becomes the emitter layer 5a and the collector layer 3 may be an AlGaAs layer instead of the InGaP layer, and in this case, lattice matching with the GaAs layer of the base layer 4a.

  An insulating region 20 for separation is provided in the vicinity of the surface S1 'below the base layer 4a.

  On the surface of the subcollector layer 2, a first collector electrode 7 made of an ohmic metal layer (AuGe / Ni / Au) is disposed at a position sandwiching the collector layer 3. A base electrode 8 made of an ohmic metal layer (Pt / Ti / Pt / Au) is arranged on the surface of the base layer 4a in a pattern surrounding the emitter layer 5a. A first emitter electrode 9 made of an ohmic metal layer (AuGe / Ni / Au) is disposed on the emitter contact layer 6a.

  FIG. 4C is a perspective view of the unit FET 102 when the unit element is cut along the cross section indicated by the line cc in FIG. The unit FET 102 uses the nInGaP layer 5 as the channel layer 5b. The uppermost n + GaAs layer 6 is used as contact layers 6bs and 6bd. The contact layers 6bd and 6bs become the drain region and the source region of the FET, respectively. The contact layers 6bd and 6bs are also formed in a mesa shape, and the gate electrode 12 is provided on the channel layer 5b exposed between them. On the contact layers 6bd and 6bs, the first drain electrode 10 and the source electrode 11 are formed by ohmic metal layers, respectively.

  A p-type buffer layer 4b is disposed below the channel layer 5b. The p-type buffer layer 4b is a p + GaAs layer, and this layer can prevent carriers leaking from the channel to the substrate side.

  Note that the layer below the p + GaAs layer 4 is a layer that does not particularly affect the operation of the FET, so that the characteristics of the unit HBT 101 may be designed to be optimum.

  The unit element 100 shown in FIG. 4A has a structure in which the surface S1 'of the unit HBT 101 shown in FIG. 4B and the surface S1 of the unit FET 102 shown in FIG. The contact surface is the surface of line cc in FIG. A connection wiring 17 is provided on the source electrode 11 of the unit FET 102 by a wiring metal layer (Ti / Pt / Au). The connection wiring 17 extends along the mesa of the unit FET 102 and over the insulating region 20 to the base electrode 8 of the unit HBT 101.

  Here, the mesa shape and the wiring direction will be described.

  When wet etching is employed for GaAs mesa etching, the crystal plane affects the mesa shape. As the relationship between the crystal direction and the mesa shape, the mesa shape when tracing the surface of the etching step in the direction parallel to the direction of [01 bar 1 bar] (hereinafter referred to as [01-1-) is a forward mesa shape (trapezoidal shape). Shape). Further, the mesa shape when the etching step surface is traced in the direction perpendicular to the [01-1-] direction is an inverted mesa shape (overhang shape).

  That is, for example, when the wiring metal layer moves up and down the mesa step, a step coverage problem occurs depending on the mesa shape or the extending direction of the wiring metal layer.

  When the metal layer extends in a direction parallel to the [01-1-] direction and moves up and down the mesa step, the step coverage problem does not occur because the metal layer has a forward mesa shape. However, when the wiring extends in the direction perpendicular to the [01-1-] direction and goes up and down the mesa level difference, it has an inverted mesa shape, which causes a step coverage problem.

  In this embodiment, a mesa is simultaneously formed in the region of the unit FET 102 by mesa etching for forming the emitter contact layer 6a and the emitter layer 5a of the unit HBT 101. That is, in FIG. 3, the emitter mesa EM is formed simultaneously.

  In addition, a mesa is simultaneously formed in the region of the unit FET 102 by mesa etching for forming the base layer 4a and the collector layer 3 of the unit HBT 101. That is, in FIG. 3, the base mesa BM is a mesa formed at the same time.

  Therefore, the connection wiring 17 connecting the source electrode 11 of the unit FET 102 and the base electrode 8 of the unit HBT 101 moves up and down the emitter mesa EM, and the gate wiring 120 moves up and down the base mesa BM.

  Therefore, in this embodiment, the connection wiring 17 and the gate wiring 120 are aligned in the direction in which the mesa is raised and lowered, and both extend in the direction parallel to the [01-1-] direction (the direction of the arrow in the figure).

  The n + GaAs layer 6 and the nInGaP layer 5 have a mesa shape and are separated by a space. On the other hand, the layer below the p + GaAs layer 4 is separated by an isolation region (insulating region) 20. That is, the base layer 4a, the collector layer 3, and the subcollector layer 2 of the unit HBT 101 are electrically separated from the buffer layer 4b, the n-GaAs layer 3, and the n + GaAs layer 2 of the unit FET 102, but structurally. Is continuous. The unit HBT 101 and the unit FET 102 are arranged adjacent to each other with the isolation region 20 interposed therebetween.

  In the present embodiment, the unit FET 102 and the unit HBT 101 are connected in proximity to each other for each unit element 100. The stacked structure of the semiconductor layers of the unit HBT 101 and the unit FET 102 is the same, and the base layer 4a, the collector layer 3, and the sub-collector layer 2 of the unit HBT 101 are each continuous with the corresponding semiconductor layer of the unit FET 102. Therefore, heat generated by the operation of the unit HBT 101 can be transmitted to the FET 102. Since the drain current of the unit FET 102 has a negative temperature coefficient, the base current of the unit HBT 101 also has a negative temperature coefficient. Therefore, the heat generation of the unit HBT 101 reduces the collector current of the unit HBT 101.

  In general, an HBT can potentially have a very high current density and a very low on-resistance Ron compared to a HEMT. However, the HBT has a problem that current is concentrated on one unit element due to a positive feedback action due to temperature and is destroyed by secondary breakdown. For this reason, the current density cannot actually be increased sufficiently. In order to solve this problem, generally, a countermeasure is always taken to insert an emitter ballast resistor or a base ballast resistor in the comb-like unit element of the HBT. However, when an emitter ballast resistor or a base ballast resistor is inserted, a new problem arises that the high-frequency characteristics are degraded accordingly.

  However, according to the present embodiment, a temperature-compensated switch circuit device can be realized without taking a method of deteriorating high-frequency characteristics such as an emitter ballast resistor and a base ballast resistor as a countermeasure against secondary breakdown.

Since the characteristics of the base-emitter voltage V _{BE -base} current of the HBT have a positive coefficient with respect to temperature, the unit element may have a base-emitter relative to other unit elements due to some design non-uniformity factor. The inter-voltage V _BE bias may be applied slightly larger. As a result, a large amount of base current and collector current flow, and it is a normal secondary breakdown process to flow more base current and collector current than when the temperature rises. However, in the unit element 100 of the present embodiment, the secondary breakdown process is not actually started. The unit FET 102 supplies the base current of the unit HBT 101 of the unit element 100. Unlike the unit HBT 101, the unit FET 102 has a negative temperature coefficient with respect to the temperature. Further, since the unit HBT 101 and the unit FET 102 are close to each other, the heat of the generated unit HBT 101 is transmitted to the adjacent unit FET 102 and the source current of the unit FET 102 is reduced. Since the source and base are connected, the source current of the unit FET 102 becomes the base current of the unit HBT 101. That is, the source current of the unit FET 102 decreases due to the heat generation of the unit HBT 101, and the base current of the unit HBT 101 decreases. As a result, the collector current of the unit HBT 101 decreases, and conversely, the unit HBT 101 cools. That is, as a result, occurrence of secondary breakdown can be prevented.

  By adopting such a mechanism, it is possible to prevent the occurrence of secondary breakdown without adding any factors that degrade the high-frequency characteristics such as emitter ballast resistance and base ballast resistance. Can be significantly increased. As a result, the on-resistance Ron of the first and second switching elements SW1 and SW2 can be made very small, and the insertion loss of the switch MMIC can be made very small.

Since the HEMT generally used in the switch MMIC is a unipolar device, the HBT is a bipolar device, so that the current density can be greatly increased and the on-resistance Ron can be extremely reduced. Further, by using the above-described symmetrical HBT as the unit HBT 101, the current consumption between the collector and the emitter is reduced to zero, so that an energy saving operation is possible. The reason is that the collector-emitter voltage can be biased to 0V in the symmetric HBT 101 in the same manner as the drain-source voltage is biased to 0V in the HEMT.
FIG. 5 is a characteristic diagram of a symmetric HBT. As described above, the unit HBT may be a symmetric HBT. Figure symmetric HBT, the collector at a given base current _{I B} - shows the V-I curve of the emitter voltage _{V CE} and the collector current Ic.

In a given base current I _B collector - called emitter voltage V _CE and the collector current Ic is positive (+) value sequentially transistor transistor shown a negative (-) value transistor of the opposite transistor shown a.

As shown in FIG. 5A, the symmetric HBT has an on-resistance Ron (= ΔV _CE / ΔI _C ) during forward transistor operation and an on-resistance Ron ′ (= ΔV _CE ′ / ΔI _C ′) during reverse transistor operation. It is HBT comprised so that it might become substantially equal. In order to realize this, the emitter layer 5a and the collector layer 3 have basically the same structure. For example, when an InGaP layer is used for the emitter layer 5a, an InGaP layer is also used for the collector layer 3. When InGaP layers are used for the emitter layer 5a and the collector layer 3, they are lattice-matched with the GaAs layers (sub-collector layer 2 and emitter contact layer 6a), respectively. Further, when AlGaAs layers are used for the emitter layer 5a and the collector layer 3, the molar ratio of Al is made the same.

  Then, the impurity concentration of the emitter layer 5a and the impurity concentration of the collector layer 3 are set to substantially the same value. As a result, the base-collector breakdown voltage is lower than that of a normal HBT. However, in the switch circuit device, a base-collector breakdown voltage of 7 to 8 V is sufficient.

  The symmetrical HBT can operate with a collector-emitter voltage of 0 A by operating the collector-emitter voltage with a bias of 0V.

The rising voltage of the forward transistor (same as the rising voltage of the reverse transistor) is preferably 0 V as shown in FIG. However, as shown in FIG. 5B, the forward voltage of the forward transistor may not be 0 V but may have an offset voltage V _OFF . In this case, when the bias collector-emitter voltage V _CE to 0V, and the collector - slight current consumption occurs in the emitter.

  In many cases, the symmetric HBT has basically the same structure of the emitter and the collector. Therefore, the offset voltage of the symmetric HBT is very small compared to the non-symmetrical HBT. However, there may be an offset voltage although it is small. This is caused by a band spike at the bottom of the conduction band at the base-emitter and base-collector heterojunction. In order to eliminate the band spike, a grading layer may be provided.

  FIG. 6 is a cross-sectional view for explaining another structure of the unit HBT 101.

  FIG. 6A shows a structure having a grading layer in order to eliminate band spikes.

For example, an Al _0.3 Ga _0.7 As layer is employed for the emitter layer 5 a and the collector layer 3. Then, the grading layer 32 is disposed between the base and the emitter and between the base and the collector. That is, an n-type Al _X Ga _1-X As (X = 0 → 0.3) layer gradually changing from GaAs to Al _0.3 Ga _0.7 As is disposed between the base and the emitter, and the base-collector is arranged. For example, an n-type Al _X Ga _1-X As (X = 0.3 → 0) layer that gradually changes from Al _0.3 Ga _0.7 As to GaAs is disposed. Thereby, the offset voltage can be further reduced extremely.

  FIG. 6B shows a case where a ballast resistor layer is inserted. Depending on the design of the FET 102 and the HBT 101 constituting the unit element 100, secondary breakdown may not be sufficiently prevented. In addition, when a very large current is passed through the HBT 101, the occurrence of secondary breakdown cannot be completely avoided. In such a case, it is better to take measures against secondary breakdown by putting a ballast resistance layer in the epi structure of HBT 101.

  That is, because of the symmetrical type, the n-GaAs layer 33 is disposed as a ballast resistance layer on the emitter layer 5a side and the collector layer 3 side. Since the n-GaAs layer 33 having a predetermined resistance value becomes a ballast resistance layer, it is possible to prevent the occurrence of secondary breakdown due to current concentration on one unit element.

  The ballast resistor layer 33 may be formed of a non-doped GaAs layer, or may be an n-InGaP layer or a non-doped InGaP layer when the emitter layer 5a is an InGaP layer. When the emitter layer 5a is an AlGaAs layer, the ballast resistor layer 33 may be formed of an n-AlGaAs layer or a non-doped AlGaAs layer. The other semiconductor layers are the same as those in FIG.

  FIG. 6C shows the case where the heterojunction is shifted from the emitter-base pn junction, and the emitter layer 5a is an n-type AlGaAs layer.

  As a general HBT structure, the emitter-base pn junction between the n-type AlGaAs layer of the emitter layer 5a and the p-type GaAs layer of the base layer 4a coincides with the heterojunction. In this case, a band spike is present at the bottom of the conduction band, and this band spike is one of the causes of the offset voltage generation. In order to prevent generation of an offset voltage due to a band spike, an n-type GaAs layer 5a ′ is added between the base layer 4a (p-type GaAs layer) and the emitter layer 5a (n-type AlGaAs layer), thereby locating the heterojunction position. It may be shifted from the pn junction position between the so-emitters. Further, since it is a symmetric type HBT 101, an n-type GaAs layer 3 ′ is further added between the base layer 4a (p-type GaAs layer) and the collector layer 3 (n-type AlGaAs layer), so that the heterojunction position is between the base and the collector. It may be shifted from the pn junction position. In this case, since the heterojunction position does not coincide with the pn junction between the emitter and the base and the pn junction between the collector and the base, the offset voltage can be made very small.

  As the principle of HBT, in order not to inject holes in the base to the emitter side, an AlGaAs layer having a band gap larger than that of the GaAs layer as the base layer 4a is arranged as the emitter layer 5a.

  In the case of this structure, the junction between the added nGaAs layer 5a 'and the emitter nAlGaAs layer 5a positioned thereon is a heterojunction. Similarly, the junction between the added nGaAs layer 3 'and the nAlGaAs layer 3 as the collector layer located therebelow becomes a heterojunction.

  Further, the on-resistances Ron and Ron ′ may be slightly different as an asymmetry other than the offset voltage. The cause is the difference between the emitter parasitic resistance and collector parasitic resistance. In that case, the impurity concentration and thickness of the emitter layer 5a, the collector layer 3, and further the emitter contact layer 6a and the subcollector layer 2 may be adjusted so that the on-resistances Ron and Ron 'are equal.

In this embodiment, the symmetric HBT is used for the unit HBT 101 to constitute a switch circuit device. As a result, a switch circuit with a current consumption between the collector and the emitter of 0 A is realized. Furthermore, in the symmetric HBT, the on-resistance Ron during forward transistor operation and the on-resistance Ron ′ during reverse transistor operation are substantially equal, so that the collector-emitter voltage _VCE is positive in the amplitude of the high-frequency signal, and the collector-emitter voltage V _A switch circuit with good linearity can be obtained at the switching portion where _CE is negative.

The switch circuit using GaAs MESFET or HEMT has a drain-source bias of 0 V, so that the drain-source consumption current is 0 A, and the drain-source voltage V _DS is positive in the amplitude of the high-frequency signal. The linearity is good at the switching portion where the _VDS is negative. That is, the switch circuit device of this embodiment has the same advantages as the GaAs MESFET and HEMT switch circuit devices. Further, the on-resistance of the bipolar device HBT is overwhelmingly lower than that of the unipolar device FET, and when a switch circuit is formed, the high frequency characteristics are greatly improved, and the chip size can be greatly reduced.

  FIG. 7 shows a cross-sectional view of the pad and the wiring. 7A and 7B are cross-sectional views taken along the line dd in FIG. 2, and FIG. 7C is a cross-sectional view taken along the line ee in FIG.

  The common input terminal pad I, the first output terminal pad O1, the first control terminal pad C1 (the same applies to the second switching element SW2 side), the power supply terminal pad V, the pad P serving as the ground terminal pad G, and the gate wiring 120 are shown in FIG. It is provided on the subcollector layer (n + GaAs) layer. The pad P and the gate wiring 120 are provided on the subcollector layer 2 through the nitride film 51 (FIG. 7B) or directly provided on the subcollector layer 2 so as to form a Schottky junction with the surface of the subcollector layer 2. It is formed (FIGS. 7A and 7C).

  Therefore, as a countermeasure against isolation around the pad P and the gate wiring 120, a peripheral impurity region 170 (impurity region 23) is disposed around the pad P and the gate wiring 120. The impurity region 23 of the present embodiment is formed by being separated by the insulating region 20 as described above.

  Next, a second embodiment of the present invention will be described with reference to FIGS.

  The second embodiment is a switch circuit device that can operate with one control terminal by providing a logic circuit.

  FIG. 8 is a circuit diagram. The circuit diagram shows a schematic diagram similar to FIG. 1A, but the first and second switching elements SW1 and SW2 are actually configured as shown in FIG. 1B.

  FIG. 8A shows a case where an inverter circuit 41 having a resistance load is connected as a logic circuit. That is, a resistance load 411 and a GaAs MESFET 412 (pinch-off voltage Vp = 0V: enhancement type) are connected in series at a connection point CP, and the connection point CP, for example, the gate of the FET2 of the second switching element SW2 is connected to the control resistor R2. Connect through. The gate of the MESFET 412 is connected to one control terminal Ctl.

  FIG. 8B shows a case where an inverter circuit 41 of enhancement type / depletion type DCFL (Direct Coupled FET Logic) is connected as a logic circuit. That is, the source and gate of the depletion type MESFET 413 (pinch-off voltage Vp = −1V) and the drain of the enhancement type MESFET 414 (pinch-off voltage Vp = 0 V) are connected in series at the connection point CP, and the connection point CP and, for example, the gate of the FET 2 are connected. Connection is made via a control resistor R2. Also, the gate of the enhancement type MESFET 414 is connected to one control terminal Ctl. In FIG. 8, the other components are the same as those in the first embodiment, and thus description thereof is omitted.

  By connecting the inverter circuit 41 in this way, the control signal applied to the control terminal Ctl is applied to the gate of the FET1 of the first switching element SW1, and the complementary signal of the control signal is the gate of the FET2 of the second switching element SW2. To be applied. That is, the control terminal can be made one by the SPDT switch MMIC.

  The logic circuit 41 can also be formed of a resistor and / or MESFET. That is, the switch MMIC with the built-in logic circuit can be integrated on one chip of the GaAs substrate.

  FIG. 9 shows the inverter circuit 41 of the enhancement type / depletion type DCFL shown in FIG. 9A is a plan pattern diagram, and FIG. 9B is a cross-sectional view taken along the line ff of FIG. 9A.

  In the D-type FET 413, the first gate electrode 127 is disposed between the source electrode 135d and the drain electrode 136d of the second layer made of the wiring metal layer. Below the source electrode 135d and the drain electrode 136d, a first source electrode 115d and a drain electrode 116d made of an ohmic metal layer are disposed, and the operation region is separated by the separation region 20 indicated by a two-dot chain line. The source electrode 115d and the drain electrode 116d are connected to the contact layers 6bsd and 6bdd, respectively.

  The first gate electrode 127 is disposed between the source electrode and the drain electrode, and is connected to the second-layer source electrode 135d outside the operation region.

In the E-type FET 414, the second source electrode 135e and the drain electrode 136e made of a wiring metal layer are alternately arranged, and the second gate electrode 128 is arranged therebetween.
Below the source electrode 135e and the drain electrode 136e, a first source electrode 115e and a drain electrode 116e made of an ohmic metal layer are disposed. The source electrode 115e and the drain electrode 116e are connected to the contact layers 6bse and 6bde, respectively.

  The drain electrode 136e of the second layer at the end of the E-type FET 414 (same as the drain electrode 116e of the first layer) is shared with the source electrode 135d of the second layer of the D-type FET 413 (same as the source electrode 115d of the first layer). is doing. Similarly, the drain contact layer 6bde at the end of the E-type FET 414 is shared with the source contact layer 6bsd of the D-type FET 413.

  The cross-sectional structure is the same as that of the unit FET 102 shown in FIG. 4C, but the deposition thicknesses of Pt of the first and second gate electrodes 127 and 128 made of the gate metal layer (Pt / Mo) are different, The embedding depth in the channel layer 5b is appropriately selected to realize a predetermined pinch-off voltage Vp.

  FIG. 10 is a schematic circuit diagram showing the third embodiment. The third embodiment is an SP3T (Single Pole Throw Through) switch MMIC.

  The SP3T includes a first switching element SW1, a second switching element SW2, and a third switching element SW3. The first switching element SW1, the second switching element SW2, and the third switching element SW3 are each an HBT group in which three HBTs are connected in series. The collector at one end of the first switching element SW1, the collector at one end of the second switching element SW2, and the collector at one end of the third switching element SW3 are connected to the common input terminal IN.

  The first switching element SW1 is formed by connecting HBT1-1, HBT1-2, and HBT1-3 in series. Further, FET1-1, FET1-2, and FET1-3 corresponding to HBT1-1, HBT1-2, and HBT1-3, respectively, are provided. FET1-1, FET1-2, and FET1-3 are MESFETs, and the source is These are connected to the bases of HBT1-1, HBT1-2, and HBT1-3, respectively. The gates of the FET 1-1, FET1-2, and FET1-3 are connected to the first control terminal Ctl1 through the control resistors R11, R12, and R13, respectively. FIG. 10 is a circuit schematic diagram similar to FIG. 1A, and the actual connection between the HBT 1-1 and the FET 1-1 is the connection indicated by the first switching element SW1 in FIG.

  Similarly, the bases of HBT2-1, HBT2-2, and HBT2-3 constituting the second switching element SW2 are connected to FET2-1, FET2-2, and FET2-3, respectively, and the gates are connected to control resistors R21, R22. , R23 to the second control terminal Ctl2.

  The bases of HBT 3-1, HBT 3-2, and HBT 3-3 constituting the third switching element SW 3 are also connected to FET 3-1, FET 3-2, and FET 3-3, respectively, and each gate is connected via control resistors R 31, R 32, and R 33. To the third control terminal Ctl3.

  Further, the emitters at the other ends of the first switching element SW1, the second switching element SW2, and the third switching element SW3 are connected to the first output terminal OUT1, the second output terminal OUT2, and the third output terminal OUT3, respectively.

The control signal applied to the first, second, and third control terminals Ctl1, Ctl2, and Ctl3 is H level or L level, and the FET to which the H level signal is applied is turned on to supply current to the base of the switching element. Supply. As a result, the switching element is turned on to form a signal path, and the high-frequency analog signal input to the common input terminal IN is transmitted to the output terminal corresponding to the turned on switching element. The resistors are arranged for the purpose of preventing leakage of high-frequency signals via the gate electrodes with respect to the DC potentials of the control terminals Ctl1, Ctl2, and Clt3 that are AC grounded. In addition, the isolation element 30 between the collector and emitter of each HBT and GND, and the isolation element 30 between the drain and V _{DD of} each FET all use inductors. Since other components are the same as those in the first embodiment, description thereof is omitted.

The switch circuit device of FIG. 10 has an on-voltage (base-emitter voltage) V _BE of the HBT of 1.6 V, for example, and the pinch-off voltage Vp of the FET is 0 V. Therefore, the control terminal is based on the potential of the emitter and collector of the HBT. Both the FET and the HBT start to turn on when the potential of becomes higher than 1.6V. Therefore, in the switching element that is turned on when 3V is applied to the control terminal, since the separation element 30 is an inductor, the voltage drop due to the base current flowing through the inductor is 0V, and the HBT and FET are sufficiently turned on. Between the emitter and collector of the switching element. On the other hand, since 0V is applied to the control terminal on the off side, it can withstand 1.6V amplitude power. At this time, since the SP3T has a three-stage configuration, an amplitude of 1.6 V corresponds to a power of 29.6 dBm, and can be sufficiently used for CDMA mobile phone applications. Further, both the emitter and the collector of each HBT are connected to the GND potential, and are used for drawing the base current of each HBT. In a high power application such as a switch circuit device for a CDMA mobile phone, since the base current for driving the HBT is large, an inductor that does not drop a voltage due to the base current flowing is used as the separation element 30.

Since all the HBTs 101 of the embodiment of the present invention are symmetrical, the emitter and collector of the HBT 101 may be interchanged in the first, second, and third embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS (A) The circuit schematic diagram for demonstrating this invention, (B) The circuit diagram. It is a top view for demonstrating this invention. It is a top view for demonstrating this invention. It is (A) sectional drawing, (B) perspective view, and (C) perspective view for demonstrating this invention. It is a characteristic view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is a circuit diagram for demonstrating this invention. It is (A) top view and (B) sectional drawing for demonstrating this invention. It is a circuit schematic diagram for explaining the present invention. It is (A) circuit diagram and (B) sectional drawing for demonstrating the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 Subcollector layer 3 Collector layer 4a Base layer 5a Emitter layer 6a Emitter contact layer 7, 13 Collector electrode 8 Base electrode 9, 15 Emitter electrode 4b P-type buffer layer 5b Channel layer 6bs, 6bd, 6bse, 6bde, 6bsd , 6bdd Contact layer 10, 16 Drain electrode 11 Source electrode 12 Gate electrode 17 Connection wiring 20 Separating region 23 Impurity region 30 Separating element 32 Grading layer 33 Ballast resistor layer 41 Inverter circuit 51 Nitride film 100 Unit element 101 Unit HBT
102 unit FET
115, 135, 115e, 115d, 135e, 135d Source electrode electrode 116, 136, 116e, 116d, 136e, 136d Drain electrode 120 Gate wiring 127 First gate electrode 128 Second gate electrode 130 Collector wiring 150 Emitter wiring 160 Drain wiring 411 Resistance 412 MESFET
413 D-type FET
414 E-type FET
CP connection point SW1 first switching element SW2 second switching element SW3 third switching element IN common input terminal OUT1 first output terminal OUT2 second output terminal OUT3 third output terminal Ctl control terminal Ctl1 first control terminal Ctl2 second control terminal Ctl3 Third control terminal

Claims (14)

A compound semiconductor substrate in which a plurality of semiconductor layers forming at least one heterojunction are stacked;
A first transistor provided on the substrate, the collector layer, the base layer, and the emitter layer as the semiconductor layers, and a collector electrode, a base electrode, and an emitter electrode;
A second transistor provided on the substrate and having a gate electrode, a source electrode, and a drain electrode;
A unit element in which the first transistor and the second transistor are arranged adjacent to each other via an isolation region, and the base electrode of the first transistor and the source electrode of the second transistor are connected;
A plurality of switching elements in which the unit elements are connected in parallel;
A first RF port commonly connected to collector electrodes or emitter electrodes of the plurality of switching elements;
A plurality of second RF ports respectively connected to an emitter electrode or a collector electrode of the plurality of switching elements;
A power supply terminal connected to each of the drain electrodes of the plurality of switching elements,
A control signal is applied to each gate electrode of the second transistor, the first transistor is driven by a current supplied by conduction of the second transistor, and a signal path is formed between the first and second RF ports. A switch circuit device.   One unit element includes the drain electrode, the gate electrode, and the emitter electrode and the collector electrode of the second transistor in parallel with the corresponding electrodes of the other unit elements, respectively. The switch circuit device according to claim 1, wherein the switch circuit devices are connected in common.   2. The switch circuit device according to claim 1, wherein the emitter layer and the channel layer of the second transistor are provided in the same semiconductor layer.   The said each electrode of the said 1st transistor is provided in the comb shape, and it extends in a 1st direction, The said gate electrode of the said 2nd transistor is extended in a 2nd direction, The 1st aspect is characterized by the above-mentioned. The switch circuit device described.   The first transistor has a heterojunction between the emitter layer and the base layer and the base layer and the collector layer, and has an on-resistance value during forward transistor operation and an on-resistance value during reverse transistor operation as one base. 2. The switch circuit device according to claim 1, wherein current values are substantially equal.   2. A logic circuit connected to each gate electrode of the plurality of second transistors and at least one control terminal, and a control signal is applied to each gate electrode from the one control terminal. The switch circuit device according to 1.   The switch circuit device according to claim 1, wherein another switching element is connected in series to the switching element in multiple stages.   The switch circuit device according to claim 1, wherein the base layer is a p + GaAs layer.   The switch circuit device according to claim 1, wherein the emitter layer is an InGaP layer or an AlGaAs layer.   The switch circuit device according to claim 1, wherein the collector current of the first transistor has a negative temperature coefficient.   2. The switch circuit device according to claim 1, wherein bias points for applying an equal bias potential to the emitter electrode and the collector electrode of the switching element are connected to each other.   12. The switch circuit device according to claim 11, wherein separation elements for high-frequency signals are connected between the emitter electrode of the switching element and the bias point, and between the collector electrode of the switching element and the bias point, respectively.   2. The switch circuit device according to claim 1, wherein a high-frequency signal separation element is connected between the power supply terminal and the second transistor.   The switch circuit device according to claim 1, wherein the semiconductor layer serving as the base layer and the collector layer is continuous with the second transistor.