JP2006041057A - Metamorphic semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability by eliminating disconnection of wiring caused by large stepping of a semiconductor element due to a metamorphic buffer layer in a semiconductor device with a non-grating matching semiconductor element. <P>SOLUTION: The metamorphic buffer layer 20 on a base body 1 has its extension area 20R formed outside a formation part for a semiconductor element across an inter-element separation groove 41 to reduce a substantial step between the semiconductor element and another part adjacent thereto, thereby improving reliability of an insulating layer, a wire, etc., against the stepping. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a metamorphic semiconductor device in which a semiconductor element is formed on a substrate via a metamorphic buffer layer.

  In a semiconductor device such as a semiconductor integrated circuit having a heterojunction bipolar transistor (hereinafter referred to as HBT), a buffer layer 101 is provided on the semiconductor substrate 100 as necessary, as shown in a schematic sectional view in FIG. Then, the sub-collector layer 102, collector layer 103, base layer 104, emitter layer 105, and emitter cap layer (emitter contact layer) 106 constituting the HBT element are sequentially epitaxially grown, and the emitter cap layer 106, emitter layer 105, The base layer 104 and the collector layer 103 are etched to expose a part of the sub-collector layer 102 on the surface, where a collector electrode 107C is formed, and the emitter cap layer 106 and the emitter layer 105 are etched to form one part of the base layer 104. Part exposed on the surface , Here, the base electrode 107B is formed, composed of the emitter electrode 107E on the emitter cap layer 105 is formed.

In this HBT, when a so-called lattice-matched HBT is formed, that is, each semiconductor layer lattice-matched to the substrate 100 is epitaxially grown, for example, on the base 100 made of InP. For example, when forming an InP-based lattice-matched HBT, the buffer layer 101 is not interposed on the semiconductor substrate 100, or a sufficiently thin buffer layer 101 may be formed.
In the conventional structure, the HBT is separated from the other by removing the subcollector layer 102 other than the HBT element forming portion together with the buffer layer 101 by etching.

For example, in HBT, element isolation is performed by forming an isolation groove in the collector layer (see Patent Document 1).
Further, for example, in a HEMT (High Electron Mobility Transistor), etching is performed across the buffer layer simultaneously with etching for element isolation (see Patent Document 2).
However, the conventional structure employs a structure in which the buffer layer is removed except for the element forming portion.

  By the way, in an InP-based HBT, when the semiconductor substrate 100 is a GaAs substrate, for example, and a lattice-mismatched semiconductor layer is epitaxially grown thereon, the buffer layer 101 is shown as a schematic cross-sectional view in FIG. A metamorphic buffer layer 201 (see, for example, Patent Document 1) is used, and lattice matching is achieved by the interposition of the metamorphic buffer layer 201.

The metamorphic buffer layer is made of, for example, InAlAs, InGaAs, or InP, and its composition changes in the thickness direction sequentially.
However, such a metamorphic buffer layer 201 has a large thickness of, for example, 1.5 μm.
Normally, the thickness of epitaxial growth having an HBT transistor configuration is about 1 μm, and therefore, compared with the thickness h 0 from the base 100 of the lattice-matched InP-based HBT of FIG. 10 to the emitter cap layer 106 of FIG. A similar thickness h1 for a lattice mismatched HBT is about twice as large as that for a lattice matched HBT.

Therefore, for example, when this HBT is covered and an organic insulating layer such as polyimide or BCB (benzocyclobutene) is applied as an interlayer insulating layer or a surface protective layer, the insulating layer is disconnected due to a large step. In addition, when an upper layer wiring is formed thereon, for example, this step causes a drop in the wiring, resulting in a decrease in reliability. In this case, when the film thickness of the polyimide or BCB described above is sufficiently large so as to flatten the surface, the step becomes large at the opening of the scribe line, and coverage for film formation in the next process is increased. I have a problem.
Japanese Unexamined Patent Publication No. 2000-114271 (FIG. 2). JP 2002-252345 A

  The present invention provides a metamorphic semiconductor device in which a metamorphic buffer layer having a large thickness is used because it is necessary to sufficiently relax the strain as an underlayer on which the above-described non-lattice matching epitaxial growth is performed. It is an object of the present invention to provide a metamorphic semiconductor device capable of avoiding a decrease in reliability based on the step due to the presence of the above-described metamorphic buffer layer.

  A metamorphic semiconductor device according to the present invention is a metamorphic semiconductor device having a semiconductor element in which a semiconductor epitaxial growth layer is formed on a substrate via a metamorphic buffer layer, and the first element is included in the metamorphic buffer layer. An inter-separation groove is formed, and an extension region of the metamorphic buffer layer is provided outside the semiconductor element formation portion with the first inter-element separation groove interposed therebetween.

In addition, the present invention is characterized in that a passive element is provided on the extension region of the metamorphic buffer layer.
In addition, the present invention is characterized in that the passive element is formed on the metamorphic buffer layer via an inorganic insulating film and / or an organic insulating film.
Further, the present invention is characterized in that the passive element is constituted at least partially by the same epitaxial growth layer as the epitaxial growth layer constituting the semiconductor element.

Further, the present invention is characterized in that the semiconductor element is a heterojunction bipolar transistor.
According to the present invention, the semiconductor element is a heterojunction bipolar transistor, and the subcollector layer of the heterojunction bipolar transistor is stacked on the metamorphic buffer layer.
The present invention is also characterized in that the semiconductor element is a heterojunction bipolar transistor, and the passive element is a resistance element having a resistance layer in the same epitaxial growth layer as the subcollector layer constituting the heterojunction bipolar transistor. To do.

Further, the present invention is characterized in that the first inter-element separation groove is selected to have a depth reaching the base.
Further, the present invention is characterized in that the width W and the depth D of the first isolation trench are selected so that W ≦ D.
Further, the present invention is characterized in that a second element isolation groove is formed in the semiconductor epitaxial growth layer, and the first element isolation groove is formed independently of the second element isolation groove. And
Furthermore, the present invention is characterized in that an organic insulating film is formed on the surface.

The present invention is characterized in that the semiconductor element is an InP lattice-matched heterojunction bipolar transistor, and the substrate is a non-lattice-matched semiconductor substrate for InP.
The present invention is characterized in that the collector layer of the heterojunction bipolar transistor is an InP-based semiconductor layer.
The present invention is characterized in that the collector layer of the heterojunction bipolar transistor is an InGaAs-based or InGaP-based semiconductor layer.

As described above, in the present invention, in the metamorphic semiconductor device, the metamorphic buffer layer is formed not only in a portion where a semiconductor element is formed by simply performing lattice matching as usual, but also in an element isolation groove. Since the metamorphic buffer layer extends outside the semiconductor element formation portion, that is, adjacent to the semiconductor element formation portion, with the inter-element separation groove interposed therebetween, as described at the beginning. Even if a thick metamorphic buffer layer is present in the semiconductor element forming portion, the thick metamorphic buffer layer is disposed adjacent to the semiconductor element forming portion. In the semiconductor element body, that is, other HBTs, the step is limited to the thickness above the subcollector layer 102 in FIG. It can be.
For this reason, when the surface is covered with, for example, an organic insulating layer, for example, an interlayer insulating layer, the generation of defects in the interlayer insulating layer due to this step, the short circuit with the upper layer wiring, and the occurrence of disconnection in the upper layer wiring are avoided. It is possible to improve reliability and yield.

In the present invention, a passive element, for example, a resistor, a capacitor, an inductor, and the like can be disposed in the extending portion of the metamorphic buffer layer. In this case, since the metamorphic buffer layer exists here, Further, since a stable semiconductor layer can be formed, a highly reliable passive element as designed can be configured.
That is, for example, a stable semiconductor layer formed simultaneously with the growth of the same semiconductor layer as the collector layer of the HBT of the semiconductor element, that is, has a stable specific resistance.

  The inter-element isolation groove formed in the metamorphic buffer layer has a width equal to or less than the depth thereof, and unevenness occurs in, for example, the insulating layer formed thereon due to the presence of the inter-element isolation groove. Can be effectively avoided.

Embodiments of a metamorphic semiconductor device according to the present invention will be described with reference to the drawings.
FIG. 1 is a schematic plan view of an embodiment when applied to an InP-based HBT of a metamorphic semiconductor device according to the present invention, and FIG. 2 is a schematic cross-sectional view along the line XX.
Note that the InP-based HBT indicates that each semiconductor layer constituting the transistor operation unit has a configuration capable of lattice matching with InP as usual.

  In the example of FIGS. 1 and 2, a metamorphic buffer layer 20 of InAlAs, InGaAs, or InP is epitaxially grown to a thickness of, for example, about 1.5 μm on a base 1 made of a GaAs semiconductor substrate. As is well known, the composition of the metamorphic buffer layer 20 is changed sequentially from the bottom to the top, and the distortion of non-lattice matching with the substrate 1 of the semiconductor layer epitaxially grown thereon is reduced. It has the composition to do.

  Subsequently, on the metamorphic buffer layer 20, a sub-collector layer 2 having a thickness of about 300 nm of, for example, InGaAs or InP having a high impurity concentration of the first conductivity type, for example, n-type, and a thickness of, for example, n-type, for example, InGaAs or InP, for example Collector layer 3 having a thickness of about 500 nm, base layer 4 having a second conductivity type such as p-type InGaAs or InGaSb, for example 50 nm, base layer 4 having n-type InP or InAlAs, for example, an emitter layer 5 having a thickness of 50 nm, n-type having a high impurity concentration The emitter cap layer (emitter contact layer) 6 having a thickness of about 150 nm made of, for example, InGaAs is formed by, for example, continuous MOCVD (Metal Organic Chemical Vapor Deposition).

An emitter mesa EM is formed by etching the emitter cap layer 6 and the emitter layer 5 in a predetermined pattern.
Also, the base layer 4 and the collector layer 5 are etched leaving the emitter mesa EM on the upper surface to form a base mesa BM.
Further, the sub-collector layer 2 surrounds the base mesa BM, and an element isolation groove (referred to as a second element isolation groove) is formed by etching to a depth over the entire thickness of the sub-collector layer 2 as usual. .

  In the present invention, the element isolation groove (referred to as the first element isolation groove) 31 reaches the base 1 outside the second element isolation groove 32 with respect to the metamorphic buffer layer 20. The metamorphic buffer layer 20 is left inside and outside the inter-element isolation trench 31.

In this way, a semiconductor element as an active element in which the subcollector layer 2, the base mesa BM, and the emitter mesa EM are formed on the substrate 1 via the metamorphic buffer layer 20, that is, in this example, the HBT is the subcollector layer. The second second inter-element separation groove 32 is formed so as to be separated from the others as usual.
In the present invention, the extended region 20R formed by the metamorphic buffer layer 20 separated by the first inter-element isolation groove 31 is disposed on the outer periphery of the semiconductor device by the HBT, for example, on the entire outer periphery. It is.

The first inter-element isolation groove 21 of the metamorphic buffer layer 20 can be narrowly selected in a range where the insulation between the elements is maintained, for example, 1 μm or more, and this width is 3.5 μm. Hereinafter, for example, it is desirable that W ≦ D with respect to 1.5 μm to 2 μm or the depth D.
This is to prevent a groove from being generated on the surface of the insulating layer due to the presence of the first inter-element separation groove 21 in the application of an insulating layer such as BCB described later.

  As usual, the collector electrode 7C, the base electrode 7B, and the emitter electrode 7E for the subcollector layer 2, the base layer 4, and the emitter cap layer 6 in the HBT are respectively ohmic contact electrodes made of a metal layer having a Ti / Pt / Au structure, for example. Can be configured.

Further, as described above, the method for manufacturing the HBT can be performed by a normal method until the etching process for the subcollector layer 2.
The formation of the first inter-element isolation groove 21 for the metamorphic buffer layer 20 is preferably performed by dry etching using anisotropic etching. In this way, the narrow first inter-element isolation groove 21 is formed. be able to. This is because the metamorphic buffer layer is inferior in crystallinity, and therefore, when wet etching is performed, it is difficult to form a narrow and good first element isolation groove 21 by side etching. Subsequently, the substrate 1 is etched by 100 nm or more.

  The non-lattice-matched HBT according to the present invention has an extension region 20R due to the metamorphic buffer layer around the HBT, although the thick metamorphic buffer layer 20 exists in the HBT. The difference in height from the surroundings is substantially a thickness not including the buffer layer 101 at the small height ho shown in FIG. 10 depending on the thickness of the element body.

Then, as shown in FIG. 3, for example, an organic coating film BCB is applied on the substrate 1, and an insulating layer 40 constituting, for example, an interlayer insulating film is formed over the entire surface of the HBT.
At this time, the width W of the first inter-element isolation groove 31 is 1 μm or more and 3.5 μm or less, for example, 1.5 μm to 2 μm, or W ≦ D with respect to the depth D, as described above. As a result, it was avoided that a recess was formed on the surface of the insulating layer 40 in the portion where the first inter-element isolation groove 31 was formed in the insulating layer 40.
In FIG. 3, parts corresponding to those in FIG.

  As described above, according to the configuration of the present invention, the level difference between the HBT formation part and the other part can be reduced, and the surface of the insulating layer 40 can be formed gently, so that the generation of defects due to the level difference of the insulating layer itself. In addition, by avoiding disconnection of, for example, wiring formed on the semiconductor device, a highly reliable semiconductor device can be configured.

  In this way, according to the present invention, a highly reliable non-lattice-matched, for example, InP-based HBT can be configured, so that, for example, disconnection of wirings formed on the insulating layer 40 can be avoided. A highly reliable semiconductor device is formed.

As described above, according to the present invention, since a semiconductor device having an InP-based HBT having a highly reliable non-lattice matching can be configured, for example, the collector layer 3 is made of InP having a large band gap and a high breakdown voltage. When the InP-based HBT is used, the breakdown voltage can be improved and the collector layer 3 can be configured as an InP-based HBT made of In _0.47 Ga _0.53 As that is excellent in high speed. Can constitute a semiconductor device having an HBT excellent in high-speed performance.
That is, since an InP-based HBT having excellent characteristics according to the purpose of use can be configured, the present invention is suitable for application to various semiconductor integrated circuits having such an InP-based HBT as a semiconductor element. .

  Further, in the semiconductor device according to the present invention, for example, as shown in FIG. 4, a passive element as a circuit element of a semiconductor integrated circuit is formed on the insulating layer 40 on the portion where the extension region 20R of the metamorphic buffer layer is formed. An element 41 such as a resistor R, a capacitor C, an inductor L, etc. can be formed.

In the example shown in FIG. 4, a resistor R is formed. In this case, a resistor layer 41R having a required pattern is formed by a semiconductor layer having a required specific resistance, and electrodes 42 are formed at both ends, for example.
In this example, the insulating layer 40 has a two-layer structure in which a planarized lower insulating layer 40A made of an organic insulating layer such as BCB is formed, and an upper insulating layer 40B made of SiN and SiO ₂ is formed thereon. In this case, the surface of the insulating layer 40 can be formed more entirely and more flatly.
Therefore, in this case, the configuration of the passive element 41, for example, the resistance layer in the resistor R shown in the figure, the dielectric layer in the other passive elements, the inductance, etc. on the flat insulating layer 40 on the extending region 20R of the metamorphic buffer layer 20 It is possible to avoid the occurrence of step breakage in the layer and to configure the passive element 41 as a circuit element having excellent reliability.

Alternatively, as shown in FIG. 5, as the insulating layer 40, for example, an inorganic insulating layer such as SiN or SiO ₂ is coated, and a flat surface is formed on the extending portion 20R of the metamorphic buffer layer. The element 41 can be formed.
Even in this case, in the present invention, the reliability of the insulating layer 40 is high because the step between the HBT of the semiconductor element and the other part is small as described above, so that the reliability of the semiconductor device is improved. be able to.

Further, in the present invention, as shown in FIG. 6, a lower insulating layer 40A made of an organic insulating layer made of BCB, for example, is formed so as to cover the HBT forming portion of the semiconductor element, and the upper insulating layer made of the above-mentioned inorganic insulating layer, for example, is formed thereon. This is a case where the layer 40B is formed and the insulating layer 40B is formed on the extending region 20R of the metamorphic buffer layer 20 by the above-described inorganic insulating layer such as SiN or SiO ₂ .
In this way, the unevenness of the surface is reduced by the lower insulating layer 40A, and the organic insulating layer is formed thereon, whereby the coverage of the insulating layer 40 can be improved.

  As described above, when the circuit element is formed on the extension region 20R of the metamorphic buffer layer, the first and second inter-element separation grooves 31 even if the metamorphic buffer layer 20 has some conductivity. And 32 are formed, the parasitic capacitance between the HBT of the semiconductor element and the passive element 41 can be ignored.

  Further, as shown in FIG. 7, the passive element 41 can be directly formed on the extending region 20R of the metamorphic buffer layer without using an insulating layer. In this case, for example, the sub-collector layer 2 of HBT is left, and thereby the resistance layer 41R of the resistance element R can be configured, for example. Even in this case, the inter-element separation groove 31 does not generate a leakage current between the HBT and the passive element, and does not cause any trouble in the circuit operation between the HBT and the passive element.

In some cases, as shown in FIG. 8, the subcollector extension region 2R in which the subcollector layer 2 is left is formed on the extension region 20R of the metamorphic buffer layer 20, and the first and The second inter-element separation grooves 31 and 32 can be formed at the same time, that is, at the same position, for example, in the manufacturing process of the HBT.
In this way, by forming the stacked portion of the metamorphic buffer layer and the subcollector layer outside the HBT, that is, the semiconductor element formation portion, the step difference between the semiconductor element formation portion and the other portion can be further reduced. Can do.

4 to 8, parts corresponding to those in FIGS. 1 to 3 are denoted by the same reference numerals, and redundant description is omitted.
As described above, according to the configuration of the present invention, it is possible to improve the reliability by improving the step, and since the thickness of the insulating layer can be improved, the problem of the scribe line can be improved. It is intended.

In each of the above-described examples, the semiconductor element has been described with respect to the HBT. However, the semiconductor element is not limited to the HBT, and can be applied to, for example, a HEMT (High Electron Mobility Transistor).
FIG. 9 is a schematic cross-sectional view of an example of this case. In this case, an InP-based HEMT that is non-lattice matched to the substrate 1 is used. In this case, the HEMT is also formed on the metamorphic buffer layer 20. For example, a buffer layer 50 made of InAlAs, a channel layer 51 made of InGaAs, for example, an electron supply layer made of InAlAs and a contact layer 52 are formed by epitaxial growth.

53G, 53S and 53D are a gate electrode made of Pt / Ti / Pt / Au, a source electrode and a drain electrode made of AuGe / Ni, for example.
Also in this case, the first inter-element isolation groove 21 is formed in the metamorphic buffer layer 20 formed on the substrate 1 made of GaAs, for example, as in the above-described HBT, and the metamorphic structure is formed around the semiconductor element made of HBT. A similar effect can be achieved by providing the extended region 20R with the Fick buffer layer 20.
9, parts corresponding to those in FIGS. 1 to 8 are denoted by the same reference numerals, and redundant description is omitted.

Further, the present invention can be applied to a semiconductor device having various semiconductor elements on which a metamorphic buffer layer is formed other than the above-described HBT and HEMT, and the same effect can be obtained.
In addition, it goes without saying that the substrate 1 can take various forms in the present invention, for example, Si can be used, and the metamorphic buffer layer can be applied to GaAs.

  As described above, in the configuration of the present invention, a step is formed as a whole by forming the same semiconductor layer as the metamorphic buffer layer serving as a base of the semiconductor element in the vicinity of the semiconductor element forming portion in the vicinity thereof. Therefore, a highly reliable metamorphic semiconductor device can be configured.

It is a schematic plan view of an example of a metamorphic semiconductor device according to the present invention. It is sectional drawing of the XX line of FIG. It is a schematic plan view of an example of a metamorphic semiconductor device according to the present invention. It is a schematic plan view of an example of a metamorphic semiconductor device according to the present invention. It is a schematic plan view of an example of a metamorphic semiconductor device according to the present invention. It is a schematic plan view of an example of a metamorphic semiconductor device according to the present invention. It is a schematic plan view of an example of a metamorphic semiconductor device according to the present invention. It is a schematic plan view of an example of a metamorphic semiconductor device according to the present invention. It is a schematic plan view of an example of a metamorphic semiconductor device according to the present invention. It is a schematic plan view of a conventional heterojunction semiconductor device. It is a schematic plan view of a conventional heterojunction semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,100 ... Base | substrate, 2,102 ... Subcollector layer, 2R ... Extension area | region of a subcollector layer, 3,103 ... Collector layer, 4,104 ... Base layer, 5, 105 ... emitter layer, 6,106 ... emitter cap layer, 7B, 107B ... base electrode, 7C, 107C ... collector electrode, 20,201 ... metamorphic buffer layer, 20R ... metamol Extension region of the Fick buffer layer, 7E, 107E... Emitter electrode, 31... First inter-element isolation groove, 32... Second inter-element isolation groove, 40. 40B ... Upper and lower insulating layers, 42 ... Electrodes, 41 ... Passive elements, 41R ... Resistance layers, BM ... Base mesa, EM ... Emitter mesa

Claims (14)

A metamorphic semiconductor device having a semiconductor element in which a semiconductor epitaxial growth layer is formed on a substrate via a metamorphic buffer layer,
A first inter-element isolation groove is formed in the metamorphic buffer layer, and an extension region of the metamorphic buffer layer is provided outside the semiconductor element formation portion with the first inter-element isolation groove interposed therebetween. A metamorphic semiconductor device characterized by the above.   The metamorphic semiconductor device according to claim 1, wherein a passive element is provided on the extension region of the metamorphic buffer layer.   The metamorphic semiconductor device according to claim 2, wherein the passive element is formed on the metamorphic buffer layer via an inorganic insulating film and / or an organic insulating film.   The metamorphic semiconductor device according to claim 2, wherein the passive element is formed at least partially by the same epitaxial growth layer as the epitaxial growth layer constituting the semiconductor element.   The metamorphic semiconductor device according to claim 1, wherein the semiconductor element is a heterojunction bipolar transistor.   4. The metamorphic semiconductor device according to claim 3, wherein the semiconductor element is a heterojunction bipolar transistor, and a subcollector layer of the heterojunction bipolar transistor is stacked on the metamorphic buffer layer.   5. The semiconductor element according to claim 4, wherein the semiconductor element is a heterojunction bipolar transistor, and the passive element is a resistance element having a resistance layer in the same epitaxial growth layer as the subcollector layer constituting the heterojunction bipolar transistor. Metamorphic semiconductor devices.   The metamorphic semiconductor device according to claim 1, wherein the first inter-element isolation groove is selected to have a depth reaching the base.   2. The metamorphic semiconductor device according to claim 1, wherein a width W and a depth D of the first inter-element isolation trench are selected such that W ≦ D.   2. The device according to claim 1, wherein a second element isolation groove is formed in the semiconductor epitaxial growth layer, and the first element isolation groove is formed independently of the second element isolation groove. The metamorphic semiconductor device described.   The metamorphic semiconductor device according to claim 1, wherein an organic insulating film is formed on the surface.   2. The metamorphic semiconductor device according to claim 1, wherein the semiconductor element is an InP lattice-matched heterojunction bipolar transistor, and the base is a non-lattice-matched semiconductor base for InP.   The metamorphic semiconductor device according to claim 12, wherein the collector layer of the heterojunction bipolar transistor is an InP-based semiconductor layer. The metamorphic semiconductor device according to claim 12, wherein the collector layer of the heterojunction bipolar transistor is an InGaAs or InGaP semiconductor layer.

Images